WO2002099871A3 - Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform - Google Patents

Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform Download PDF

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Publication number
WO2002099871A3
WO2002099871A3 PCT/DE2002/002044 DE0202044W WO02099871A3 WO 2002099871 A3 WO2002099871 A3 WO 2002099871A3 DE 0202044 W DE0202044 W DE 0202044W WO 02099871 A3 WO02099871 A3 WO 02099871A3
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WO
WIPO (PCT)
Prior art keywords
plastic housing
semiconductor chips
injection
producing
modification plate
Prior art date
Application number
PCT/DE2002/002044
Other languages
English (en)
French (fr)
Other versions
WO2002099871A2 (de
Inventor
Andreas Woerz
Thomas Zeiler
Original Assignee
Infineon Technologies Ag
Andreas Woerz
Thomas Zeiler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Andreas Woerz, Thomas Zeiler filed Critical Infineon Technologies Ag
Priority to EP02740387A priority Critical patent/EP1393364A2/de
Priority to JP2003502880A priority patent/JP2004528729A/ja
Priority to US10/478,682 priority patent/US20040175866A1/en
Priority to KR10-2003-7015897A priority patent/KR20040012896A/ko
Publication of WO2002099871A2 publication Critical patent/WO2002099871A2/de
Publication of WO2002099871A3 publication Critical patent/WO2002099871A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01052—Tellurium [Te]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Die Erfindung betrifft ein Kunststoffgehäuse (14) mit mehreren Halbleiterchips (3) sowie eine Umverdrahtungsplatte (11), auf der die Halbleiterchips (3) angeordnet sind, und eine Spritzgussform zur Herstellung des Kunststoffgehäuses (14) sowie ein elektronisches Bauteil, das mit Hilfe der Kombination aus Spritzgussform, Umverdrahtungsplatte (11) und Kunststoffgehäuse (14) herstellbar wird. Ferner betrifft die Erfindung ein Verfahren, das unter Verwendung der erfindungsgemässen Umverdrahtungsplatte (11) und der zweiteiligen Spritzgussform die Herstellung eines derartigen Kunststoffgehäuses (14) mit mehreren Halbleiterchips (3) für mehrere elektronische Bauteile ermöglicht.
PCT/DE2002/002044 2001-06-05 2002-06-05 Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform WO2002099871A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02740387A EP1393364A2 (de) 2001-06-05 2002-06-05 Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform
JP2003502880A JP2004528729A (ja) 2001-06-05 2002-06-05 複数の半導体チップ、および配線ボードを有する樹脂パッケージ、ならびにこの樹脂パッケージを射出成形用金型によって製作する方法
US10/478,682 US20040175866A1 (en) 2001-06-05 2002-06-05 Plastic housing comprising several semiconductor chips and a wiring modification plate, and method for producing the plastic housing in an injection-molding mold
KR10-2003-7015897A KR20040012896A (ko) 2001-06-05 2002-06-05 플라스틱 패키지, 배선 보드, 주입 몰드, 전자 구성 요소,플라스틱 패키지 생성 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10127009.7 2001-06-05
DE10127009A DE10127009A1 (de) 2001-06-05 2001-06-05 Kunststoffgehäuse mit mehreren Halbleiterchips und einer Umverdrahtungsplatte sowie ein Verfahren zur Herstellung des Kunststoffgehäuses in einer Spritzgußform

Publications (2)

Publication Number Publication Date
WO2002099871A2 WO2002099871A2 (de) 2002-12-12
WO2002099871A3 true WO2002099871A3 (de) 2003-03-06

Family

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Family Applications (1)

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PCT/DE2002/002044 WO2002099871A2 (de) 2001-06-05 2002-06-05 Kunststoffgehäuse mit mehreren halbleiterchips und einer umverdrahtungsplatte sowie ein verfahren zur herstellung des kunststoffgehäuses in einer spritzgussform

Country Status (7)

Country Link
US (1) US20040175866A1 (de)
EP (1) EP1393364A2 (de)
JP (1) JP2004528729A (de)
KR (1) KR20040012896A (de)
DE (1) DE10127009A1 (de)
TW (1) TW558813B (de)
WO (1) WO2002099871A2 (de)

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TW567562B (en) 2001-01-15 2003-12-21 Chuen Khiang Wang Method of packaging microchip devices, the interposer used therefor and the microchip device packaged thereby
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DE10320579A1 (de) 2003-05-07 2004-08-26 Infineon Technologies Ag Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
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US20070292708A1 (en) * 2005-08-12 2007-12-20 John Pereira Solder composition
DE102005046737B4 (de) 2005-09-29 2009-07-02 Infineon Technologies Ag Nutzen zur Herstellung eines elektronischen Bauteils, Bauteil mit Chip-Durchkontakten und Verfahren
DE102008032330A1 (de) 2008-07-09 2010-01-14 Akro Plastic Gmbh Verfahren zur Herstellung von montagefertigen, kunststoffumspritzten Elektronikbauteilen bzw. Elektronikbaugruppen
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Publication number Publication date
DE10127009A1 (de) 2002-12-12
US20040175866A1 (en) 2004-09-09
KR20040012896A (ko) 2004-02-11
TW558813B (en) 2003-10-21
WO2002099871A2 (de) 2002-12-12
EP1393364A2 (de) 2004-03-03
JP2004528729A (ja) 2004-09-16

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