WO2002049036A1 - Matrice memoire - Google Patents
Matrice memoire Download PDFInfo
- Publication number
- WO2002049036A1 WO2002049036A1 PCT/JP2001/010995 JP0110995W WO0249036A1 WO 2002049036 A1 WO2002049036 A1 WO 2002049036A1 JP 0110995 W JP0110995 W JP 0110995W WO 0249036 A1 WO0249036 A1 WO 0249036A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dummy
- line
- memory array
- memory
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/229—Timing of a write operation
Definitions
- the present invention relates to memory arrays. Background art
- MC0, MC1, MC (n-1), and MCn are memory cells, each of which is a switching transistor (M0
- S-FET It is composed of Q and capacitor C connected in series.
- WL0, WL1, WL2n, WL (2n + 1) are the memory cells 00, 1 ⁇ [J1, MC (n-l)., Respectively.
- Word line for activating M Cn is BL and BLB are bit lines forming a pair in which complementary logic voltages are interchanged during data writing.
- V L is the memory cell M C0, M C1,
- a cell plate voltage line for applying a cell plate voltage V cp ( VccZ 2) to the capacitor C side of M C (n ⁇ 1) and M Cn.
- the cell plate voltage line VL is connected to a cell plate voltage generation circuit (not shown).
- each switching transistor (M ⁇ S-FET) Q and the capacitor C of 1) is connected between the bit line B L 'and the cell plate voltage line VL, and each switching transistor Q Control terminal (gate) power ⁇ Connected to word lines WL0, WL2, WL2n.
- the capacitor C side is connected to the cell plate voltage line VL.
- the memory cells MC1, MC3, MCn A series circuit of the switching transistor Q and the capacitor C is connected between the bit line BLB and the cell plate voltage line VL, and the control terminal (gate) of each switching transistor Q and the lead line W
- the capacitor C side is connected to the cell plate voltage line VL.
- a sense amplifier SA is connected between the bit lines BL and BLB.
- the equalizing circuit EQ is connected between the bit lines BL and BLB.
- This equalizing circuit EQ includes M0S-FETQ1, Q2, and Q3.
- the drain and source of M0S—FETQ3 are connected to bit lines BL and BLB, respectively.
- the bit line precharge voltage Vpr is supplied to the bit lines BL and BLB, and the gate signal PEQ for equalizing the bit lines BL and BLB is applied to each of the MOS-FETQ1, Q2 and Q3. Applied to gate.
- the cell plate voltage lines VL of the plurality of circuits are connected to a common cell plate voltage generation circuit.
- the memory cell MC 0 When the memory cell MC 0 is activated, that is, when its MOS FETQ is 0 N, the following read operation and write operation are performed.
- the data “0” is supplied to the sense amplifier SA through the M0S—FETQ and the bit line BL, and is then spread and latched. As shown in FIG. 6B, the voltage of the bit line BL is It becomes 0 (V).
- the data "1" is invertedly written to the sense amplifier SA, then amplified and latched, and the voltage of the bit line BL is inverted to Vcc (V) as shown in FIG. 6B.
- the data "1” is transmitted through the bit line BL and the MOS-FETQ of the memory cell MC0, and then the canon. Rewritten to Sita C.
- the voltage of the word line WL0 is at a high level
- the voltage of the word line WL1 is also at a high level
- the latch state of the sense amplifier SA at the time of reading and writing is performed.
- the voltage of the bit line BL is the reverse voltage of the voltage of the bit line BLB.
- the data stored in the activated memory cell is read out, supplied to the sense amplifier SA through the bit line, amplified and latched, and then transmitted to the sense amplifier SA.
- the voltage of the bit lines BL and BLB is reversed by the inverted writing of the data and then the width and latching, the following operation is performed. That is, coupling noise is applied to the cell plate voltage line VL through the capacitor of the activated memory cell.
- a pair of bit lines BL and BLB is provided, but generally, a plurality of pairs of bit lines BL and BLB are provided.
- the cell plate voltage lines VL corresponding to the bit lines BL and BLB of each pair are connected to a common cell plate voltage generation circuit. Therefore, the voltage of the bit lines connected to the same word line and connected to a plurality of memory cells that are activated at the same time is changed from 0 (V) to Vcc (V).
- the present invention provides a plurality of pairs of first and second bit lines in which mutually complementary logic voltages are interchanged during data writing, and a plurality of pairs of first and second lead lines.
- a first memory cell connected between each of the first bit lines, each of the first ground lines and the common cell plate voltage line, and a second of the second memory cells.
- a second memory cell connected between the bit line, each second lead line and the common cell plate voltage line, and a sense amplifier connected between the first and second bit lines of each pair
- a memory array in which a plurality of first and second memory cells are arranged in a matrix, it is possible to avoid occurrence of a coupling noise on a cell plate voltage line. They try to suggest something.
- a plurality of pairs of first and second bit lines in which mutually complementary logic voltages are interchanged at the time of data writing, and a plurality of pairs of first and second lead lines are shared.
- a first memory cell connected between each cell plate voltage line, each first bit line, each first ground line, and a common cell plate voltage line, and each second bit line
- a second memory cell connected between each second lead line and a common cell plate voltage line, and a sense amplifier connected between the first and second bit lines of each pair.
- a second memory cell connected between each second bit line, a second dummy line, and a common cell plate voltage line;
- the timing at which the first and second dummy gate lines transition from the active state to the inactive state is determined by the second and first memory modules. This is a memory array that is delayed for a predetermined time from the timing when the active line goes from the active state to the inactive state.
- each of the first and second lead lines and the second and first dummy lead lines have transitioned from an active state to an inactive state.
- a memory array provided with a means for applying a precharge voltage.
- a fourth invention is the memory array according to the first, second, or third invention, wherein the memory array is a memory array that is a dynamic RAM.
- FIG. 1 is a circuit diagram illustrating an example of a memory array according to an embodiment of the present invention.
- FIG. 2 is a timing chart for explaining the operation of the memory array of FIG.
- FIG. 3 is a circuit diagram showing another example of the memory array according to the embodiment of the present invention.
- FIG. 4 is a timing chart for explaining the operation of the memory array of FIG.
- FIG. 5 is a circuit diagram showing a conventional example of a memory array.
- FIG. 6 is a timing chart for explaining the operation of the memory array of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- MC0, MC1, MC (n-1), and MCn are memory cells each having a switching transistor (M0S-FET) Q and a capacitor C connected in series.
- M0S-FET switching transistor
- (2n + 1) are the memory cells MC0, MC1,.
- BL and BLB are bit lines forming a pair in which complementary logic voltages are interchanged when writing data.
- a series circuit of the switching transistors (MOS-FET) Q of the memory cells MC 0, MC 2, MC (n ⁇ 1) and the capacitor C is connected between the bit line BL and the cell plate voltage line VL.
- the control terminals (gates) of the respective switching transistors Q are connected to the lead lines WL0, WL2, W
- the capacitor C side is connected to the cell plate voltage line VL.
- the capacitor C side is connected to the cell plate voltage line VL.
- a sense amplifier SA is connected between the bit lines BL and BLB.
- the equalizing circuit EQ is connected between the bit lines BL and BLB.
- This equalizing circuit E Q has MOS FET Q 1, Q 2 and Q 3.
- the drain and source of M0S—FETQ3 are connected to bit lines BL and BLB, respectively.
- the gate signal P EQ for supplying the bit line precharge voltage Vpr to the bit lines B L and B L B and for equalizing the bit lines B L and B L B is given by MOS-F E T Q
- dummy memory cells DMC0 and DMC1 having the same configuration as the memory cells MC0 and MCI are provided.
- Dummy memory cell DMC 0 A switching circuit (M 0 S—: FET) Q and a series circuit of the capacitor C are connected between the bit line BL and the cell plate voltage line VL, and the control terminal (the gate terminal) of the switching transistor Q is connected. ) Is connected to the dummy line DWL0 for activating the dummy memory cell DMC0. In this case, the capacitor C side is connected to the cell plate voltage line VL.
- a series circuit of a switching transistor and a capacitor of the dummy memory cell DMC1 is connected between the bit line BLB and the cell plate voltage line VL, and a control terminal (gate) of the switching transistor Q is provided. Connected to a dummy word line DWL 1 for activating the dummy memory cell DMC 1. In this case, the capacitor C side is connected to the cell plate voltage line VL.
- the data "0" stored in the capacitor C of the memory cell MC0, M0S is supplied to the sense amplifier SA through the FETQ and the bit line BL, amplified and latched, and as shown in FIG.
- the voltage of the bit line BL becomes 0 (V).
- the data "1” is inverted and written to the sense amplifier SA, then amplified and latched, and the voltage of the bit line BL is inverted to Vcc (V) as shown in Figure 2C.
- the data "1", the bit line BL and the MOS-FETQ of the memory cell MC0 are rewritten to the capacitor C.
- the lead line WL0 is at a high voltage, as shown in FIG. 2B, the dummy word line to which the MOS-FETQ gate of the dummy memory cell DMC1 is connected is connected.
- the voltage of DWL 1 is also high, and the MOS-FETQ of the dummy memory cell DMC 1 is 00 N.
- the coupling noises of the two have the same level (the same amount), the polarities are opposite to each other, and the coupling noises of the two are cancelled, so that the coupling noise is not superimposed on the cell plate voltage V cp. become.
- the word line WL0 when the word line WL0 is at a high level, the word line WL1 is also at a high level, and in the latch state of the sense amplifier SA at the time of reading and writing, As shown in FIG. 2C, the voltage on the bit line BL is the reverse voltage of the voltage on the bit line BLB. With the transition from reading to writing, as shown in FIG. 2C, the voltage of the bit line BLB changes from Vcc (V) to 0 (V), and passes through the capacitor C of the memory cell MC1. Power ripple noise is superimposed on the cell plate voltage Vcp.
- the nodes between the M0S—FETQ of the dummy memory cells DMC0 and DMC1 and the capacitor C are denoted by NO and N1.
- the gate signal PEQ changes from the low level to the high level as shown in FIG. 4F.
- the M0S-FETs Q1 to Q3 that make up the equalizer circuit EQ are both converted from 0FF to 0N, and as shown in Figure 4C, the bit trains BL and BLB Both voltages are the bit line precharge voltage V pr
- the voltage of the dummy lead line DWL1 can be changed from the high level to the low level simultaneously with the voltage of the lead line WL0.
- the voltage of the dummy line DWL0 can be changed from the high level to the low level simultaneously with the voltage of the word line WL1.
- Figure 4E shows the change in the voltage of node N1.
- the voltage of capacitor C of dummy memory cell DMC1 is equal to Vcc (V) (during reading).
- V) (Writing) Changes to Vpr ( Vcc / 2) (equalizing * precharging).
- the activation timing at which the voltage of the lead line WL0 changes from the low level to the high level is changed to the dummy word line DWL1 Of the dummy lead line DWL 1 in order to minimize the effect on the bit line minute potential difference. May be delayed by the activation timing of the lead line WL0.
- a plurality of pairs of first and second bit lines in which mutually complementary logic voltages are exchanged with each other, and a plurality of pairs of first and second gate lines A first memory cell connected between the common cell plate voltage line, each first bit line, each first pad line and the common cell plate voltage line, and each second cell line.
- a second memory cell connected between the bit line, each second lead line and the common cell plate voltage line, and connected between the first and second bit lines of each pair.
- first dummy first dummy memo connected between lead line and common cell plate voltage line
- a second dummy memory cell connected between each second bit line, second dummy mode line, and common cell plate voltage line, and each first memory cell has a second dummy memory cell.
- the first dummy data having the polarity opposite to that of the second data is written to each first dummy memory cell, so the size of the capacitor is increased, the number of bits is increased, and the speed is increased. Regardless of In addition, power ripple noise can be avoided from being generated in the cell plate voltage line, and power consumption may be increased because the capacity of the cell plate voltage source is not used as a means for avoiding coupling noise. You can get no Mary Array.
- the evening when the first and second dummy gate lines shift from the active state to the inactive state is performed by the second and the second, respectively. Since the first lead line is delayed by a predetermined time from the timing of transition from the active state to the inactive state, the same effect as that of the first invention can be obtained, and the force applied to the cell plate voltage line can be reduced. It is possible to obtain a memory array capable of preventing unnecessary data from being written into each of the first and second dummy memory cells when avoiding occurrence of noise.
- the third aspect in the memory array according to the first aspect, when each of the first and second lead lines and the second and first dummy line transitions from the active state to the inactive state.
- the second and third Dami—switching transistors and cano of the memory cell Since a means for applying a precharge voltage is provided at the middle point of the connection, the same effect as that of the first invention can be obtained, and at the same time, it is possible to avoid occurrence of cutting noise on the cell plate voltage line. In addition, it is possible to obtain a memory array that can prevent unnecessary data from being written into each of the first and second dummy memory cells.
- first, second and third memory arrays are dynamic RA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/203,610 US6768687B2 (en) | 2000-12-15 | 2000-12-14 | Memory array |
EP01270889A EP1343171A4 (en) | 2000-12-15 | 2001-12-14 | MEMORY MATRIX |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000382580A JP2002184173A (ja) | 2000-12-15 | 2000-12-15 | メモリアレイ |
JP2000-382580 | 2000-12-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002049036A1 true WO2002049036A1 (fr) | 2002-06-20 |
Family
ID=18850379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/010995 WO2002049036A1 (fr) | 2000-12-15 | 2001-12-14 | Matrice memoire |
Country Status (5)
Country | Link |
---|---|
US (1) | US6768687B2 (ja) |
EP (1) | EP1343171A4 (ja) |
JP (1) | JP2002184173A (ja) |
KR (1) | KR20030009356A (ja) |
WO (1) | WO2002049036A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004221473A (ja) * | 2003-01-17 | 2004-08-05 | Renesas Technology Corp | 半導体記憶装置 |
JP5189809B2 (ja) * | 2007-09-13 | 2013-04-24 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2009245503A (ja) * | 2008-03-31 | 2009-10-22 | Nec Electronics Corp | 半導体記憶装置 |
US8269203B2 (en) | 2009-07-02 | 2012-09-18 | Actel Corporation | Resistive RAM devices for programmable logic devices |
JP2012160230A (ja) * | 2011-01-31 | 2012-08-23 | Elpida Memory Inc | 半導体装置 |
US10270451B2 (en) | 2015-12-17 | 2019-04-23 | Microsemi SoC Corporation | Low leakage ReRAM FPGA configuration cell |
EP3507808A4 (en) * | 2016-08-31 | 2020-05-27 | Micron Technology, Inc. | MEMORY NETWORKS |
US10147485B2 (en) | 2016-09-29 | 2018-12-04 | Microsemi Soc Corp. | Circuits and methods for preventing over-programming of ReRAM-based memory cells |
DE112017006212T5 (de) | 2016-12-09 | 2019-08-29 | Microsemi Soc Corp. | Resistive Speicherzelle mit wahlfreiem Zugriff |
WO2018132250A1 (en) | 2017-01-12 | 2018-07-19 | Micron Technology, Inc. | Memory cells, arrays of two transistor-one capacitor memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry |
DE112018004134T5 (de) | 2017-08-11 | 2020-04-23 | Microsemi Soc Corp. | Schaltlogik und verfahren zur programmierung von resistiven direktzugriffs-speichervorrichtungen |
KR20190047217A (ko) * | 2017-10-27 | 2019-05-08 | 삼성전자주식회사 | 메모리 셀 어레이에 대한 테스트를 수행하는 메모리 장치 및 이의 동작 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63222385A (ja) * | 1987-03-12 | 1988-09-16 | Toshiba Corp | 半導体記憶装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4791616A (en) * | 1985-07-10 | 1988-12-13 | Fujitsu Limited | Semiconductor memory device |
US5377152A (en) * | 1991-11-20 | 1994-12-27 | Kabushiki Kaisha Toshiba | Semiconductor memory and screening test method thereof |
US6105152A (en) * | 1993-04-13 | 2000-08-15 | Micron Technology, Inc. | Devices and methods for testing cell margin of memory devices |
US6097649A (en) * | 1998-06-01 | 2000-08-01 | Silicon Magic Corporation | Method and structure for refresh operation with a low voltage of logic high in a memory device |
KR100348577B1 (ko) * | 1999-09-30 | 2002-08-13 | 동부전자 주식회사 | 강유전체 메모리 |
-
2000
- 2000-12-14 US US10/203,610 patent/US6768687B2/en not_active Expired - Fee Related
- 2000-12-15 JP JP2000382580A patent/JP2002184173A/ja active Pending
-
2001
- 2001-12-14 KR KR1020027010270A patent/KR20030009356A/ko not_active Application Discontinuation
- 2001-12-14 WO PCT/JP2001/010995 patent/WO2002049036A1/ja not_active Application Discontinuation
- 2001-12-14 EP EP01270889A patent/EP1343171A4/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63222385A (ja) * | 1987-03-12 | 1988-09-16 | Toshiba Corp | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
KR20030009356A (ko) | 2003-01-29 |
JP2002184173A (ja) | 2002-06-28 |
US20030095446A1 (en) | 2003-05-22 |
EP1343171A1 (en) | 2003-09-10 |
EP1343171A4 (en) | 2004-04-21 |
US6768687B2 (en) | 2004-07-27 |
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