WO2002019783A1 - Ensemble carte de circuits imprimes et procede de fabrication associe - Google Patents

Ensemble carte de circuits imprimes et procede de fabrication associe Download PDF

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Publication number
WO2002019783A1
WO2002019783A1 PCT/JP2000/005843 JP0005843W WO0219783A1 WO 2002019783 A1 WO2002019783 A1 WO 2002019783A1 JP 0005843 W JP0005843 W JP 0005843W WO 0219783 A1 WO0219783 A1 WO 0219783A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
electronic component
board unit
sheet
gap
Prior art date
Application number
PCT/JP2000/005843
Other languages
English (en)
Japanese (ja)
Inventor
Makoto Sasaki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2000/005843 priority Critical patent/WO2002019783A1/fr
Publication of WO2002019783A1 publication Critical patent/WO2002019783A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

Definitions

  • the present invention relates to a circuit board unit and a solder having electronic components mounted on a circuit board, and a method of manufacturing the same.
  • a semiconductor bay chip is sealed on a circuit board surface with a covering sheet to maintain a connection state.
  • the new circuit board unit is sealed on a circuit board surface with a covering sheet to maintain a connection state.
  • the circuit board unit is implemented by electronically connecting electronic components to a circuit board. These circuit boards and electronic components expand and contract due to the heat of power consumption during operation and the environmental temperature. On the other hand, these circuit boards and electronic components have different coefficients of thermal expansion. Therefore, in such a circuit board unit, there is a problem that the pad of the circuit board and the bump of the electronic component are easily separated from each other and a conduction failure is easily generated.
  • circuit board unit described in Japanese Patent Application Laid-Open Nos. 633-131647 and 61-232322.
  • circuit board units after electrically connecting the bumps of the electronic component to the pads of the circuit board, a region facing the electronic component and the printed board is filled with a filler.
  • This filler is to reinforce the adhesion between the chip component and the circuit board, and to prevent the adhesion of dust at the connection between the bump of the electronic component and the pad of the circuit board.
  • this filler for example, epoxy resin is used, and the relative dielectric constant of this resin is about 3 to 5.
  • the performance of electronic components is improved, and in particular, when a semiconductor chip that performs signal processing of several 10 GHz is mounted, there is a problem that the dielectric constant of such a filler causes a delay in signal propagation speed. Therefore, in a circuit board unit requiring high-speed operation, it is preferable that the relative permittivity of the filler in the region facing the electronic component and the circuit board be low.
  • the method of filling the filler is generally a method of injecting a liquid filler into a region facing the electronic component and the circuit board.
  • this injection method when the filler has a low viscosity, it flows out of a desired region, and when the filler has a high viscosity, it is not easy to fill the entire desired region. As a result, it is difficult to manufacture and requires many man-hours Furthermore, a portable notebook personal computer using such a circuit board unit may cause bumps and pads to separate due to impact during transportation and vibration.
  • the present invention provides a circuit board unit in which a conductive terminal of an electronic component and a conductive pad of a circuit board are conductively connected, wherein the electronic component is sealed to the circuit board so as to seal a gap between the electronic component and the circuit board.
  • a circuit board unit provided with a covering sheet is provided.
  • the covering sheet is sealed under reduced pressure so that the conductive terminal of the electronic component according to claim 1 and the conductive pad of the circuit board have a bonding load value of 30 (g / bump) or more.
  • the present invention provides a circuit board unit characterized in that a gap between the electronic component according to claim 2 and a circuit board is filled with an inert gas or air. Therefore, the relative dielectric constant can be reduced by the inert gas or air in the facing region. In addition, it is possible to prevent oxidation of component terminals of electronic components and circuit patterns of circuit boards and corrosion by moisture.
  • the present invention provides a circuit board unit, wherein the cover sheet according to claim 1 has a two-layer sheet structure of polyethylene terephthalate and ethylene-vinyl acetate copolymer. I do.
  • the covering sheet is shielded from the electronic components to the circuit board.
  • the circuit board unit can be easily manufactured simply by covering. Furthermore, the electronic component can be pressed and joined to the circuit board by the covering sheet.
  • the present invention provides a method of filling an inert gas into a gap between an electronic component and a circuit board, and a covering sheet hermetically covering the electronic component and the circuit board,
  • the present invention provides a method of manufacturing a circuit board unit, wherein the coated sheet is heat-pressed and sealed on a circuit board.
  • the region facing the electronic component and the circuit board can be filled with an inert gas. Therefore, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board can be reduced. Then, the manufacture of the circuit board unit is facilitated, and the man-hour for manufacturing the circuit board unit can be reduced.
  • FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
  • FIG. 3 is a plan view showing a pattern arrangement of a circuit board used in the present invention.
  • FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
  • FIG. 5 shows the results of a continuity test of each sample according to the example of the present invention.
  • FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention.
  • the circuit board unit of FIG. 1 is usually mounted with a plurality of electronic components, it is a drawing in which one component is mounted for easy understanding of the contents.
  • 1 is a circuit board unit manufacturing apparatus
  • 10 is a circuit board unit
  • '0 is a covering sheet
  • 30 is a heating and pressing apparatus.
  • the circuit board unit manufacturing apparatus 1 described first includes a holding base 2 as a base and a heating / compression bonding apparatus 30.
  • the holding table 2 can hold and remove the circuit board unit 10 on the upper surface. Then, the circuit board unit manufacturing apparatus 1 shuts off the inside and the outside of the apparatus 1 to make a sealed pressure-reduced state, and then supplies gas from the outside of the circuit board unit manufacturing apparatus 1. Can be filled.
  • thermocompression bonding apparatus 30 Next, the thermocompression bonding apparatus 30 will be described.
  • the thermocompression bonding device 30 can be moved up and down and left and right by a driving source (not shown).
  • the shape of the head 31 of the thermocompression bonding device 30 is concave.
  • the size of the concave depression is accommodated in the depression without the electronic component 13 covered with the covering sheet 10 being in contact with the lateral and top surfaces.
  • the shape of the depression is similar to that of the electronic component 13.
  • the width of the tip head 31 pressing the cover sheet bent portion 21 of the cover sheet 10 is about lmm.
  • This tip head 31 is kept at about 140 ° C. by a heat source.
  • the folded portion 21 of the covering sheet 10 can be pressed with a pressure of about 10 kgf.
  • circuit board unit 10 is manufactured outside the circuit board unit manufacturing apparatus 1. After manufacturing, it is carried into the circuit board unit manufacturing apparatus 1.
  • This circuit board unit 10 is the surface of the circuit board 11 (the
  • the circuit pattern 12 which is the pad of the circuit is provided on the surface (1).
  • the circuit pattern 12 and the component terminal 14 which is a bump of the electronic component provided on the lower surface (second surface) of the electronic component 13 are temporarily bonded with a silver paste.
  • a silver paste for example, a product name Doitite manufactured by Fujikura Kasei Co., Ltd. can be used. This temporary adhesive is not melt-bonded to each other but is temporarily bonded for positioning.
  • FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
  • the electronic component 13 corresponds to a 16-pin electronic component.
  • the size of the component terminal 14 is a circle with a diameter of 0.1 ⁇ ,
  • Each of the component terminals 14 is electrically conductively connected two by two by a conductor 15, and each of the component terminals 14 and each of the conductors 15 are formed by patterning an aluminum vapor-deposited film.
  • Each component terminal 14 is provided with a bump having a height of about 40 ⁇ m by wire bonding of a gold wire.
  • FIG. 3 is a plan view showing a terminal arrangement of a circuit board used in the present invention.
  • the circuit board 11 is a simulated circuit board 11 made of glass epoxy resin having a total of 16 circuit patterns 16 as in FIG.
  • the circuit pattern 16 is arranged according to the terminal arrangement of the electronic component 13, and has the same size and spacing as the component terminal 14. However, on the circuit board 11, the circuit patterns 16 at both ends are connected to the conductive chip pattern 17, out of the total 16 circuit patterns 16, eight on each of the opposing left and right sides.
  • the six circuit patterns 16 are electrically conductively connected to each other by the conductor 18. That is, at the time when the electronic component 13 is mounted, the conductive check patterns 17 at both ends are in a conductive state on each side.
  • Such a circuit pattern 16 and the conductor 18 are obtained by patterning a copper thin film having a thickness of about 7 ⁇ m.
  • FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
  • the covering sheet 20 is obtained by bonding the base sheet 1 and the adhesive sheet 12 together.
  • the material of the base sheet 21 is a sheet of polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • the product name is Toyobo E-500 manufactured by Toyobo Co., Ltd.
  • the thickness t1 is about 30 ⁇ m.
  • the base sheet 21 is mechanically tough, has corrosion resistance to organic solvents and oils, has airtightness, has a melting point of about 260 ° C., and has high heat resistance.
  • the material of the other adhesive sheet 2 is a sheet of ethylene vinyl acetate copolymer (EVA).
  • EVA ethylene vinyl acetate copolymer
  • the product name is Suntec EVAEF1010 manufactured by Toyobo Co., Ltd., and the thickness t2 is about 40 m.
  • This adhesive sheet 12 is particularly excellent in adhesiveness and moisture resistance.
  • circuit board unit 10 is loaded into the circuit board unit manufacturing apparatus 1 and fixedly held on the holding table 2.
  • Sample 5 was manufactured at 0.61 atm, which was manufactured to 25 (g weight / bump).
  • Sample 6 was manufactured at 0.54 atm, which was manufactured to 30 (g weight / bump).
  • Sample 7 was manufactured at 0.46 atm, which was manufactured to 35 (g weight / bump).
  • Sample 8 was manufactured at 0.38 atm, which was manufactured to 40 (g weight / bump).
  • Sample 9 was produced at 0.30 atm, produced at 45 (g weight / bump).
  • Sample 10 was manufactured at 0.23 atm, which was manufactured to 50 (g weight / bump).
  • the coating sheet 20 is placed on the circuit board unit 10 in the circuit board unit manufacturing apparatus 1.
  • the adhesive sheet 22 of the covering sheet 20 is directed in a direction facing the circuit board 11, and the upper surface (first surface) of the electronic component is placed on the upper surface of the circuit board 11.
  • the adhesive sheet 22 is provided with a cover sheet bent portion 23 so as to be surely heat-pressed to the circuit board 11.
  • the width of the cover sheet bent portion 23 is about l mm.
  • thermocompression bonding apparatus 30 Subsequently, the head 31 of the thermocompression bonding apparatus 30 and the circuit board unit 10 covered with the covering sheet 10 are aligned, and the thermocompression bonding apparatus 30 is lowered.
  • argon gas having a relative dielectric constant of about 1 can be easily filled. Therefore, filling The relative permittivity of the gap between the electronic component and the surface of the circuit board can be made to be about 1 by the argon gas.
  • the covering sheet 10 is covered, as compared with the conventional method in which the filling material is filled in the facing region between the electronic component and the printed board by the injection method. Therefore, it can be easily manufactured and the number of manufacturing steps can be reduced. In addition, the covering sheet 10 relaxes the functions of the conventional filler, such as adhesion reinforcement, prevention of adhesion of dust and dust, and the like.
  • the inside of the gap between the sealed electronic component and the circuit board becomes lower than the external pressure of the covering sheet, that is, the atmospheric pressure, and the component terminals of the electronic component and the circuit pattern of the circuit board are pressed and pressed by the atmosphere. Therefore, the joining surfaces of the component terminals and the circuit patterns, which are pressed and joined, are slidable on each other, so that differences in elongation due to thermal expansion and vibration can be absorbed.
  • one electronic component is covered with one cover sheet, but a plurality of electronic components can be covered with one cover sheet. Also, when a child circuit board is mounted on the parent circuit board, the circuit board mounted with the parent and child can be bonded in the same manner by covering the child circuit board from above.
  • a sealed inert gas is filled in the gap between the electronic component and the circuit board, the terminal of the electronic component and the circuit pattern of the circuit board are prevented from being oxidized, and corrosion due to moisture is prevented.
  • An inert gas such as nitrogen gas, helium, xenon, or cribton can be used in place of the argon gas.
  • a continuity test was performed on 10 types of samples 1 to 10 of the examples.
  • the failure judgment of the continuity test was that the continuity resistance between the continuity check pads 17 after the temperature cycle was increased by 10% from the continuity resistance before the temperature cycle was performed.
  • the temperature cycle conditions were as follows: first, 15 ° C at 15 ° C for 15 minutes, then at room temperature for 5 minutes, then at 115 ° C for 15 minutes, and then at room temperature for 5 minutes. Made under 500 cycles. 100 samples of each sample were used for a continuity test.
  • Figure 5 shows the continuity test results for Samples 1 to 10.
  • the circuit board unit As described above, by adopting the circuit board unit as in the present invention, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board is reduced, and furthermore, the circuit board unit is reduced. It is possible to facilitate the manufacture, reduce the man-hour for manufacturing the circuit board unit, and prevent the bumps of the electronic components from coming off the pads of the circuit board.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

L'invention concerne un ensemble (10) carte de circuits imprimés comprenant, d'une part, une carte de circuits imprimés (11) pourvu de pastilles conductrices et, d'autre part, un dispositif électronique (13) pourvu de bornes conductrices, qui sont reliés de manière électrique par l'intermédiaire des pastilles et des bornes correspondantes. Le dispositif électronique (13) est pourvu d'une feuille (20) qui sert à le recouvrir sur la carte de circuits imprimés (11) de manière à sceller l'espace entre le dispositif électronique (13) et la carte de circuits imprimés (11).
PCT/JP2000/005843 2000-08-29 2000-08-29 Ensemble carte de circuits imprimes et procede de fabrication associe WO2002019783A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/005843 WO2002019783A1 (fr) 2000-08-29 2000-08-29 Ensemble carte de circuits imprimes et procede de fabrication associe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/005843 WO2002019783A1 (fr) 2000-08-29 2000-08-29 Ensemble carte de circuits imprimes et procede de fabrication associe

Publications (1)

Publication Number Publication Date
WO2002019783A1 true WO2002019783A1 (fr) 2002-03-07

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ID=11736407

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/005843 WO2002019783A1 (fr) 2000-08-29 2000-08-29 Ensemble carte de circuits imprimes et procede de fabrication associe

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078384A (ja) * 2006-09-21 2008-04-03 Toppan Printing Co Ltd プリント配線板の製造方法、保護シート及びプリント配線板
JP2008155245A (ja) * 2006-12-22 2008-07-10 Matsushita Electric Works Ltd 接合方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090868U (ja) * 1983-11-28 1985-06-21 パイオニア株式会社 プリント配線基板装置
JPS6362297A (ja) * 1986-09-02 1988-03-18 信越ポリマ−株式会社 電子部品の実装方法
JPH01278734A (ja) * 1988-05-02 1989-11-09 Matsushita Electron Corp チップ型装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090868U (ja) * 1983-11-28 1985-06-21 パイオニア株式会社 プリント配線基板装置
JPS6362297A (ja) * 1986-09-02 1988-03-18 信越ポリマ−株式会社 電子部品の実装方法
JPH01278734A (ja) * 1988-05-02 1989-11-09 Matsushita Electron Corp チップ型装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078384A (ja) * 2006-09-21 2008-04-03 Toppan Printing Co Ltd プリント配線板の製造方法、保護シート及びプリント配線板
JP2008155245A (ja) * 2006-12-22 2008-07-10 Matsushita Electric Works Ltd 接合方法

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