WO2002019783A1 - Circuit board unit and method of manufacture thereof - Google Patents

Circuit board unit and method of manufacture thereof Download PDF

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Publication number
WO2002019783A1
WO2002019783A1 PCT/JP2000/005843 JP0005843W WO0219783A1 WO 2002019783 A1 WO2002019783 A1 WO 2002019783A1 JP 0005843 W JP0005843 W JP 0005843W WO 0219783 A1 WO0219783 A1 WO 0219783A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
electronic component
board unit
sheet
gap
Prior art date
Application number
PCT/JP2000/005843
Other languages
French (fr)
Japanese (ja)
Inventor
Makoto Sasaki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2000/005843 priority Critical patent/WO2002019783A1/en
Publication of WO2002019783A1 publication Critical patent/WO2002019783A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3164—Partial encapsulation or coating the coating being a foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

Definitions

  • the present invention relates to a circuit board unit and a solder having electronic components mounted on a circuit board, and a method of manufacturing the same.
  • a semiconductor bay chip is sealed on a circuit board surface with a covering sheet to maintain a connection state.
  • the new circuit board unit is sealed on a circuit board surface with a covering sheet to maintain a connection state.
  • the circuit board unit is implemented by electronically connecting electronic components to a circuit board. These circuit boards and electronic components expand and contract due to the heat of power consumption during operation and the environmental temperature. On the other hand, these circuit boards and electronic components have different coefficients of thermal expansion. Therefore, in such a circuit board unit, there is a problem that the pad of the circuit board and the bump of the electronic component are easily separated from each other and a conduction failure is easily generated.
  • circuit board unit described in Japanese Patent Application Laid-Open Nos. 633-131647 and 61-232322.
  • circuit board units after electrically connecting the bumps of the electronic component to the pads of the circuit board, a region facing the electronic component and the printed board is filled with a filler.
  • This filler is to reinforce the adhesion between the chip component and the circuit board, and to prevent the adhesion of dust at the connection between the bump of the electronic component and the pad of the circuit board.
  • this filler for example, epoxy resin is used, and the relative dielectric constant of this resin is about 3 to 5.
  • the performance of electronic components is improved, and in particular, when a semiconductor chip that performs signal processing of several 10 GHz is mounted, there is a problem that the dielectric constant of such a filler causes a delay in signal propagation speed. Therefore, in a circuit board unit requiring high-speed operation, it is preferable that the relative permittivity of the filler in the region facing the electronic component and the circuit board be low.
  • the method of filling the filler is generally a method of injecting a liquid filler into a region facing the electronic component and the circuit board.
  • this injection method when the filler has a low viscosity, it flows out of a desired region, and when the filler has a high viscosity, it is not easy to fill the entire desired region. As a result, it is difficult to manufacture and requires many man-hours Furthermore, a portable notebook personal computer using such a circuit board unit may cause bumps and pads to separate due to impact during transportation and vibration.
  • the present invention provides a circuit board unit in which a conductive terminal of an electronic component and a conductive pad of a circuit board are conductively connected, wherein the electronic component is sealed to the circuit board so as to seal a gap between the electronic component and the circuit board.
  • a circuit board unit provided with a covering sheet is provided.
  • the covering sheet is sealed under reduced pressure so that the conductive terminal of the electronic component according to claim 1 and the conductive pad of the circuit board have a bonding load value of 30 (g / bump) or more.
  • the present invention provides a circuit board unit characterized in that a gap between the electronic component according to claim 2 and a circuit board is filled with an inert gas or air. Therefore, the relative dielectric constant can be reduced by the inert gas or air in the facing region. In addition, it is possible to prevent oxidation of component terminals of electronic components and circuit patterns of circuit boards and corrosion by moisture.
  • the present invention provides a circuit board unit, wherein the cover sheet according to claim 1 has a two-layer sheet structure of polyethylene terephthalate and ethylene-vinyl acetate copolymer. I do.
  • the covering sheet is shielded from the electronic components to the circuit board.
  • the circuit board unit can be easily manufactured simply by covering. Furthermore, the electronic component can be pressed and joined to the circuit board by the covering sheet.
  • the present invention provides a method of filling an inert gas into a gap between an electronic component and a circuit board, and a covering sheet hermetically covering the electronic component and the circuit board,
  • the present invention provides a method of manufacturing a circuit board unit, wherein the coated sheet is heat-pressed and sealed on a circuit board.
  • the region facing the electronic component and the circuit board can be filled with an inert gas. Therefore, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board can be reduced. Then, the manufacture of the circuit board unit is facilitated, and the man-hour for manufacturing the circuit board unit can be reduced.
  • FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
  • FIG. 3 is a plan view showing a pattern arrangement of a circuit board used in the present invention.
  • FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
  • FIG. 5 shows the results of a continuity test of each sample according to the example of the present invention.
  • FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention.
  • the circuit board unit of FIG. 1 is usually mounted with a plurality of electronic components, it is a drawing in which one component is mounted for easy understanding of the contents.
  • 1 is a circuit board unit manufacturing apparatus
  • 10 is a circuit board unit
  • '0 is a covering sheet
  • 30 is a heating and pressing apparatus.
  • the circuit board unit manufacturing apparatus 1 described first includes a holding base 2 as a base and a heating / compression bonding apparatus 30.
  • the holding table 2 can hold and remove the circuit board unit 10 on the upper surface. Then, the circuit board unit manufacturing apparatus 1 shuts off the inside and the outside of the apparatus 1 to make a sealed pressure-reduced state, and then supplies gas from the outside of the circuit board unit manufacturing apparatus 1. Can be filled.
  • thermocompression bonding apparatus 30 Next, the thermocompression bonding apparatus 30 will be described.
  • the thermocompression bonding device 30 can be moved up and down and left and right by a driving source (not shown).
  • the shape of the head 31 of the thermocompression bonding device 30 is concave.
  • the size of the concave depression is accommodated in the depression without the electronic component 13 covered with the covering sheet 10 being in contact with the lateral and top surfaces.
  • the shape of the depression is similar to that of the electronic component 13.
  • the width of the tip head 31 pressing the cover sheet bent portion 21 of the cover sheet 10 is about lmm.
  • This tip head 31 is kept at about 140 ° C. by a heat source.
  • the folded portion 21 of the covering sheet 10 can be pressed with a pressure of about 10 kgf.
  • circuit board unit 10 is manufactured outside the circuit board unit manufacturing apparatus 1. After manufacturing, it is carried into the circuit board unit manufacturing apparatus 1.
  • This circuit board unit 10 is the surface of the circuit board 11 (the
  • the circuit pattern 12 which is the pad of the circuit is provided on the surface (1).
  • the circuit pattern 12 and the component terminal 14 which is a bump of the electronic component provided on the lower surface (second surface) of the electronic component 13 are temporarily bonded with a silver paste.
  • a silver paste for example, a product name Doitite manufactured by Fujikura Kasei Co., Ltd. can be used. This temporary adhesive is not melt-bonded to each other but is temporarily bonded for positioning.
  • FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
  • the electronic component 13 corresponds to a 16-pin electronic component.
  • the size of the component terminal 14 is a circle with a diameter of 0.1 ⁇ ,
  • Each of the component terminals 14 is electrically conductively connected two by two by a conductor 15, and each of the component terminals 14 and each of the conductors 15 are formed by patterning an aluminum vapor-deposited film.
  • Each component terminal 14 is provided with a bump having a height of about 40 ⁇ m by wire bonding of a gold wire.
  • FIG. 3 is a plan view showing a terminal arrangement of a circuit board used in the present invention.
  • the circuit board 11 is a simulated circuit board 11 made of glass epoxy resin having a total of 16 circuit patterns 16 as in FIG.
  • the circuit pattern 16 is arranged according to the terminal arrangement of the electronic component 13, and has the same size and spacing as the component terminal 14. However, on the circuit board 11, the circuit patterns 16 at both ends are connected to the conductive chip pattern 17, out of the total 16 circuit patterns 16, eight on each of the opposing left and right sides.
  • the six circuit patterns 16 are electrically conductively connected to each other by the conductor 18. That is, at the time when the electronic component 13 is mounted, the conductive check patterns 17 at both ends are in a conductive state on each side.
  • Such a circuit pattern 16 and the conductor 18 are obtained by patterning a copper thin film having a thickness of about 7 ⁇ m.
  • FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
  • the covering sheet 20 is obtained by bonding the base sheet 1 and the adhesive sheet 12 together.
  • the material of the base sheet 21 is a sheet of polyethylene terephthalate (PET).
  • PET polyethylene terephthalate
  • the product name is Toyobo E-500 manufactured by Toyobo Co., Ltd.
  • the thickness t1 is about 30 ⁇ m.
  • the base sheet 21 is mechanically tough, has corrosion resistance to organic solvents and oils, has airtightness, has a melting point of about 260 ° C., and has high heat resistance.
  • the material of the other adhesive sheet 2 is a sheet of ethylene vinyl acetate copolymer (EVA).
  • EVA ethylene vinyl acetate copolymer
  • the product name is Suntec EVAEF1010 manufactured by Toyobo Co., Ltd., and the thickness t2 is about 40 m.
  • This adhesive sheet 12 is particularly excellent in adhesiveness and moisture resistance.
  • circuit board unit 10 is loaded into the circuit board unit manufacturing apparatus 1 and fixedly held on the holding table 2.
  • Sample 5 was manufactured at 0.61 atm, which was manufactured to 25 (g weight / bump).
  • Sample 6 was manufactured at 0.54 atm, which was manufactured to 30 (g weight / bump).
  • Sample 7 was manufactured at 0.46 atm, which was manufactured to 35 (g weight / bump).
  • Sample 8 was manufactured at 0.38 atm, which was manufactured to 40 (g weight / bump).
  • Sample 9 was produced at 0.30 atm, produced at 45 (g weight / bump).
  • Sample 10 was manufactured at 0.23 atm, which was manufactured to 50 (g weight / bump).
  • the coating sheet 20 is placed on the circuit board unit 10 in the circuit board unit manufacturing apparatus 1.
  • the adhesive sheet 22 of the covering sheet 20 is directed in a direction facing the circuit board 11, and the upper surface (first surface) of the electronic component is placed on the upper surface of the circuit board 11.
  • the adhesive sheet 22 is provided with a cover sheet bent portion 23 so as to be surely heat-pressed to the circuit board 11.
  • the width of the cover sheet bent portion 23 is about l mm.
  • thermocompression bonding apparatus 30 Subsequently, the head 31 of the thermocompression bonding apparatus 30 and the circuit board unit 10 covered with the covering sheet 10 are aligned, and the thermocompression bonding apparatus 30 is lowered.
  • argon gas having a relative dielectric constant of about 1 can be easily filled. Therefore, filling The relative permittivity of the gap between the electronic component and the surface of the circuit board can be made to be about 1 by the argon gas.
  • the covering sheet 10 is covered, as compared with the conventional method in which the filling material is filled in the facing region between the electronic component and the printed board by the injection method. Therefore, it can be easily manufactured and the number of manufacturing steps can be reduced. In addition, the covering sheet 10 relaxes the functions of the conventional filler, such as adhesion reinforcement, prevention of adhesion of dust and dust, and the like.
  • the inside of the gap between the sealed electronic component and the circuit board becomes lower than the external pressure of the covering sheet, that is, the atmospheric pressure, and the component terminals of the electronic component and the circuit pattern of the circuit board are pressed and pressed by the atmosphere. Therefore, the joining surfaces of the component terminals and the circuit patterns, which are pressed and joined, are slidable on each other, so that differences in elongation due to thermal expansion and vibration can be absorbed.
  • one electronic component is covered with one cover sheet, but a plurality of electronic components can be covered with one cover sheet. Also, when a child circuit board is mounted on the parent circuit board, the circuit board mounted with the parent and child can be bonded in the same manner by covering the child circuit board from above.
  • a sealed inert gas is filled in the gap between the electronic component and the circuit board, the terminal of the electronic component and the circuit pattern of the circuit board are prevented from being oxidized, and corrosion due to moisture is prevented.
  • An inert gas such as nitrogen gas, helium, xenon, or cribton can be used in place of the argon gas.
  • a continuity test was performed on 10 types of samples 1 to 10 of the examples.
  • the failure judgment of the continuity test was that the continuity resistance between the continuity check pads 17 after the temperature cycle was increased by 10% from the continuity resistance before the temperature cycle was performed.
  • the temperature cycle conditions were as follows: first, 15 ° C at 15 ° C for 15 minutes, then at room temperature for 5 minutes, then at 115 ° C for 15 minutes, and then at room temperature for 5 minutes. Made under 500 cycles. 100 samples of each sample were used for a continuity test.
  • Figure 5 shows the continuity test results for Samples 1 to 10.
  • the circuit board unit As described above, by adopting the circuit board unit as in the present invention, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board is reduced, and furthermore, the circuit board unit is reduced. It is possible to facilitate the manufacture, reduce the man-hour for manufacturing the circuit board unit, and prevent the bumps of the electronic components from coming off the pads of the circuit board.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

A circuit board unit (10) includes a circuit board (11) with conductive pads and an electronic device (13) with conductive terminals, which are electrically interconnected through the pads and the corresponding terminals. The electronic device (13) has a sheet (20) for covering itself on the circuit board (11) to seal the gap between the electronic device (13) and the circuit board (11).

Description

明 細 書  Specification
回路板ュニッ 卜とその製造方法 Circuit board unit and its manufacturing method
技術分野 Technical field
本発明は電子部品を回路基板に実装した回路板ュ二、ソ 卜と、 その製造方法に係 り、 特に半導体べァチップを被覆シ一卜で回路基板面上にシールして接続状態を 保持するようにした新しい回路板ユニッ トに関する。 景技術  The present invention relates to a circuit board unit and a solder having electronic components mounted on a circuit board, and a method of manufacturing the same. In particular, a semiconductor bay chip is sealed on a circuit board surface with a covering sheet to maintain a connection state. The new circuit board unit. Landscape technology
回路板ュニッ トは回路基板に電子部品を導通接続して実装されたものである。 これら回路基板と電子部品は稼働時の消費電力の熱及び、 環境温度によつて熱膨 張、 収縮する。 一方これら回路基板および電子部品の熱膨張率は互いに異なって いる。 従って、 このような回路板ュニッ トでは回路基板のパッ ドと電子部品のバ ンプとのはずれ及び導通不良を発生し易い問題がある。  The circuit board unit is implemented by electronically connecting electronic components to a circuit board. These circuit boards and electronic components expand and contract due to the heat of power consumption during operation and the environmental temperature. On the other hand, these circuit boards and electronic components have different coefficients of thermal expansion. Therefore, in such a circuit board unit, there is a problem that the pad of the circuit board and the bump of the electronic component are easily separated from each other and a conduction failure is easily generated.
このための解決技術としては特開昭 6 3— 3 1 6 4 4 7号公報、 特開平 6一 2 3 2 2 1 2号公報に記載された回路板ュニッ 卜がある。 これら回路板ュニッ 卜で は、 電子部品のバンプと回路基板のパッ ドとを導電接続した後、 電子部品とプリ ン卜基板との対向領域に充填材が充填されている。  As a solution to this problem, there is a circuit board unit described in Japanese Patent Application Laid-Open Nos. 633-131647 and 61-232322. In these circuit board units, after electrically connecting the bumps of the electronic component to the pads of the circuit board, a region facing the electronic component and the printed board is filled with a filler.
この充填材の役割はチップ部品と回路基板との接着補強と、 電子部品のバンプ と回路基板のパッ ドとの接続部の埃、 塵の付着防止である。  The role of this filler is to reinforce the adhesion between the chip component and the circuit board, and to prevent the adhesion of dust at the connection between the bump of the electronic component and the pad of the circuit board.
しかし、 この充填材は例えばエポキシ樹脂が使用され、 この樹脂の比誘電率は 約 3から 5である。 現在電子部品の性能が向上し、 特に数 1 0 G H zの信号処理 を行う半導体チップを実装する場合、 かかる充填材の誘電率は信号伝搬速度の遅 延をもたらす問題がある。 従って高速動作の要求される回路板ュニッ 卜では、 電 子部品と回路基板との対向領域の充填材の比誘電率は低い方が好ましい。  However, for this filler, for example, epoxy resin is used, and the relative dielectric constant of this resin is about 3 to 5. At present, the performance of electronic components is improved, and in particular, when a semiconductor chip that performs signal processing of several 10 GHz is mounted, there is a problem that the dielectric constant of such a filler causes a delay in signal propagation speed. Therefore, in a circuit board unit requiring high-speed operation, it is preferable that the relative permittivity of the filler in the region facing the electronic component and the circuit board be low.
また、 この充填材の充填方法は電子部品と回路基板との対向領域に液状の充填 材を注入する方法が一般的である。 この注入方法の場合、 粘度の低い充填材の場 合は所望する領域外に流出し、 粘度の高い時は所望する領域の全域を充満するこ とが容易でない。 結果として製造が困難であり、 多くの製造工数が必要とされる 更に、 このような回路板ュニッ トを使用した携帯用のノートパソコンは運搬時 の衝擊および、 振動によってバンプとパッ ドとの外れを生じることがある。 The method of filling the filler is generally a method of injecting a liquid filler into a region facing the electronic component and the circuit board. In the case of this injection method, when the filler has a low viscosity, it flows out of a desired region, and when the filler has a high viscosity, it is not easy to fill the entire desired region. As a result, it is difficult to manufacture and requires many man-hours Furthermore, a portable notebook personal computer using such a circuit board unit may cause bumps and pads to separate due to impact during transportation and vibration.
本発明の目的は電子部品と回路基板との対向領域の媒体の比誘電率を低減し、 更に、 回路板ュニッ 卜の製造を容易にして、 回路板ュニッ 卜の製造工数を削減し、 且つ電子部品のバンプと回路基板のパッ ドとの外れを防止した信頼性の高い新し い回路板ュニッ トを提供するものである。 発明の開示  SUMMARY OF THE INVENTION It is an object of the present invention to reduce the relative dielectric constant of a medium in a region facing an electronic component and a circuit board, to facilitate the manufacture of a circuit board unit, to reduce the number of man-hours for manufacturing a circuit board unit, It is intended to provide a new and highly reliable circuit board unit that prevents the bumps of components from coming off the pads of the circuit board. Disclosure of the invention
本発明は、 電子部品の導電端子と回路基板の導電パッ ドとを導電接続した回路 板ュニッ 卜において、 前記電子部品と回路基板との間隙を密閉するように電子部 品を回路基板にシールする被覆シ一トを設けたことを特徴とする回路板ュニッ ト を提供する。 この結果、 電子部品と回路基板との対向領域に不活性気体を充填で き、 または間隙を減圧環境とすることができる。 従って電子部品と回路基板との 対向領域の媒体の比誘電率を低減できる。 そして回路板ュニッ 卜の製造.を容易に して、 回路板ュニットの製造工数を削減できる。  The present invention provides a circuit board unit in which a conductive terminal of an electronic component and a conductive pad of a circuit board are conductively connected, wherein the electronic component is sealed to the circuit board so as to seal a gap between the electronic component and the circuit board. A circuit board unit provided with a covering sheet is provided. As a result, the region facing the electronic component and the circuit board can be filled with an inert gas, or the gap can be made a reduced pressure environment. Therefore, the relative dielectric constant of the medium in the area where the electronic component and the circuit board are opposed can be reduced. Then, the manufacture of the circuit board unit is facilitated, and the man-hour for manufacturing the circuit board unit can be reduced.
更に、 本発明は、 請求項 1に記載の電子部品の導電端子と回路基板の導電パッ ドとが接合荷重値 3 0 ( g /バンプ） 以上になるよう被覆シートを減圧状態でシ ールして成ることを特徴とする回路板ュ二、ソ 卜を提供する。 従って、 電子部品と 回路基板との対向領域を大気より減圧された間隙にすることができる。 従って電 子部品と回路基板とは互いに大気に押圧される。 そして強固に圧接される。 結果 として部品端子と回路パターンとの外れを防止できる。  Further, according to the present invention, the covering sheet is sealed under reduced pressure so that the conductive terminal of the electronic component according to claim 1 and the conductive pad of the circuit board have a bonding load value of 30 (g / bump) or more. Provided are a circuit board and a software characterized by comprising: Therefore, the gap between the electronic component and the circuit board can be reduced to a lower pressure than the atmosphere. Therefore, the electronic component and the circuit board are pressed against each other by the atmosphere. And it is pressed firmly. As a result, separation between the component terminals and the circuit pattern can be prevented.
次に、 本発明は、 請求項 2に記載の電子部品と回路基板との間隙に不活性ガス または空気を充填されていることを特徴とする回路板ュニッ 卜を提供する。 従つ て、 対向領域の不活性ガスまたは空気によって比誘電率を低減できる。 また電子 部品の部品端子や回路基板の回路パタ一ンの酸化防止および水分による腐食を防 止できる。  Next, the present invention provides a circuit board unit characterized in that a gap between the electronic component according to claim 2 and a circuit board is filled with an inert gas or air. Therefore, the relative dielectric constant can be reduced by the inert gas or air in the facing region. In addition, it is possible to prevent oxidation of component terminals of electronic components and circuit patterns of circuit boards and corrosion by moisture.
更に、 本発明は、 請求項 1に記載の被覆シートがポリエチレンテレフタレ一ト とエチレン酢酸ビニル共重合体との 2層のシ一ト構造であることを特徴とする回 路板ュニッ 卜を提供する。 結果として被覆シートを電子部品から回路基板まで遮 蔽するだけで回路板ュニットを容易に製造できる。 更に被覆シートで電子部品を 回路基板に押圧接合できる。 Further, the present invention provides a circuit board unit, wherein the cover sheet according to claim 1 has a two-layer sheet structure of polyethylene terephthalate and ethylene-vinyl acetate copolymer. I do. As a result, the covering sheet is shielded from the electronic components to the circuit board. The circuit board unit can be easily manufactured simply by covering. Furthermore, the electronic component can be pressed and joined to the circuit board by the covering sheet.
続いて、 本発明は、 電子部品と回路基板との間隙内に不活性ガスを充填し、 被覆シ一トが電子部品と回路基板とを密閉被覆し、  Subsequently, the present invention provides a method of filling an inert gas into a gap between an electronic component and a circuit board, and a covering sheet hermetically covering the electronic component and the circuit board,
更に被覆した被覆シートが回路基板に加熱圧着シールされたことを特徴とする回 路板ュニッ 卜の製造方法を提供する。 結果として電子部品と回路基板との対向領 域に不活性気体を充填することができる。 従って電子部品と回路基板との対向領 域の媒体の比誘電率を低減できる。 そして回路板ュニッ 卜の製造を容易にして、 回路板ュニッ 卜の製造工数を削減できる。 図面の簡単な説明 Further, the present invention provides a method of manufacturing a circuit board unit, wherein the coated sheet is heat-pressed and sealed on a circuit board. As a result, the region facing the electronic component and the circuit board can be filled with an inert gas. Therefore, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board can be reduced. Then, the manufacture of the circuit board unit is facilitated, and the man-hour for manufacturing the circuit board unit can be reduced. BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明の実施例に係る回路板ュニッ 卜の製造方法の説明図である。 図 2は本発明に使用される電子部品の端子配列を示す平面図である。  FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention. FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
図 3は本発明に使用される回路基板のパタ一ン配列を示す平面図である。 図 4は本発明の実施例に係る被覆シートの斜視図である。  FIG. 3 is a plan view showing a pattern arrangement of a circuit board used in the present invention. FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
図 5は本発明の実施例に係る各試料の導通試験結果である。 発明を実施するための最良の形態  FIG. 5 shows the results of a continuity test of each sample according to the example of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
本発明の実施例を図面に基づいて説明する。  An embodiment of the present invention will be described with reference to the drawings.
く実施例 > Example>
図 1は本発明の実施例に係る回路板ュニッ トの製造方法の説明図である。 図 1の回路板ュニッ トは通常複数の電子部品を実装されるが、 内容を理解し易く するために 1個の部品を実装した図面である。  FIG. 1 is an explanatory diagram of a method of manufacturing a circuit board unit according to an embodiment of the present invention. Although the circuit board unit of FIG. 1 is usually mounted with a plurality of electronic components, it is a drawing in which one component is mounted for easy understanding of the contents.
1は回路板ュニッ ト製造装置、 1 0は回路板ュニッ 卜、' 0は被覆シート、 3 0は加熱圧着装置である。'  1 is a circuit board unit manufacturing apparatus, 10 is a circuit board unit, '0 is a covering sheet, and 30 is a heating and pressing apparatus. '
最初に説明する回路板ュニッ 卜製造装置 1は基台である保持台 2と加熱圧着装 置 3 0とを内蔵している。 この保持台 2は上面に回路板ュニッ ト 1 0を保持およ び取り外し可能である。 そして回路板ュニッ ト製造装置 1は装置 1内と外部とを 遮断し密閉減圧状態にした後に、 回路板ュニッ ト製造装置 1の外部からガスを充 満することができる。 The circuit board unit manufacturing apparatus 1 described first includes a holding base 2 as a base and a heating / compression bonding apparatus 30. The holding table 2 can hold and remove the circuit board unit 10 on the upper surface. Then, the circuit board unit manufacturing apparatus 1 shuts off the inside and the outside of the apparatus 1 to make a sealed pressure-reduced state, and then supplies gas from the outside of the circuit board unit manufacturing apparatus 1. Can be filled.
次に加熱圧着装置 3 0を説明する。  Next, the thermocompression bonding apparatus 30 will be described.
加熱圧着装置 3 0は図示しない駆動源によって上下昇降可能、 左右移動可能であ る。 この加熱圧着装置 3 0の先端へッ ド 3 1の形状は凹状である。 凹状の窪みの 大きさは窪み内に被覆シート 1 0で被覆された電子部品 1 3横面、 上面が接触す ることなく収納される。 この窪みの形状は電子部品 1 3と相似形状である。 次に 被覆シート 1 0の被覆シ一卜曲折部 2 1を押圧する先端へッ ド 3 1の幅は約 l m mである。 この先端へッド 3 1は熱源で約 1 4 0度 Cに保たれている。 更に被覆 シート 1 0の被覆シート曲折部 2 1を約 1 0 K g重の圧力で押圧できる。 The thermocompression bonding device 30 can be moved up and down and left and right by a driving source (not shown). The shape of the head 31 of the thermocompression bonding device 30 is concave. The size of the concave depression is accommodated in the depression without the electronic component 13 covered with the covering sheet 10 being in contact with the lateral and top surfaces. The shape of the depression is similar to that of the electronic component 13. Next, the width of the tip head 31 pressing the cover sheet bent portion 21 of the cover sheet 10 is about lmm. This tip head 31 is kept at about 140 ° C. by a heat source. Further, the folded portion 21 of the covering sheet 10 can be pressed with a pressure of about 10 kgf.
次に、 回路板ュニッ ト 1 0の詳細を説明する。 この回路板ュニッ ト 1 0は具体 的には回路板ュニット製造装置 1の外部で製造される。 製造後に回路板ュニッ ト 製造装置 1内に搬入される。 この回路板ュニッ ト 1 0は回路基板 1 1の表面 （第 Next, details of the circuit board unit 10 will be described. Specifically, the circuit board unit 10 is manufactured outside the circuit board unit manufacturing apparatus 1. After manufacturing, it is carried into the circuit board unit manufacturing apparatus 1. This circuit board unit 10 is the surface of the circuit board 11 (the
1の面） に回路のパッ ドである回路パターン 1 2が設けられている。 この回路パ ターン 1 2と電子部品 1 3の下面 （第 2の面） に設けられた電子部品のバンプで ある部品端子 1 4が銀べ一ストで仮接着されている。 この銀ペーストは例えば藤 倉化成株式会社製の製品名ドータイ トを使用できる。 この仮接着剤は互いの金属 が溶融接着されたものではなく位置決めのために仮接着されたものである。 The circuit pattern 12 which is the pad of the circuit is provided on the surface (1). The circuit pattern 12 and the component terminal 14 which is a bump of the electronic component provided on the lower surface (second surface) of the electronic component 13 are temporarily bonded with a silver paste. As this silver paste, for example, a product name Doitite manufactured by Fujikura Kasei Co., Ltd. can be used. This temporary adhesive is not melt-bonded to each other but is temporarily bonded for positioning.
次に電子部品 1 3の詳細を説明する。  Next, details of the electronic component 13 will be described.
図 2は本発明に使用される電子部品の端子配列を示す平面図である。 FIG. 2 is a plan view showing a terminal arrangement of an electronic component used in the present invention.
1辺が約 1 0 mmの略正方状、 厚さ 6 5 0 mのシリコン製の模擬電子部品 1 3 である。 この電子部品 1 3の左右各辺に 8個ずつ合計 1 6個の接続用の部品端子 It is a simulated electronic component 13 made of silicon having a substantially square shape with a side of about 10 mm and a thickness of 650 m. 8 electronic components on each side of this electronic component 1 3 for a total of 16 component terminals
1 4が設けられている。 つまり、 この電子部品 1 3は 1 6ピンの電子部品に相当 する。 この部品端子 1 4の大きさは直径 0 . 1 πι Φの円形であり、 部品端子 1There are 14 provided. That is, the electronic component 13 corresponds to a 16-pin electronic component. The size of the component terminal 14 is a circle with a diameter of 0.1 πιΦ,
4の間隔は 6 0〃mである。 各部品端子 1 4は導体 1 5によって 2個ずつ順に導 電接続されており、 このような各部品端子 1 4及び各導体 1 5はアルミニウム蒸 着膜のパ夕一ニングによって形成されている。 なお各部品端子 1 4には、 それぞ れに金線のワイヤボンディングによって 4 0 u m程度の高さのバンプが設けられ ている。 The interval of 4 is 60〃m. Each of the component terminals 14 is electrically conductively connected two by two by a conductor 15, and each of the component terminals 14 and each of the conductors 15 are formed by patterning an aluminum vapor-deposited film. Each component terminal 14 is provided with a bump having a height of about 40 μm by wire bonding of a gold wire.
次に回路基板 1 1の詳細を説明する。 図 3は本発明に使用される回路基板の端子配列を示す平面図である。 Next, details of the circuit board 11 will be described. FIG. 3 is a plan view showing a terminal arrangement of a circuit board used in the present invention.
回路基板 1 1は、 図 2と同様のように合計 1 6個の回路パターン 1 6を有したガ ラスエポキシ樹脂製の模擬の回路基板 1 1である。 回路パターン 1 6は電子部品 1 3の端子配列に合わせて配列されており、 大きさ及び間隔は部品端子 1 4と同 一である。 ただし、 回路基板 1 1では、 対向する左右各辺に 8個ずつ合計 1 6個 の設けられた回路パターン 1 6の内、 両端の回路パターン 1 6は導通チヱック用 パターン 1 7と接続され、 残りの 6個の回路パターン 1 6が導体 1 8によって 2 個ずつ導電接続されている。 つまり、 電子部品 1 3が実装された時点で、 各辺に おいて、 両端の導通チヱック用パターン 1 7が導通状態になっている。 このよう な回路パターン 1 6及び導体 1 8は、 厚さ約 7〃mの銅薄膜をパターニングした ものである。 The circuit board 11 is a simulated circuit board 11 made of glass epoxy resin having a total of 16 circuit patterns 16 as in FIG. The circuit pattern 16 is arranged according to the terminal arrangement of the electronic component 13, and has the same size and spacing as the component terminal 14. However, on the circuit board 11, the circuit patterns 16 at both ends are connected to the conductive chip pattern 17, out of the total 16 circuit patterns 16, eight on each of the opposing left and right sides. The six circuit patterns 16 are electrically conductively connected to each other by the conductor 18. That is, at the time when the electronic component 13 is mounted, the conductive check patterns 17 at both ends are in a conductive state on each side. Such a circuit pattern 16 and the conductor 18 are obtained by patterning a copper thin film having a thickness of about 7 μm.
続いて図 4は本発明の実施例に係る被覆シートの斜視図である。  Next, FIG. 4 is a perspective view of the covering sheet according to the embodiment of the present invention.
被覆シ一ト 2 0はべ一スシ一ト 1 と接着シ一ト 1 2 とを貼り合わせたものであ る。 一方のベ一スシート 2 1の材料は、 ポリエチレンテレフタレ一ト （P E T ) のシートである。 例えば東洋紡株式会社製の製品名東洋紡エステル E— 5 0 0 0 の厚さ t 1約 3 0〃mである。 このべ一スシート 2 1は機械的に強靭であり、 そ して有機溶剤や油の耐蝕性を有し、 更に気密性を有し、 融点約 2 6 0度 Cであり 耐熱性が高い。 The covering sheet 20 is obtained by bonding the base sheet 1 and the adhesive sheet 12 together. The material of the base sheet 21 is a sheet of polyethylene terephthalate (PET). For example, the product name is Toyobo E-500 manufactured by Toyobo Co., Ltd., and the thickness t1 is about 30 μm. The base sheet 21 is mechanically tough, has corrosion resistance to organic solvents and oils, has airtightness, has a melting point of about 260 ° C., and has high heat resistance.
他方の接着シート 2の材料はエチレン酢酸ビニル共重合体 （E V A ) のシー トである。 例えば東洋紡株式会社製の製品名サンテック E V A E F 1 0 1 0の 厚さ t 2約 4 0〃mである。 この接着シー卜 1 2は特に接着性、 耐湿性に優れて いる。  The material of the other adhesive sheet 2 is a sheet of ethylene vinyl acetate copolymer (EVA). For example, the product name is Suntec EVAEF1010 manufactured by Toyobo Co., Ltd., and the thickness t2 is about 40 m. This adhesive sheet 12 is particularly excellent in adhesiveness and moisture resistance.
ぐ製造方法 > Manufacturing method>
続いて、 上記回路板ュニッ 卜製造装置 1を使用して回路板ュニッ ト 1 0に被覆 シート 2 0を被覆する製造方法を説明する。  Next, a description will be given of a manufacturing method for coating the circuit board unit 10 with the coating sheet 20 using the circuit board unit manufacturing apparatus 1 described above.
(1) 最初に回路板ュニッ ト 1 0を回路板ュニッ ト製造装置 1内に搬入し保持台 2 に固定保持する。  (1) First, the circuit board unit 10 is loaded into the circuit board unit manufacturing apparatus 1 and fixedly held on the holding table 2.
(2) その後、 回路板ユニッ ト製造装置 1内の空気を排除する。  (2) Thereafter, the air in the circuit board unit manufacturing apparatus 1 is eliminated.
(3) この回路板ュニッ ト製造装置 1内に水分を乾燥除去した不活性のアルゴンガ スを封入する。 この不活性のアルゴンガスの比誘電率は約 1である。 アルゴンガスを封入した後の回路板ュニッ ト製造装置 1内の圧力を減圧する。 こ の減圧値は電子部品の単位バンプ当たりの接合荷重を各種設定された 1 0種類の 試料を製造した。 詳細には、 試料 1は 5 ( g重/バンプ） に設定される 0 . 9 2 気圧にて製造した。 試料 2は 1 0 ( g重/バンプ） に設定される 0 . 8 6気圧に て製造した。 試料 3は 1 5 ( g重/バンプ） に製造される 0 . 7 7気圧にて製造 した。 試料 4は 2 0 ( g重/バンプ） に製造される 0 . 6 9気圧にて製造した。 試料 5は 2 5 ( g重/バンプ） に製造される 0 . 6 1気圧にて製造した。 試料 6 は 3 0 ( g重/バンプ） に製造される 0 . 5 4気圧にて製造した。 試料 7は 3 5 ( g重/バンプ） に製造される 0 . 4 6気圧にて製造した。 試料 8は 4 0 ( g重 /バンプ） に製造される 0 . 3 8気圧にて製造した。 試料 9は 4 5 ( g重/バン プ） に製造される 0 . 3 0気圧にて製造した。 試料 1 0は 5 0 ( g重/バンプ） に製造される 0 . 2 3気圧にて製造した。 (3) An inert argon gas from which water has been dried and removed is installed in the circuit board unit manufacturing equipment 1. Encapsulation. The relative permittivity of this inert argon gas is about 1. After the argon gas is sealed, the pressure in the circuit board unit manufacturing apparatus 1 is reduced. This reduced pressure value produced 10 types of samples in which the bonding load per unit bump of the electronic component was variously set. Specifically, Sample 1 was manufactured at 0.92 atm, set at 5 (g weight / bump). Sample 2 was manufactured at 0.86 atm, set at 10 (g weight / bump). Sample 3 was manufactured at 0.77 atm, which was manufactured to 15 (g weight / bump). Sample 4 was manufactured at 0.69 atm, which was manufactured to 20 (g weight / bump). Sample 5 was manufactured at 0.61 atm, which was manufactured to 25 (g weight / bump). Sample 6 was manufactured at 0.54 atm, which was manufactured to 30 (g weight / bump). Sample 7 was manufactured at 0.46 atm, which was manufactured to 35 (g weight / bump). Sample 8 was manufactured at 0.38 atm, which was manufactured to 40 (g weight / bump). Sample 9 was produced at 0.30 atm, produced at 45 (g weight / bump). Sample 10 was manufactured at 0.23 atm, which was manufactured to 50 (g weight / bump).
(4) そして回路板ュニッ ト製造装置 1内にて、 回路板ュニッ ト 1 0の上に被覆シ —ト 2 0を載置する。 詳細には被覆シ一ト 2 0の接着シ一ト 2 2を回路基板 1 1 と対向する方向に向けて、 電子部品の上面 （第 1の面） から回路基板 1 1の上面 (4) Then, the coating sheet 20 is placed on the circuit board unit 10 in the circuit board unit manufacturing apparatus 1. In detail, the adhesive sheet 22 of the covering sheet 20 is directed in a direction facing the circuit board 11, and the upper surface (first surface) of the electronic component is placed on the upper surface of the circuit board 11.
(第 1の面） まで全周囲を遮蔽するように載置する。 従って電子部品の下面 （第 2の面） の部品端子と回路基板の上面 （第 1の面） の回路パターンとの間隙は密 閉される。 この接着シート 2 2は回路基板 1 1 と確実に加熱圧着されるように被 覆シ一卜曲折部 2 3を設ける。 被覆シート曲折部 2 3の幅は約 l mmである。(1st surface) Place so that the entire periphery is shielded. Therefore, the gap between the component terminal on the lower surface (second surface) of the electronic component and the circuit pattern on the upper surface (first surface) of the circuit board is tightly closed. The adhesive sheet 22 is provided with a cover sheet bent portion 23 so as to be surely heat-pressed to the circuit board 11. The width of the cover sheet bent portion 23 is about l mm.
(5) 続いて、 加熱圧着装置 3 0の先端へッ ド 3 1 と被覆シート 1 0を被覆された 回路板ュニッ ト 1 0との位置合わせを行って加熱圧着装置 3 0を下降させる。(5) Subsequently, the head 31 of the thermocompression bonding apparatus 30 and the circuit board unit 10 covered with the covering sheet 10 are aligned, and the thermocompression bonding apparatus 30 is lowered.
(6) その後に約 1 4 0度 Cに保たれている先端へッ ド 3 1を約 1 0 K g重の圧力 で被覆シート曲折部 1 3を 1 0秒間押圧する。 (6) Then, press the bent portion 13 of the covering sheet 13 for 10 seconds with a pressure of about 10 kg weight on the tip head 31 kept at about 140 ° C.
(7) 1 0秒間経過後に加熱圧着装置 3 0の先端へッ ド 3 1を上昇させる。  (7) After the elapse of 10 seconds, raise the head 31 of the thermocompression bonding device 30.
(8) 回路板ュニッ 卜製造装置 1の密閉減圧状態を開放して、 回路板ュニッ ト製造 装置 1から回路板ュニッ ト 1 0を取り出す。  (8) Release the closed depressurized state of the circuit board unit manufacturing apparatus 1 and take out the circuit board unit 10 from the circuit board unit manufacturing apparatus 1.
以上説明したように電子部品と回路基板の表面との間隙を減圧された密閉状態 にしたことで、 比誘電率約 1のアルゴンガスを容易に充填できる。 従って、 充填 されたアルゴンガスにより電子部品と回路基板の表面との間隙の比誘電率約 1に できる。 As described above, by setting the gap between the electronic component and the surface of the circuit board in a sealed state in which the pressure is reduced, argon gas having a relative dielectric constant of about 1 can be easily filled. Therefore, filling The relative permittivity of the gap between the electronic component and the surface of the circuit board can be made to be about 1 by the argon gas.
従って従来のように、 充填材を電子部品とプリン卜基板との対向領域に注入方 法にて充填していたのに比較すると被覆シート 1 0を被覆するだけである。 この ために容易に製造でき且つ製造工数を削減できる。 尚、 被覆シート 1 0が従来の 充填材の役目である接着補強、 埃、 塵の付着防止等を緩和する。  Therefore, only the covering sheet 10 is covered, as compared with the conventional method in which the filling material is filled in the facing region between the electronic component and the printed board by the injection method. Therefore, it can be easily manufactured and the number of manufacturing steps can be reduced. In addition, the covering sheet 10 relaxes the functions of the conventional filler, such as adhesion reinforcement, prevention of adhesion of dust and dust, and the like.
更に、 密閉された電子部品と回路基板との間隙内は被覆シートの外部気圧、 つ まり大気圧より低くなり電子部品の部品端子と回路基板の回路パターンとは大気 により押され圧接される。 従つて部品端子と回路パターンとの押圧接合された接 合面は互いの面上を摺動移動可能なために熱膨張による伸長の差異、 及び振動を 吸収できる。  Further, the inside of the gap between the sealed electronic component and the circuit board becomes lower than the external pressure of the covering sheet, that is, the atmospheric pressure, and the component terminals of the electronic component and the circuit pattern of the circuit board are pressed and pressed by the atmosphere. Therefore, the joining surfaces of the component terminals and the circuit patterns, which are pressed and joined, are slidable on each other, so that differences in elongation due to thermal expansion and vibration can be absorbed.
本実施例では 1個の電子部品を 1枚の被覆シートで被覆したが、 複数個の電子 部品を 1枚の被覆シートで被覆することも可能である。 また親回路基板に子回路 基板を搭載する場合にも子回路基板の上から親回路基板へ被覆すると同様に親子 搭載の回路基板を接着できる。  In this embodiment, one electronic component is covered with one cover sheet, but a plurality of electronic components can be covered with one cover sheet. Also, when a child circuit board is mounted on the parent circuit board, the circuit board mounted with the parent and child can be bonded in the same manner by covering the child circuit board from above.
また電子部品と回路基板との間隙に密閉不活性ガスを封入するために電子部品 の部品端子や回路基板の回路パターンの酸化防止及び、 水分による腐食を防止す る。 これらアルゴンガスの代替えに不活性ガスの窒素ガス、 ヘリウム、 キセノン、 クリブトン等を使用できる。  In addition, since a sealed inert gas is filled in the gap between the electronic component and the circuit board, the terminal of the electronic component and the circuit pattern of the circuit board are prevented from being oxidized, and corrosion due to moisture is prevented. An inert gas such as nitrogen gas, helium, xenon, or cribton can be used in place of the argon gas.
<導通試験 >  <Continuity test>
続いて、 実施例の 1 0種類の試料 1から 1 0の導通試験をした。 導通試験の不 良判定は温度サイクルを行った後の導通チェック用パッド 1 7間の導通抵抗値が 温度サイクルを行う前の導通抵抗値より 1 0 %増加しているものとした。 温度サ ィクル条件は最初に一 5 5度 Cで 1 5分間、 次に常温にて 5分間、 続いて、 1 1 5度 Cで 1 5分間、 更に常温にて 5分間を 1サイクルとした条件下で 5 0 0サイ クル行った。 各試料を 1 0 0個使用し合計 1 0 0 0個を導通試験した。  Subsequently, a continuity test was performed on 10 types of samples 1 to 10 of the examples. The failure judgment of the continuity test was that the continuity resistance between the continuity check pads 17 after the temperature cycle was increased by 10% from the continuity resistance before the temperature cycle was performed. The temperature cycle conditions were as follows: first, 15 ° C at 15 ° C for 15 minutes, then at room temperature for 5 minutes, then at 115 ° C for 15 minutes, and then at room temperature for 5 minutes. Made under 500 cycles. 100 samples of each sample were used for a continuity test.
図 5に試料 1から 1 0の導通試験結果を示している。  Figure 5 shows the continuity test results for Samples 1 to 10.
図 5に見るように、 1バンプ当たりの荷重が 3 0 ( g重/バンフ。） 以上は不良発 生率が 0 %である。 結果として 1バンプ当たりの接合荷重が 3 0 ( g重/バン プ） 以上となるように圧力値を選定すると良い。 As shown in Fig. 5, when the load per bump is 30 (g weight / Banff) or more, the defect occurrence rate is 0%. As a result, the bonding load per bump is 30 (g B) It is good to select the pressure value so that it becomes the above.
次に、 1バンプ当たりの接合荷重が 3 0 ( g重/バンプ） 以上の試料 6、 7、 8、 9、 1 0の導通チヱック用パッ ド 1 7間の抵抗値の測定を行った。 その結果、 試料 6から 1 0の全部の試料の抵抗値が約 1〜 3 ιηΩ以下であり、 合格であつた c 従って、 接合荷重が 3 0 ( g重/バンフ。） 以上に設定された圧力を選定すると良 好な導通状態が保たれる。 産業上の利用可能性 Next, the resistance value between the conductive chip pads 17 of the samples 6, 7, 8, 9, 10 having a bonding load per bump of 30 (g weight / bump) or more was measured. As a result, is from the sample 6 1 0 total resistance value of about 1~ 3 ιηΩ samples below, c Atsuta in pass Accordingly, bonding load 3 0 (g Weight / Banff.) Above the set pressure By selecting, a good conduction state is maintained. Industrial applicability
以上説明したように， 本発明のような、 回路板ュニッ トを採用することによ り、 電子部品と回路基板との対向領域の媒体の比誘電率を低減し、 更に、 回路板 ュニッ 卜の製造を容易にして、 回路板ュニッ 卜の製造工数を削減し、 且つ電子部 品のバンプと回路基板のパッ ドとの外れを防止することが可能である。  As described above, by adopting the circuit board unit as in the present invention, the relative dielectric constant of the medium in the area facing the electronic component and the circuit board is reduced, and furthermore, the circuit board unit is reduced. It is possible to facilitate the manufacture, reduce the man-hour for manufacturing the circuit board unit, and prevent the bumps of the electronic components from coming off the pads of the circuit board.

Claims

請 求 の 範 囲 The scope of the claims
1 . 電子部品の導電端子と回路基板の導電パッ ドとを導電接続した回路板ュニ ッ トにおいて、  1. In a circuit board unit in which conductive terminals of electronic components and conductive pads of a circuit board are conductively connected,
前記電子部品と回路基板との間隙を密閉するように電子部品を回路基板にシ一 ルする被覆シ一卜を設けたことを特徴とする回路板ュニッ 卜。  A circuit board unit comprising a cover sheet for sealing an electronic component on a circuit board so as to seal a gap between the electronic component and the circuit board.
2 . 請求項 1に記載の電子部品の導電端子と回路基板の導電パッ ドとが接合荷 重値 3 0 ( g /バンプ） 以上になるよう被覆シ一卜を減圧状態でシールして成る ことを特徴とする回路板ュニッ 卜。  2. The cover sheet is sealed under reduced pressure so that the conductive terminal of the electronic component according to claim 1 and the conductive pad of the circuit board have a joint load value of 30 (g / bump) or more. A circuit board unit characterized by:
3 . 請求項 2に記載の電子部品と回路基板との間隙に不活性ガスまたは空気を 充填されていることを特徴とする回路板ュニッ 卜。  3. A circuit board unit characterized in that a gap between the electronic component according to claim 2 and a circuit board is filled with an inert gas or air.
4 - 請求項 1に記載の被覆シートがポリエチレンテレフ夕レートとエチレン酢 酸ビュル共重合体との 2層のシー卜構造であることを特徴とする回路板ュニッ 卜 4-A circuit board unit according to claim 1, wherein the covering sheet according to claim 1 has a two-layer sheet structure of polyethylene terephthalate and ethylene butyl acetate copolymer.
5 . 電子部品と回路基板との間隙内に不活性ガスを充填し、 5. Fill the gap between the electronic component and the circuit board with an inert gas,
被覆シートが電子部品と回路基板とを密閉被覆し、  The covering sheet hermetically covers the electronic component and the circuit board,
更に被覆した被覆シートが回路基板に加熱圧着シールされたことを特徴とする回 路板ュニッ 卜の製造方法。 A method for producing a circuit board unit, further comprising the step of heating and press-sealing the coated sheet on a circuit board.
PCT/JP2000/005843 2000-08-29 2000-08-29 Circuit board unit and method of manufacture thereof WO2002019783A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078384A (en) * 2006-09-21 2008-04-03 Toppan Printing Co Ltd Printed wiring board manufacturing method, protection sheet, and printed wiring board
JP2008155245A (en) * 2006-12-22 2008-07-10 Matsushita Electric Works Ltd Joining method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090868U (en) * 1983-11-28 1985-06-21 パイオニア株式会社 printed wiring board equipment
JPS6362297A (en) * 1986-09-02 1988-03-18 信越ポリマ−株式会社 Method of mounting electronic parts
JPH01278734A (en) * 1988-05-02 1989-11-09 Matsushita Electron Corp Manufacture of chip type device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090868U (en) * 1983-11-28 1985-06-21 パイオニア株式会社 printed wiring board equipment
JPS6362297A (en) * 1986-09-02 1988-03-18 信越ポリマ−株式会社 Method of mounting electronic parts
JPH01278734A (en) * 1988-05-02 1989-11-09 Matsushita Electron Corp Manufacture of chip type device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078384A (en) * 2006-09-21 2008-04-03 Toppan Printing Co Ltd Printed wiring board manufacturing method, protection sheet, and printed wiring board
JP2008155245A (en) * 2006-12-22 2008-07-10 Matsushita Electric Works Ltd Joining method

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