WO2002007204A1 - Procede et appareil de fabrication d'un dispositif a semiconducteur - Google Patents

Procede et appareil de fabrication d'un dispositif a semiconducteur Download PDF

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Publication number
WO2002007204A1
WO2002007204A1 PCT/JP2001/006243 JP0106243W WO0207204A1 WO 2002007204 A1 WO2002007204 A1 WO 2002007204A1 JP 0106243 W JP0106243 W JP 0106243W WO 0207204 A1 WO0207204 A1 WO 0207204A1
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WO
WIPO (PCT)
Prior art keywords
gas
chamber
semiconductor device
substrate
manufacturing
Prior art date
Application number
PCT/JP2001/006243
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English (en)
Japanese (ja)
Inventor
Katsunari Ozeki
Atsushi Tabata
Original Assignee
Applied Materials Inc.
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Filing date
Publication date
Application filed by Applied Materials Inc. filed Critical Applied Materials Inc.
Publication of WO2002007204A1 publication Critical patent/WO2002007204A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Definitions

  • the present invention relates to a method and an apparatus for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device by depositing and growing a predetermined compound on a substrate by a high-density plasma type vapor phase growth method, and a semiconductor device. Related to the device.
  • Semiconductor devices such as semiconductor devices in which elements such as ultra-LSIs are highly integrated have been miniaturized and multi-layered from the past, and in recent years, the tendency has become increasingly remarkable.
  • a process of forming a film on a substrate (substrate) provided with various concave portions such as holes and holes on the surface is included.
  • the aspect ratio of such a concave portion tends to increase with miniaturization as described above.
  • it is required to form an ideal stacked structure with no steps, and planarization of the substrate surface is very important.
  • Phosphorus Silicon Glass As a technique for forming a film by such a recess is deposited grow given compound on a substrate such as a substrate formed, for example, the S i 0 2 with phosphorus De was one up to semiconductors on a substrate A method of forming a film and the like can be given. This method is called the so-called Phosphorus Silicon Glass (PSG) process, which has been used for forming an interlayer film for a long time, and provides a film having excellent etch rate and impurity gettering characteristics.
  • PSG Phosphorus Silicon Glass
  • the present invention has been made in view of such circumstances, and a semiconductor device is formed by depositing and growing a predetermined compound by a PSG process on a substrate having a concave portion such as a hole or a groove having a large aspect ratio. It is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device capable of improving the filling property (characteristics) of such a concave portion when obtaining.
  • a method for manufacturing a semiconductor device is a method for obtaining a semiconductor device by depositing and growing a predetermined compound on a substrate by a high-density plasma type vapor phase growth method, A substrate accommodating step of accommodating a substrate in the chamber; and a first gas composed of a compound containing a silicon atom, a second gas composed of a compound containing a phosphorus atom, and a compound containing a fluorine atom in the chamber.
  • the method includes a gas supply step of supplying a third gas, and a plasma formation step of generating plasma in the chamber.
  • a compound containing a silicon atom and a phosphorus atom is generated by supplying a first gas and a second gas to generate plasma after accommodating a substrate in a chamber. Deposit and grow on the substrate.
  • silane (SiH 4 ) gas and phosphorus hydride (PH 3 ) gas are used as the first and second gases, respectively, and plasma is introduced into the chamber from above and from the side of the chamber.
  • a PSG process by the HDP type CVD method is performed, and a phosphorus-doped SiO 2 film (PSG film) is formed on the substrate.
  • the gas supply step when a third gas composed of a compound containing a fluorine atom is further supplied into the chamber, active species such as fluorine radicals are generated from the third gas by the plasma.
  • active species Edzuchingu agent to S i 0 2 Acts as (Echants). Therefore, when a concave portion such as a hole is formed on the base, Si 2 deposited on a portion where overhang is likely to occur tends to be etched. Therefore, overhang and the like are sufficiently prevented, and the generation of voids can be suppressed. As a result, it is possible to sufficiently fill the concave portions having a high aspect ratio.
  • the third gas is not particularly limited as long as it is a gas containing a fluorine atom, but is preferably a gas containing a fluorine atom and a nitrogen atom.
  • a third gas for example, nitrogen trifluoride (NF 3 ), nitrogen monofluoride (N 2 F 2 ), or the like can be used.
  • the degree of improvement of the embedding property by using the third gas is more than expected from the etching characteristics of fluorine radicals in a normal etching process.
  • the method for manufacturing a semiconductor device according to the present invention is excellent in the embedding property of the recess having a high aspect ratio provided on the base as described above, Extremely useful.
  • a semiconductor device manufacturing apparatus is for effectively implementing the semiconductor device manufacturing method of the present invention, and deposits a predetermined compound on a substrate by a high-density plasma type vapor phase growth method. This is a semiconductor device manufacturing apparatus that obtains a semiconductor device by growing.
  • a chamber containing a substrate a first gas supply unit for supplying a first gas composed of a compound containing a silicon atom in the chamber, and a compound containing a phosphorus atom in the chamber.
  • a second gas supply unit for supplying a second gas a third gas supply unit for supplying a third gas made of a compound containing a fluorine atom into the chamber, and a plasma generation in the chamber And a plasma forming part.
  • a flow control unit that adjusts a ratio of a flow rate of the first gas supplied into the chamber to a flow rate of the third gas supplied into the chamber to a predetermined value.
  • FIG. 1 is a schematic cross-sectional view showing a preferred embodiment of a semiconductor device manufacturing apparatus according to the present invention.
  • FIG. 2 is a cross-sectional view schematically illustrating a structure of an example of a wafer W (substrate).
  • the CVD apparatus 1 semiconductor device manufacturing apparatus shown in FIG. 1 is a 110-type (0 apparatus) and includes a chamber 2 having an inlet 2a for introducing a wafer W as a base into the inside.
  • a support member 3 for supporting the wafer W is provided in the chamber 2, and an electrostatic chuck 4 for fixing the wafer W is provided above the support member 3.
  • a DC power supply (not shown) is connected to the electric chuck 4.
  • a lift mechanism (not shown) having lift pins and the like is provided below the mounting position of W on the support member 3. This lift mechanism lifts (lifts up) the wafer W, and is used when the charged wafer W is brought into contact with plasma to remove charges from the wafer W.
  • a dome 5 is provided on the upper part of the chamber 2 so as to cover the chamber 2. On this dome 5, a plate 6 for setting the dome temperature and a cold plate 7 are placed. Further, the chamber 2 has a gas inlet 8a, and the dome 5 is provided with a gas inlet 8b.
  • gas inlets 8a and 8b are connected to gas supply sources 11a to 1e via gas supply lines 10a and 10b, respectively. From e, a predetermined gas is supplied into the chamber 2 through the gas inlets 8a and 8b.
  • the gas supply source 1 La S i H 4 gas (first gas), 0 2 gas, A'r gas, Roita 3 gas (second gas) and NF 3 gas ( Third gas).
  • the first, second and third gas supply units are respectively constituted by the gas supply sources 1 la, 1 Id and 1 le and the gas supply lines 10 a and 10 b connected to the respective gas supply sources. ing.
  • the gas supply lines 10a and 10b are provided with a mass flow controller 12 for controlling the amount of each gas supplied to the gas inlets 8a and 8b.
  • the mass flow controllers 12 provided in the gas supply lines 1 a and 10 b connected to the gas supply source 1 la where the SiH 4 is stored and the gas supply source 11 e where the NF 3 is stored are And a control function for adjusting the flow ratio of both gases to an appropriate or predetermined value. That is, at least the mass flow controllers 12 provided in the gas supply lines 10a and 10b connected to the gas supply sources 11a and 11e constitute a flow control unit.
  • S iH 4 gas and 0 2 gas of these gases the main raw material gas for allowing formation of S i0 2 film on the wafer W.
  • PH 3 gas is Source gas for doping atoms (ions).
  • the CVD apparatus 1 effectively forms a PSG film (phosphorus-doped SiO 2 film) on a wafer.
  • the NF 3 gas and the Ar gas are supplied into the chamber during the formation of the PSG film and used as a film forming gas, and also serve as a cleaning gas for cleaning the inside of the chamber 2 and a carrier gas thereof, respectively. What is used.
  • a throttle valve chamber 22 in which a two-blade evening boss throttle valve 23 is stored is provided below the chamber 2 so as to communicate with the two chambers.
  • a turbo-molecular pump 25 for evacuating the inside of the chamber 2 through a gate valve 24 is installed below the throttle valve chamber 22.
  • the throttle valve chamber is opened and closed by opening and closing the gate valve 24. 22 can be connected and isolated from the inlet of the molecular pump 25.
  • the pressure in the chamber 2 can be stably controlled during the processing of the wafer W.
  • the exhaust port 26 of the molecular pump 25 is connected to a chamber via an exhaust pipe 27.
  • the exhaust pipe 27 and the exhaust port 29 provided in the throttle valve chamber 22 are connected by an exhaust pipe 30 having a rough throttle valve 31. These exhaust pipes 27, 30 are provided with isolation valves 32, 33, respectively.
  • the chamber 2 is provided with a gas inlet 16 connected to the reactor 18 via a cleaning gas supply line 17.
  • This reactor 18 has a microwave generator 19 for generating plasma and is connected to gas supply sources 11 c and 11 d via a gas supply line 20.
  • the gas supply line 20 is provided with a mass flow controller 21 for controlling the amount of each gas supplied to the reactor 18.
  • the dome 5 has coils 13a and 13b (side coils and ⁇ Top coil) is installed.
  • Each of the coils 13a, 13b is connected to an RF generator 14a, 14b, respectively, and plasma is generated in the chamber 2 by application of high-frequency power from the RF generators 14a, 14b.
  • the coils 13a and 13b and the RF generators 14a and 14b constitute a plasma forming unit.
  • matching networks 15a, 15b for matching the output impedance of the RF generators 14a, 14b to the coils 13a, 13b.
  • the electrostatic chuck 4 is connected to a bias RF generator 14c via a matching network 15c.
  • the wafer W shown in FIG. 2 is introduced into the chamber 2 from the introduction port 2a and placed on the support member 3 (substrate accommodation step).
  • a gate portion 102 is formed on an Si layer 101, and an SiN film 103 is formed so as to cover the gate portion 102, and a concave portion is formed between the gate portions 102. 110 are formed.
  • the above-described aspect ratio of the concave portion 110 is represented by a value obtained by dividing the depth A of the concave portion by the bottom width B of the concave portion, that is, AZB.
  • Ar gas from the gas supply source 11c is supplied into the chamber 2 from the gas inlets 8a and 8b. After the pressure in the chamber 2 becomes a predetermined value, and supplies the 0 2 gas in the gas supply source 11 b to the gas inlet port 8 a, 8 b Karachi Yamba 2.
  • the SiH 4 gas from the gas supply source 11a is supplied into the chamber 2 from the gas inlets 8a and 8b, and simultaneously or almost simultaneously with the PH 3 gas from the gas supply sources lid and lie.
  • gas and NF 3 gas gas inlet 8 a supplied from 8 b into the chamber 2.
  • a gas supply step is constituted by these gas supply steps.
  • These gases supplied into the chamber 2 generate active species by plasma. Further, the cooling of the wafer W is started with a slight delay.
  • a high frequency power for bias is applied to the wafer W from the RF generator 14 c via the electrostatic chuck 4.
  • active species generated from SiH 4 , O 2 , and PH 3 were drawn into the support W on the support member 3, reached the support W, and phosphorus atoms were doped on the surface of the support W by a chemical reaction.
  • S i 0 2 is deposited grown to obtain a semiconductor device PSG film is formed on the S iN film 103.
  • Si 2 also grows on the bottom wall surface and the side wall surface of the recess 110, and the recess 11
  • the active species of the chemical species containing fluorine derived from NF 3 gas in contrast, in the present embodiment, the active species of the chemical species containing fluorine derived from NF 3 gas
  • SiH 4 gas and NF 3 gas are preferably used in the following formula (1);
  • F 1 in the equation represents the flow rate of the SiH 4 gas supplied into the chamber 2
  • F 3 represents the flow rate of the NF 3 gas supplied into the chamber 2.
  • the ratio of the gas flow (F 3ZF 1) is less than 0.1, the concentration and fluorine radicals produced is significantly reduced in the chamber tends to etch resistance is not sufficiently expressed for S i0 2 .
  • the flow rate ratio exceeds 2.0, a sufficient film forming rate tends not to be obtained. Therefore, by setting the ratio of the third gas flow rate to the first gas flow rate to a value within such a preferable range, it is possible to suppress the decrease in the deposition rate of the PSG film while maintaining the recess 110 on the W. There is an advantage that the embedding property can be sufficiently improved.
  • the pressure in the chamber 2 when the PSG film is formed is preferably 5 OmT or less, particularly preferably 10 mT or less. If the pressure in the chamber 2 exceeds the above upper limit, it tends to be difficult to obtain sufficient filling characteristics of the PSG film.
  • the deposition temperature of the PSG film is preferably 300 to 800 ° C., and more preferably 400 to 600 ° C. If the film forming temperature is below the lower limit, a sufficient growth rate of the PSG film tends not to be obtained. On the other hand, when the film formation temperature exceeds the upper limit, the reaction tends to proceed to the supply rate-controlling side, and the coverage of the TiN film 103 (particularly, the step coverage near the concave portion 110) tends to decrease.
  • the flow rate of each gas supplied into the chamber 2 is preferably set to the following conditions.
  • the frequency of the high-frequency power applied from the RF generators 14a and 14b is preferably 1.8 to 2.2 MHz, and the output is preferably 1000 to 5000 W. May be different.
  • the frequency of the high-frequency power applied from the RF generator 14c is preferably 13.56 MHz, and the output is preferably 1000 to 5000 W, more preferably 1500 to 3500 W.
  • the cooling of the wafer W is stopped, the electrostatic chuck 4 of the wafer W is turned off, and the application of the high-frequency power from the RF generators 14a, 14b to the coils 13a, 13b is stopped. Moreover, therewith, it stops the supply of 0 2 gas and Ar gas from the gas supply source 1 lb, 11 c.
  • the CVD apparatus 1 having such a configuration and the method of manufacturing a semiconductor device using the same, by supplying the NF 3 gas into the chamber 2 together with the SiH 4 gas, the plasma generated by the plasma is used.
  • the formation of the PSG film is performed while active species of chemical species including sulfur act as an etching agent.
  • S i 0 2 to grow, especially deposited on the likely site occur over one hanging in the vicinity of the opening in the recessed portion 110 provided on Uweha W is effectively etched.
  • the SiH 4 gas and the NF 3 gas are preferably supplied into the chamber 2 so as to satisfy the relationship represented by the above formula (1), more preferably the same formula (2).
  • the NF 3 gas may be supplied into the chamber 2 only from the gas inlet 16 or from the gas inlet 16.
  • the procedure for supplying each gas to the chamber 2 and the procedure for applying high-frequency power from the RF generator are not limited to the above-described procedures.
  • the third gas may be, for example, nitrogen monofluoride (N 2 F 2 ) gas other than NF 3 gas, and these may be used alone or in combination. Further, nitrogen difluoride (NF 2 ) gas may be mixed with these gases.
  • phosphines that is, other phosphorus hydrides and their alkyl or aryl substituents may be used in place of the PH 3 gas, and any of the first phosphine, the second phosphine, and the third phosphine may be used. Diphosphine may be used.
  • RF generator 14a (side): frequency 2. OMHz, output 4000W • RF generator 14b (top): frequency 2. OMHz, output 2000W
  • the obtained semiconductor device that is, the cross section of the wafer W after film formation, can be viewed with a secondary electron microscope. (Scanning Electron Microscope) Visual observation was performed using S5000 manufactured by Hitachi, Ltd., and the bottom width B of the recess 110 shown in FIG. 2, an arc ratio, and the presence or absence of voids were measured. Table 1 shows the obtained results. In the table, “ ⁇ ” in the “Void presence / absence” column indicates that no void was found, and “X” indicates that a void was found.
  • a PSG film was formed on wafers W having various arc ratios in the same manner as in Examples 1 to 10 except that the NF 3 gas was not supplied into the chamber 2.
  • Table 1 also shows the results of measuring the bottom width B of the recess 110, the arc ratio, and the presence or absence of voids in the same manner as in Examples 1 to 10.
  • Example 1 20 1 4.6 ⁇ Example 2 22 1 3.4 ⁇ Example 3 23 1 2.8 ⁇ Example 4 28 1 0.4 ⁇ Example 5 29 1 0.1 ⁇ Example 6 30 9 8 ⁇ Example 7 37 7.9 ⁇ Example 8 38 7.7 ⁇ Example 9 42 7.8 ⁇ Example 10 43 6.8 ⁇ Comparative Example 1 22 1 3.1 X
  • a predetermined compound is deposited and grown on a substrate having a concave portion such as a hole or a groove having a large aspect ratio, particularly by a PSG process. At this time, it is possible to improve the embeddability of such concave portions.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un dispositif à semiconducteur, dans lequel une plaquette (W) est chargée dans la chambre (2) d'un appareil de dépôt chimique en phase vapeur (CVD) (1). Dans cette chambre (2), des gaz SiH4 et NF3 sont injectés, et un plasma haute densité est produit par application de fréquences élevées provenant de générateurs RF (14a, 14b), pour former un film PSG. Les radicaux de fluor provenant du gaz NF3 agissent tel un agent d'attaque chimique pour empêcher le surplomb dans un évidement. On améliore ainsi la capacité de remplissage des évidements à rapport d'aspect élevé d'une plaquette (W), tout en maintenant fixe le taux de dépôt de croissance d'un film PSG.
PCT/JP2001/006243 2000-07-18 2001-07-18 Procede et appareil de fabrication d'un dispositif a semiconducteur WO2002007204A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-217624 2000-07-18
JP2000217624A JP5116189B2 (ja) 2000-07-18 2000-07-18 半導体装置の製造方法及び装置

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WO2002007204A1 true WO2002007204A1 (fr) 2002-01-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554590A (zh) * 2020-04-16 2020-08-18 上海陛通半导体能源科技股份有限公司 半导体填孔真空系统及填孔方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3975099B2 (ja) 2002-03-26 2007-09-12 富士通株式会社 半導体装置の製造方法
KR100497607B1 (ko) 2003-02-17 2005-07-01 삼성전자주식회사 박막 형성 방법 및 박막 증착 장치
JP4820785B2 (ja) * 2007-07-20 2011-11-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
CN102931143B (zh) * 2011-08-10 2015-04-29 无锡华润上华科技有限公司 NOR Flash器件制作方法
TWI628694B (zh) * 2017-05-19 2018-07-01 台灣積體電路製造股份有限公司 排氣裝置、半導體製造系統與半導體製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0950995A (ja) * 1995-08-07 1997-02-18 Sony Corp シリコン系酸化物および半導体装置の層間絶縁膜
JPH0969518A (ja) * 1995-08-31 1997-03-11 Sony Corp シリコン化合物系絶縁膜の成膜方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748479B2 (ja) * 1992-11-30 1995-05-24 日本電気株式会社 絶縁膜形成方法及び装置
US5563105A (en) * 1994-09-30 1996-10-08 International Business Machines Corporation PECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming element
JP3467393B2 (ja) * 1997-10-27 2003-11-17 Ｎｅｃエレクトロニクス株式会社 半導体装置の配線形成方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0950995A (ja) * 1995-08-07 1997-02-18 Sony Corp シリコン系酸化物および半導体装置の層間絶縁膜
JPH0969518A (ja) * 1995-08-31 1997-03-11 Sony Corp シリコン化合物系絶縁膜の成膜方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554590A (zh) * 2020-04-16 2020-08-18 上海陛通半导体能源科技股份有限公司 半导体填孔真空系统及填孔方法

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TW494458B (en) 2002-07-11
JP2002043311A (ja) 2002-02-08

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