WO2001084635A1 - Transistor a couche mince et son procede de fabrication, et ecran a cristaux liquides comprenant ledit transistor - Google Patents

Transistor a couche mince et son procede de fabrication, et ecran a cristaux liquides comprenant ledit transistor Download PDF

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Publication number
WO2001084635A1
WO2001084635A1 PCT/JP2000/006330 JP0006330W WO0184635A1 WO 2001084635 A1 WO2001084635 A1 WO 2001084635A1 JP 0006330 W JP0006330 W JP 0006330W WO 0184635 A1 WO0184635 A1 WO 0184635A1
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Prior art keywords
region
channel
film transistor
thin
drain
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PCT/JP2000/006330
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English (en)
Japanese (ja)
Inventor
Yutaka Nanno
Takashi Okada
Atsunori Yamano
Kouji Senda
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Matsushita Electric Industrial Co., Ltd.
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Publication of WO2001084635A1 publication Critical patent/WO2001084635A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/42—Arrangements for providing conduction through an insulating substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/12—Materials and properties photoconductor

Definitions

  • the present invention relates to a thin film transistor, a manufacturing method thereof, and a liquid crystal display device including the thin film transistor. Background technology
  • a-Si active matrix type liquid crystal display devices formed of amorphous silicon
  • a-Si active matrix type liquid crystal display devices formed of amorphous silicon
  • the mobility of a — Si is 0.5 to 1 cm 2 ⁇ s — ' ⁇ V- 1 , and the number of pixels on the liquid crystal panel will increase in the future.
  • the general time is: The time to turn on the TFT of the pixel corresponding to a maximum of one horizontal period is shorter, and the writing capability to the pixel is shorter. Insufficient power.
  • the TFT of the pixel is made of polysilicon (hereinafter, referred to as “p—Si”), so that the mobility of the TFT is a— Compared with the case of the one created by Si, the charge ability to the pixel becomes higher because it is higher by one to two digits or more. Therefore, the definition of the liquid crystal panel will be increased; thus, it is advantageous to form the pixel TFT with p-S S (FPDE). xpo Forum 97.2-14).
  • the structure of a P-Si TFT is such that the gate electrode is located above the channel layer and the top electrode is located above the channel layer, and the gate electrode is located on the substrate relative to the channel layer.
  • the top-gate type structure is such that impurities are doped in a self-aligned manner using the gate electrode as a mask. As a result, it is possible to produce a TFT having a small parasitic capacity, and this is a significant factor for miniaturization.
  • the above-mentioned top gate type TFT When the above-mentioned top gate type TFT is applied to a liquid crystal display device, for example, and light is irradiated from the back surface of the TFT, the light of the knock light is directly transmitted to the TFT. The channel area is irradiated. Then, when the channel region is irradiated with light, a photoconductive current is generated in this portion, and the OFF current is increased.
  • the “photoconductive flow” is described.
  • the generation of photoconductive current is caused by the generation of electron / hole pairs via a band gap in the state where an electric field is applied, and the generated electron / hole pairs.
  • the increase in the number of carriers is observed in the form of the carrier recombination current. is there .
  • the electron which is the majority carrier on the drain side, has a sheet resistance in the n-region in the range of 20 k ⁇ / port to 100 k ⁇ Z port.
  • the width of the depletion layer is represented by W d.
  • the deterioration of the image quality caused by the deterioration of the off characteristic is the brightness gradient and the crosstalk.
  • the luminance gradient is caused by the difference in the current Z luminance characteristics of the liquid crystal between the upper part and the lower part of the screen.
  • a difference in brightness occurs between the upper and lower portions of the screen.
  • the black box pattern is displayed in the center of the white box as shown in Fig. 38 (b)
  • the black image Or it is like a trailing tail.
  • the inferiority of the off-characteristic has a great effect on the picture quality, such as an increase in the frit strength and the occurrence of uneven brightness.
  • the p-Si TFT since the p-Si TFT has high mobility, some or all of the active matrix elements and the iff drive circuit in the screen are made of glass. It can be formed simultaneously on the substrate. However, p-Si TFTs have a drawback when the OFF current is large compared to a-Si TFTs and MS-type electrolytic effect transistors. Yes.
  • a special feature 5-1 3 6 4 1 7 As shown in FIG. 1, a low-concentration impurity region (LDD region) is provided at least adjacent to at least one of the source region or the drain region of the TFT. (The first conventional method).
  • the LDD region force s ⁇ As for the mechanism that is effective in reducing the FF current, the LDD region is disclosed in Japanese Patent Laid-Open No. 5-133641. Because of the high resistance to the force drain region, the electric field force that covers the junction of the channel ZLDD region and the case where the LDD region is not provided It is considered to be smaller.
  • either method controls the presence or absence of Ta OX by combining the LDD region with a mask, or controls the presence or absence of a resist film. As a result, different portions of the doping concentration are formed.
  • the length of the LDD area in order to ensure the area of the LDD, the length of the LDD area must be longer than the dimensional accuracy of the mask. Absent .
  • the LDD region on the gate electrode in a self-aligning manner, and the mask for forming the LDD region can be reduced.
  • the length of the region with a high impurity concentration was increased by anodizing. It can be formed as small as 0.1 m to 0.5 m, which is equivalent to the thickness of the oxide present on the side surface of.
  • the LDD structure has a high effect on the reduction of OFF current; the force is inverted; the channel under the gate electrode of the TFT reverses.
  • ⁇ N In dog mode
  • the LDD region which is a relatively high resistance layer, is inserted in series into the channel region, which lowers the ON current. .
  • the LDD region has a high resistance to the source and the drain region, and as the characteristics of the TFT increase, the effect of the resistance becomes more pronounced. Tend to be. Therefore, the length of the LDD region, which is the high resistance region, is sufficient to reduce the OFF current and to ensure a high ⁇ N current. It must have a very low resistance value.
  • the method shown in the third conventional example which enables the LDD region to be formed as small as 0.1 m to 0.5 m, is possible.
  • its driving voltage is about 5 to 15 V.
  • C the driving voltage
  • the LDD region is in the range of 0.1 to 1.0, the effect becomes insufficient, and in this process, the ⁇ FF current cannot be sufficiently reduced. Les ⁇ .
  • the present invention adopts a configuration that suppresses the FFF current (photoconductive current) during light irradiation, thereby achieving a luminance gradient and a crosstalk. ⁇ Its primary purpose is to provide thin-film transistors that achieve high performance and high reliability by suppressing image quality degradation such as cracks.
  • the second objective is to provide thin-film transistors that achieve high performance and high reliability. Disclosure of the invention
  • the invention described in claim 1 is a thin-film transistor, and includes a channel region and the channel.
  • a source region and a drain region disposed on both sides of the semiconductor region, the semiconductor region having a polycrystalline silicon semiconductor layer.
  • a depletion layer is formed between the region and the drain region, and the depletion layer occurs when light is applied to the width of the depletion layer and the channel region.
  • the photoconductive current has a proportional relationship with the photoconductive current, and in order to keep the photoconductive current within a predetermined allowable value, the width of the depletion layer is equal to or less than a value obtained based on the proportional relationship.
  • the depletion layer width has a proportional relationship with the photoconductive current as described above. Are newly found, and by controlling the width of the depletion layer, the photoconductive current can be reduced to a predetermined allowable value or less. It is possible to provide a thin film transistor without deterioration in image quality such as inclined and crosstalk.
  • the invention described in claim 2 is the thin film transistor described in claim 1, wherein the sheet resistance in the drain region is R (k ⁇ / ⁇ ), when the channel width of the channel region of the Wl notation is W (itm), the relationship of equation (1) is satisfied.
  • A is a constant determined by the photoconductive current and the light intensity. (R + 30) W W A (1)
  • the invention described in claim 3 is the thin film transistor described in claim 2, wherein the sheet resistance of the drain region is R (k ⁇ Z Mouth), when the channel width of the channel region is W (m), the relationship of formula (2) is satisfied.
  • the newly controllable factor (the sheet resistance in the drain region), the channel width in the channel region, and By this relationship, it is possible to define a range in which the FF current (photoconductive current) during light irradiation is suppressed.
  • the thin film transistor satisfying the relations of the above equations (1) and (2) can suppress the increase Q of the ⁇ FF current at the time of light irradiation. As a result, crosstalk and brightness gradient can be prevented, and therefore, high performance and high reliability can be achieved.
  • the invention described in claim 4 is the thin film transistor according to claim 3, wherein the channel width W of the channel region is 2 m or less. It is characterized by the fact that
  • the invention described in claim 5 or claim 6 is the thin film transistor according to claim 3 or claim 4, wherein the drain is the thin film transistor described in claim 3 or claim 4. It is characterized in that the sheet resistance of the region is at least 20 kQZ and at least 100 kN.
  • the regulation is as follows: When the sheet resistance is less than 20 k ⁇ , the FF current increases rapidly and the sheet resistance becomes 100 k ⁇ Z If the voltage is larger than the opening, the ON current of the transistor decreases, and the panel operates. This is because it becomes unstable.
  • the OFF current can be reduced by setting the range of the sheet resistance in the drain region to more than 201 ⁇ saw and less than 100 kQZ. In addition, the ⁇ N current does not decrease, and a y-film transistor can be provided.
  • the invention described in claim 7 ′ includes a channel region, and a source region and a drain region on both sides of the channel region.
  • a low-concentration impurity region lower than the impurity region is formed, and the length AL of the low-concentration impurity region is less than 1.0 / im. It is with.
  • the transistor can be a thin-film transistor in which the photoconductive current ( ⁇ FF current) does not increase.
  • the invention according to claim 8 forms a channel region, and a source region and a drain region arranged on both sides of the channel region.
  • the impurity concentration may be between at least one of the source region and the channel region or at least one of the drain region and the channel region.
  • the length of the low-concentration impurity region is ⁇ L (m)
  • the source-drain interrogation voltage is V 1c (V)
  • the channel of the channel region is Let the width be W (m) In this case, it is characterized by satisfying the relationship of equation (3).
  • the low-concentration impurity region described above becomes a high resistance layer where the carrier dies.
  • the OFF current can be reduced. From the above equation (1), it is possible to determine the guideline of the goodness of the LDD region, and it is necessary to secure the LDD region more than necessary to reduce the FFFF current. The point is no more.
  • the invention according to claim 9 is the thin film transistor according to claim 8, wherein the channel length of the channel region is L (rn). In this case, it is a feature that the relationship of Expression (4) is satisfied.
  • the gate of the thin-film transistor is Due to the action of the electric field from the gate electrode, the low-concentration impurity region under the gate electrode becomes a low-resistance region due to accumulation of electrons that become carriers, and the ONm current decreases. Absent . Therefore, the thin-film transistor is able to sufficiently secure the ON current and to reduce the ⁇ F current.
  • the invention described in claim 11 or claim 2 is the thin-film transistor according to claim 9 or claim 10, wherein the thin-film transistor according to claim 9 or claim 10 is the thin-film transistor according to claim 9. No concentration It is characterized in that the sheet resistance in the pure region is 20 kQZ or more and 100 kQZ or less.
  • the invention described in claim 13 is claim 11: The thin film transistor described above, wherein the low-concentration impurity region is a drain region and a chip region. It is characterized by the fact that it is formed only between it and the tunnel region.
  • the purpose of providing the low-concentration impurity region is to alleviate the electric field acting on the drain region, and from this point of view, the drain region should be used. It is not necessary to provide a low-concentration impurity region in both the region and the channel region, and therefore, between the drain region and the channel region, or in the drain region. By forming at least one low-concentration impurity region between the channel region and the channel region, the area of the thin-film transistor can be reduced. It becomes possible.
  • An invention according to claim 14 is a liquid crystal panel part including the thin film transistor according to claim 1 as a switching element.
  • a liquid crystal display device having a backlight unit for supplying light from the rear side to the liquid crystal panel unit, and a sheet in the drain area.
  • the resistance is R (k ⁇ / ⁇ )
  • the brightness of the knock light portion is ⁇ (cd / m 2 )
  • the channel width of the channel region is W (am).
  • C is a constant determined by the photoconductive current.
  • the invention according to claim 15 is the liquid crystal display device according to claim 14, wherein the sheet resistance in the drain region is R (k ⁇ / ⁇ )> If the brightness of the back light part is B (cd Zm 2 ) and the channel width of the channel area is W (/ im), the formula It is characterized by satisfying the relationship of (6). (R + 3 0) ⁇ B ⁇ W ⁇ 1 X 1 0 6 ⁇ ⁇ (6)
  • the invention according to claim 16 is an EL device having a light emitting layer as an upper layer of pixel electrodes formed on a substrate having a thin film transistor.
  • the invention described in claim 17 is an EL display device described in claim 16.
  • the sheet resistance of the drain region is R (k ⁇ / cm)
  • the light intensity radiated on the channel region is B (cd X m 2 )
  • the channel width of the channel region is W (m)
  • the relationship of Expression (6) is satisfied.
  • the invention described in claim 19 is a method for manufacturing a thin film transistor, in which a polycrystalline silicon semiconductor is formed on an insulating substrate.
  • the first impurity doping process for doping impurities by the first impurity doping process and the first impurity doping process described above shields the semiconductor region over the impurity-doped semiconductor region.
  • a film is formed, and the shielding film is formed in a pattern by anisotropic etching. Forming a film on the polycrystalline silicon semiconductor layer by using the shielding film as a mask and doping the impurity in the lower region of the shielding film and the other region; Ensure that there is a concentration difference and at least some between the source region and the channel region, or between the drain region and the channel region.
  • a low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region is formed, and the length of the low-concentration impurity region is less than 1.0 m.
  • a second impurity doping step is performed.
  • the invention according to claim 20 is the method for manufacturing a thin film transistor according to claim 19, wherein the length ⁇ of the low-concentration impurity region is 1.0. It is characterized by including an inspection process to make the following products as non-defective products. Brief explanation of drawings
  • FIG. 3 is a graph showing the relationship between the sheet resistance obtained by the simulation and the depletion layer width.
  • FIG. 5 is a diagram showing an equivalent circuit of the active matrix.
  • FIG. 6 is a graph showing a simulation result of pixel voltage loss.
  • FIG. 7 is a graph showing a thin film transistor according to Embodiment 11 of the present invention.
  • FIG. 8 is a schematic cross-sectional view of a liquid crystal display device used as a pixel switching element.
  • FIG. 8 is a thin film transistor according to Embodiment 11 of the present invention.
  • FIG. 2 is a schematic sectional view of FIG.
  • FIG. 9 is a schematic plan view of FIG.
  • FIG. 10 is a schematic cross-sectional view showing a method of manufacturing a thin-film transistor according to Embodiment 11 of the present invention.
  • Fig. 11 is a schematic cross-sectional view of the same thin film transistor manufacturing method, showing a manufacturing method of the thin film transistor.
  • FIG. 12 is a flowchart showing a method of manufacturing a thin film transistor in the same manner.
  • Fig. 13 is a graph showing the voltage-Z current characteristics of a thin-film transistor.
  • Fig. 14 is a graph showing the variation of the QFF current in the substrate surface.
  • Figure 15 is a graph showing the results of simulating the V g-I d characteristics of a thin film transistor with the concentration of the n-type region as the norameter.
  • Fig. 16 is a graph showing the result of simulating the electric field when the TFT is turned off.
  • FIG. 17 is a schematic cross-sectional view showing a method for manufacturing a thin-film transistor according to Embodiment 12 of the present invention.
  • Fig. 18 is a schematic cross-sectional view showing a method of manufacturing a thin-film transistor.
  • FIG. 19 is a plan view showing a C-MOS-in-line interconnect pattern using a thin-film transistor according to the first to third embodiments of the present invention. .
  • Figure 20 is the equivalent circuit diagram.
  • FIG. 21 is a sectional view taken along the line X—X ′ of FIG. 19.
  • Figure 22 is a graph showing the operating points in the no-contact state of the n-ch transistor when the C-MOS inverter is on Z off in the evening. It is.
  • Numeral 23 simulates V g-I d characteristics when the LDD region is changed from 0.5 am to 3 m with the sheet resistance set to no-go overnight. This is a graph showing the result of the shot.
  • Fig. 25 shows the relationship between the length (mm L) of the C region having the actual O region 0, the length (mm L), the 0 FF current, the length ( ⁇ L) of the LDD region, and the ⁇ N current. This is a graph showing the relationship.
  • FIG. 26 is a simplified cross-sectional view of the thin-film transistor according to Embodiment 2-1.
  • Figure 27 is a schematic plan view of Figure 26.
  • FIG. 28 is a schematic cross-sectional view showing a method of manufacturing a thin-film transistor according to Embodiment 2-1 of the present invention.
  • FIG. 29 shows the fabrication of a thin film transistor according to the embodiment 2-1 of the present invention. It is a schematic sectional view showing a manufacturing method.
  • FIG. 30 is a flowchart showing a method of manufacturing a thin-film transistor according to the embodiment 2-1 of the present invention.
  • FIG. 31 is a schematic cross-sectional process diagram illustrating a process of forming an LDD region.
  • FIG. 32 is a perspective view of the photomask and the substrate.
  • Figure 33 is a plan view in the same way.
  • FIG. 34 is a schematic cross-sectional view of the thin-film transistor after the formation of the LDD region.
  • FIG. 35 is a graph showing the voltage / current characteristics of the thin film transistor according to Embodiment 2-1.
  • FIG. 36 is a graph showing the variation in the OFF current of the thin film transistor in the substrate plane according to Embodiment 2-1.
  • FIG. 37 is a graph showing the result of simulating the Vg-Id characteristics of TFT with the concentration of the LDD region as the norameter.
  • Figure 38 is a schematic diagram for explaining the brightness gradient and the crosstalk. Best mode for carrying out the invention
  • the first invention group aims at suppressing a photoconductive current at the time of light irradiation to the TFT.
  • the inventors of the present application have set forth the above-mentioned optical transmission.
  • the width of the depletion layer By controlling (decreasing) the width of the depletion layer based on this proportional relation, the photoconductive current can be reduced below the allowable value, and the luminance can be reduced. It is possible to provide a thin-film transistor without deterioration in image quality such as inclination and crosstalk, etc.
  • the “depletion layer width” is described later with reference to FIG. As shown in (a), it is defined as the distance between the tangents of the two points where the electric field strength rises.
  • the luminance B of the backlight and the channel width W of the channel region have a correlation s with the photoconductive current.
  • the inventors of the present application have further studied the above “proportional relationship between the depletion layer width and the photoconductive current”, and have found that the sheet resistance in the drain region has been increased. Have also found that there is a correlation with photoconductive current.
  • the new control factor which is referred to as the 'sheet resistance' R, is used as an evaluation criterion.
  • the accuracy of the design of the thin-film transistor is improved as compared with the case of two parameters, and the photoconductive current can be remarkably suppressed.
  • the relationship between the width of the depletion layer and the photoconductive current will be described first, and then, the brightness B of the knock light and the sheet resistance R of the drain region will be described. And the relationship between the channel width W of the channel region. Then, the principle of the concrete fabrication method of TFT to suppress the photoconductive current is explained.
  • the inventors of the present application measured the relationship between the channel width and the photoconductive current of the channel region constituting the TFT, and also examined the sheet resistance and the drain resistance of the drain region. The relationship between the photoconductive and conductive currents was measured. In addition, for simulation We performed a further motion analysis to determine the range of the depletion layer width.
  • Fig. 1 (a) is a graph showing the relationship between the channel in the channel region constituting the TFT and the photoconductive current (OFF current: 1o FF ). is there .
  • the solid line 6 0 0 0 cd / cm 2
  • the broken line 4 0 0 0 cd / cm 2
  • 1 -dot chain line 2 0 0 0 cd / cm
  • the relationship between W and the photoconductive current I OFF is shown.
  • FIG. 1 (a) is a graph showing the relationship between the light luminance and the photoconductive current, and FIG. 1 (b) shows the FF current I. r "was found to be proportional to the knock light luminance B.
  • FIG. 2 (a) is a graph showing the result of simulating the electric field when the TFT is in the OFF state.
  • the electric field is concentrated only at the junction of the channel drain region, and the electric field is concentrated only at the junction of the channel drain region.
  • the width of the depletion layer is about 0.5 m, and the depletion layer region extends mainly to the channel side. It's all about the level.
  • the depletion calendar width is about 0.9 / im, which extends to the LDD region. This is confirmed.
  • FIG. 3 shows the simulation results obtained from the simulation. This shows the relationship between the depletion layer width and the depletion layer width.It has been confirmed that the depletion layer width Wd is proportional to the sheet resistance R. This is the case for a p-n junction. It is thought that the depletion layer extends to the region where the carrier concentration is low, as in the case of the expansion of the depletion layer. Equation (7) below shows the relationship between the gate resistance and the depletion layer width. W d 8 X 1 0 -. 3 ⁇ R + 0 2 4 ⁇ (7)
  • I P h. t . 5 X 1 0 - 1 5 , W d ... (8)
  • I P h. ,. Is the value at which the light intensity at a channel width of 4 m per 1 (cd Zm 2 ).
  • the depletion layer width Vd is equal to the photoconductive current Iph . t . It is found that the photoconductive current is below the allowable value by controlling (decreasing) the depletion layer width. It is possible to provide a thin-film transistor that achieves high performance and high reliability without causing deterioration in image quality such as luminance gradient and crosstalk. it can .
  • the “allowable value” mentioned above is a value of 10 pA or less, for example, as described later.
  • FIG. 6 shows a simulation result of time and power loss when the OFF current (RVsdff) of TFT is set to a parameter. As shown in Fig. 6, in order to suppress the voltage loss to less than 0.02 V at the holding time of 16 msec (1 no. It is confirmed that it is necessary to reduce the OFF current to 10 pA or less in this state.
  • C is a constant determined by the photoconductive current.
  • the thin film transistor that satisfies the above expression (6) can It can suppress the conduction current, and therefore can prevent the crosstalk and the brightness gradient, and provide excellent image quality and high performance. And high reliability can be achieved.
  • the above equation (6) is an equation including the knock light luminance as a liquid crystal nerile, but in general, a thin film transistor is always backed up. It is not limited to the transmission type with light. Therefore, assuming that the knock light luminance B is at most 500 000 cdm 2 , the above equation (6) becomes
  • the thin film transistor that satisfies the above formula (2 ') is a knocker. Regardless of the brightness B of the unit, it can be used as a thin film transistor regardless of transmission or reflection type.
  • the area covered by the electric field is the sheet resistance.
  • the above-mentioned relational expressions (1) and (2) are effective guidelines for producing a thin film transistor.
  • FIG. 7 is a schematic sectional view of a liquid crystal display device using the thin film transistor according to the first embodiment of the present invention as a pixel switching element
  • FIG. FIG. 9 is a schematic cross-sectional view of a thin-film transistor according to Embodiment 1 of the present invention.
  • FIG. 9 is a schematic plan view of FIG.
  • the liquid crystal display device 50 comprises a liquid crystal panel portion 5I and a back light portion 5 arranged on the back side of the liquid crystal panel portion 51. It is a transmission type liquid crystal display device equipped with 2 mags.
  • the liquid crystal panel portion 51 includes a polarizing plate 53 ⁇ 53, a glass substrate 2 ⁇ 54 b, and a matrix shape: the thin film transistor 1 on which the liquid crystal panel portion 51 is disposed. , A pixel electrode 55, a directing film 56, a liquid crystal layer 57, a common electrode 58, and the like.
  • a thin film transistor 1 (hereinafter, referred to as TFT) and a pixel electrode 55 are formed on the glass substrate 2, and a common electrode 58 is formed on the substrate 54 b.
  • TFT thin film transistor
  • a common electrode 58 is formed on the substrate 54 b.
  • a directing film 56, 56 made of a polyimide resin or the like is formed on the substrate 2, 54 b, respectively, and the directing film 5 is formed. 6 and 56 are rubbed so that the directions of their orientations are orthogonal to each other, and the substrates 2 and 54b are connected via a spacer (not shown). It is arranged in the opposite direction.
  • a liquid crystal layer 57 is sandwiched between the substrates 2 and 54b, and the liquid crystal in the liquid crystal layer 57 is twisted 90 degrees and oriented. . Further, on the outer surface of the above-mentioned 2 • 54b, the polarizing plates 53 • 53 are arranged so that the directions of vibration of the regulated light are parallel to each other.
  • a back light part 52 is arranged on the back (lower) side of the liquid crystal panel part 51.
  • the knock light section 52 is composed of a light emitting element such as a cold cathode tube and a light distribution plate for equalizing light.
  • FIG. 8 the thin film transistor will be described with reference to FIGS. 8 and 9.
  • Thin preparative run-g is te 1, on glass la scan the substrate 2, the thickness is 5 0 0 people polycrystalline sheet re co down layer 3, the film thickness is 1 0 0 0 A S i O 2 (two A gate insulating layer 4 composed of silicon oxide, a gate electrode 5a composed of aluminum, and an interlayer dielectric layer 6 composed of SiO 2 are provided. It is constructed by being stacked in order.
  • the polycrystalline silicon layer 3 has a channel region 3c located immediately below the gate electrode 5a and a source region 3a (n + layer) having a high concentration. ) And a drain region (n + layer) 3b having a high impurity concentration. Also, in the present embodiment, the length ⁇ L of the LDD region (n-layer) 3d-3e is set to 0.4 im. Further, the channel width W of the channel region 3c is set to 5 m.
  • the sheet resistance in the drain area is R (k ⁇ / ⁇ ), and the liquid crystal display device 5 using the active matrix TFT is used.
  • the brightness of the knock light portion 52 of 0 is B (cd / m 2 ), and the channel region 3 c is When the channel width of is set to W (), the design is made so as to satisfy the following expression (6).
  • a source electrode 7 and a drain electrode 8 are provided, and the source electrode 7 is formed on a gate insulating layer 4 and an inter-layer insulating layer 6.
  • the source electrode 3 is connected to the source region 3a through the contact hole 9a, and the drain electrode 8 is connected to the gate insulating layer 4 and the inter-layer insulating layer. It is connected to the drain region 3b via a contact hole 9b formed in 6.
  • FIG. 10 is a schematic cross-sectional view showing a method of manufacturing a thin film transistor according to the embodiment 11 of the present invention
  • FIG. 11 is a thin film transistor
  • FIG. 12 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor
  • FIG. 12 is a flow chart similarly showing a method for manufacturing a thin film transistor.
  • an a-Si layer 15 having a thickness of 50 OA is deposited on a glass substrate 2 by the plasma C ⁇ / D method.
  • the purpose of this dehydrogenation treatment is to prevent the occurrence of ablation of the Si film due to the elimination of hydrogen during crystallization.
  • the process for forming a-Si can be performed by processes other than plasma CVD, such as low-pressure CVD and snow-removing processes.
  • Polysilicon films can also be deposited directly using plasma CVD or other methods. In this case, an annealing step by a laser, which will be described later, is not required.
  • a-Si layer 15 is melt-recrystallized (p-S).
  • a polycrystalline silicon layer 16 is formed (FIG. 10 (b)).
  • the polycrystalline silicon layer 16 is formed into islands in a predetermined shape to form the polycrystalline silicon layer 3 (FIG. 10 (c)).
  • the polycrystalline silicon layer 3 is formed on the glass substrate 2 so that the gate insulating layer 4 is formed.
  • (Silicon dioxide) layer is formed (Fig. 10 (d)).
  • a gold layer 17 made of aluminum carbide is formed as the gate electrode 5a (FIG. 10 (e)).
  • the metal layer 17 is patterned into a predetermined shape to form the gate electrode 5a (FIG. 10 ( ⁇ )).
  • the impurity is doped by using the gate electrode 5a as a mask (FIG. 10 (g)). Specifically, the ion ion is doped by the ion ioning method as a dopant. As a result, the channel region 3c located immediately below the gate electrode 5a is a region where the impurity power is not doped. The region of the polycrystalline silicon layer 3 excluding the channel region 3c is a layer in which impurities are doped. In this case, the doping acceleration voltage is 80 kV, the beam current density is 1 A / cm 2, and an n-type region is created with high acceleration. .
  • a photoresist 18 is formed to cover the gate electrode 5a (FIG. 10 (h)).
  • the photoresist 18 is formed into an anisotropic etching pattern, thereby forming a resist film 5b. (Fig. 11 (i)). At this time, accurate turning of the resist film 5b can be formed by anisotropic etching.
  • the resist film 5 b is used as a mask, and the second impurity doping is performed.
  • U Specifically, ion ion is used as a dopant to make the ion ion dope by the ion doping method.
  • the doping acceleration voltage is 12 kV
  • the beam current density is 0.5 AZcm 2
  • a ⁇ -type region with low acceleration and high concentration can be created. It is.
  • contact holes 9a and 9b are opened in the inter-layer insulating layer 6 and the gate insulating layer 4 (Fig. 11 (1)).
  • the contact holes 9a and 9b are filled with a metal layer such as A1 according to the spatula method, and the upper part of the metal layer is formed. Is patterned into a predetermined shape to form a source electrode 7 and a drain electrode 8 (FIG. 11 (m)). Thus, the TFT 1 is manufactured. .
  • the n-channel TFT has been described, but the p-channel TFT is manufactured by the same manufacturing process. be able to .
  • the OFF current is approximately 5 pA. Become .
  • the thin film transistor according to the present embodiment is not required. Can ensure good display characteristics.
  • Figure 13 shows the voltage-Z current characteristics of the thin-film transistor.
  • FIG. 14 shows the distribution of the F current in the substrate plane.
  • TFT 1 (the graph of L 3) according to the present embodiment was able to secure a stable large ⁇ N current and a small OFF current. Also, from FIG. 14, the TFT 1 manufactured in this manner can reduce the variation on the substrate surface.
  • Figure 15 shows a thin-film transistor with the n-type region concentration as a parameter.
  • the results obtained by simulating the V g-I d characteristics of FIG. The sheet resistance in the LDD region is 20 k ⁇ .
  • the 0 FF current increases rapidly after the node. Therefore, the sheet resistance in the LDD region is at least 20 k ⁇ .
  • a value greater than or equal to Z ⁇ is required.
  • the sheet resistance in the LDD region is set to more than 100 kQ / port, the ON current of the transistor decreases. The operation of the cell became unstable. Therefore, it is desirable that the range of the sheet resistance in the LDD region is 20 ⁇ ⁇ ⁇ or more and 10 ⁇ ' ⁇ ⁇ or less.
  • an effective depletion layer region can be obtained by setting the length AL of the LDD region to 0.4 / xm or less. Is 0.4 m or less, and a configuration in which the photoconductive current is suppressed (to 10 pA or less) can be achieved. If the LDD region force is smaller than 0.1 m, the electric field relaxation effect is lost and the OFF current increases as shown in FIG. 2 (b).
  • the LDD area should be larger than 0.1 m.
  • the depletion layer width W d is 1 m. Therefore, since the width of the depletion layer cannot be longer than the length of the LDD region, setting the length AL of the LDD region to less than 1.0 makes the effective depletion layer more effective.
  • the area is less than 1.0 m, and the photoconductive current can be suppressed. More preferably, it should be less than 0.4 / m.
  • non-defective and non-defective products are selected by performing an inspection process in which a product whose LDD area length AL is less than 1.0 / xm is defined as a non-defective product. This will be a 5J capability, and material loss at the non-interior level can be reduced.
  • FIG. 17 is a schematic cross-sectional view showing a method of manufacturing a thin-film transistor according to Embodiment 12 of the present invention.
  • FIG. 18 is the same as the thin-film transistor.
  • FIG. 2 is a schematic cross-sectional view showing a production method of the present invention.
  • a-Si layer 15 is deposited on a glass substrate 2 in the same manner as in Embodiment 11 described above, and then an excimer having a wavelength of 300 nm is formed.
  • Polysilicon is not melt-reformed (p-Si) of a-Si layer 15 by laser annealing using a laser.
  • Form layer 16 the polycrystalline silicon layer 16 has a predetermined shape! The islands are formed to form a polycrystalline silicon layer 3.
  • a gate insulating layer 4 is formed so as to cover the polycrystalline silicon layer 3. ( Figure 17 (a)-(d)).
  • a metal layer 17 is formed, and a photo resist is formed on the metal layer 17.
  • the impurity is doped using the gate electrode 5a as a mask.
  • the ion ion is doped by the ion ioning method as a dopant.
  • the channel region 3c located immediately below the gate electrode 5a is a region where impurity force is not doped.
  • LDD regions 3d and 3e are formed in regions located immediately below the oxidation-insulated layers 5b and 5b, and channel regions 3a and drains are formed outside the LDD regions 3d and 3e. A region 3b is formed.
  • an inter-layer insulating layer (S i OX) 6 is formed, and then, an inter-layer insulating layer 6 and a gate are formed.
  • Contact holes 9a and 9b are opened in the insulating layer 4, and a metal layer such as A1 is contacted by the snow method, for example.
  • the source electrode 7 and the drain electrode 8 are formed by filling the metal holes 9a and 9b and patterning the upper portion of the metal layer into a predetermined shape. In this way, a TFT is manufactured.
  • the anodic oxidation of the present embodiment it is possible to reduce the length of the LDD region to 0.2 m to 0.5 ⁇ m. Since the region on the drain side becomes a high-concentration impurity region from this, the width of the depletion layer does not become wider than this length. Therefore, the photoconductive current can be suppressed to a small level.
  • the low-concentration impurity region becomes a high-resistance layer in which the carrier dies, so that the OFF current is low.
  • the above equation (2) further satisfies the equation (6), so that when the thin film transistor is at ⁇ N, the electric field from the gate electrode force and the like is formed.
  • the low-concentration impurity region under the gate electrode becomes a low-resistance region by accumulating the carrier electrons, and the ⁇ K current does not decrease. Therefore, a thin-film transistor that satisfies the expressions (2) and (6) can not only sufficiently secure the ON current but also suppress the FF FF current to a small extent. And become possible.
  • impurity de chromatography pin grayed is, 1 0 k V or more on the 3 0 k V below ⁇ beauty bicycloalkyl over beam current density accelerating voltage 0 0 5 zx AZ cm 2 or more on one;
  • the acceleration voltage of the ion during ion-deeping was low. For example, when doping This can reduce damage. Even when the resist is masked during impurity doping, the resist can be removed without deteriorating the resist.
  • Embodiment 3 of the present invention will be described with reference to FIG. 19 to FIG.
  • FIG. 19 is a plan view showing a wiring pattern of a CMOS integrated circuit using a thin-film transistor according to Embodiment 13 of the present invention.
  • 20 is an equivalent circuit diagram thereof
  • FIG. 21 is a sectional view taken along the line X--X 'in FIG.
  • C — MOS Innocent 50 constitutes, for example, the liquid crystal a; drive circuit of the device.
  • the C-MS interface 50 is composed of an n-channel TFT 22 and a p-channel TFT 23 and power.
  • the n-channel relay TFT 22 has the same configuration as that of the n-channel TFT 1 of the first embodiment, and the corresponding parts are denoted by the same reference numerals.
  • the p-channel TFT 23 is a normal type of TFT that does not have an LDD structure. That is, the TFT 23 is formed on the glass substrate 2 by a polycrystalline silicon layer 24, a gate insulating layer 4 made of SiO 2 (silicon dioxide) gas, A gate electrode 25 made of aluminum nitride, and an inter-layer insulating layer 6 made of Si 0, are sequentially stacked.
  • the polycrystalline silicon layer 24 includes a channel region 24 c located immediately below the gate electrode 25 and source regions disposed on both sides of the channel region 24 c. 24 a (p + layer) and drain region 24 b (p + layer) and force.
  • the TFT 23 is provided with a source electrode 26 and a drain electrode 27 made of, for example, aluminum car, and the TFT 23 is provided.
  • the source electrode 26 is formed of the contact hole 28 a formed on the gate insulating layer 4 and the inter-layer insulating layer 6. Through the source region 24a.
  • the drain electrode 27 is connected via a contact hole 28 b formed in the gate insulating layer 4 and the inter-layer insulating layer 6 to the drain electrode 27. It is connected to the rain area 24b.
  • the gate electrode 5 of the n-channel TFT 22 and the gate electrode 25 of the p-channel TFT 23 are connected to the input terminal 30 as shown in FIG. Commonly connected.
  • the drain electrode 8 of the n-channel TFT 22 and the drain electrode 27 of the p-channel TFT 23 are connected to the output terminal 31 as shown in FIG. Are connected in common.
  • the drain side of the n-channel TFT has the LDD structure described in the embodiment 11 and the TFT of the TFT is provided.
  • the noise can be reduced, and the distance between the source and the train can be reduced to about 6 m, and both the source and the drain can be used.
  • the size can be reduced to about 50% or less, and the TFT can be miniaturized.
  • both the n-channel TFT and the p-channel TFT may have an LDD structure.
  • only one of the n-channel TFT and the p-channel TFT has the LDD structure.
  • the reason for comparing the mobilities of the p-channel TFT carrier and the n-channel TFT carrier is as follows. Is much larger. Therefore, when the same electric field is applied to the p-channel TFT and the n-channel TFT, the n-channel TFT is received by the carrier. The impact is large, so that the n-channel TFT is more likely to deteriorate.
  • Figure 22 shows the operation points in the no-noise state of n-ch transistor at the time of on-Z of the C-MOS in the evening. Show. In this way, the n-ch TFT in the middle of the night: In this case, the polarity of the gate electrode is always higher than 0 V with respect to the power supply on the minus side. Works with. The power supply on the minus side always operates as the source electrode of the n-ch TFT, and the output side always acts as the drain electrode. . Therefore, the use of a circuit in which only the output side portion is configured as described above can reduce the area required for the circuit portion on the array substrate. Donate. It also contributes to the reduction of parasitic capacity in this part.
  • the LDD region having one type of concentration has been described, but the present invention is not limited to this.
  • a plurality of LDD regions having different concentration differences may be provided.
  • the impurity concentration of which gradually decreases toward the channel region is reduced. Since the impurity concentration can be changed in multiple stages, the concentration of the electric field in the semiconductor layer can be further alleviated.
  • the LDD region may be formed only between the drain region and the channel region. By configuring in this manner, the OFF current can be reduced. With the effects of the above, it is possible to reduce the area of the thin film transistor in ft.
  • Embodiments 1-1 to 13 the present invention is applied to the power described using the top gate type TF ⁇ and the bottom gate type TF ⁇ . You can also do it.
  • the thin-film transistor described in Embodiment Modes 11 to 1 to 3 can be applied not only to a liquid crystal display device but also to an EL device. . That is, a plurality of the thin film transistors described in the embodiments 11 to 11 are formed as switching elements on a substrate, and the substrate is provided. By using the EL device, it is possible to achieve a configuration in which the photoconductive current is suppressed.
  • the present invention suppresses the OFF current of a thin film transistor (hereinafter referred to as “TFT”), and also minimizes the length of the LDD region to a necessary minimum.
  • TFT thin film transistor
  • the purpose is to realize a TFT with high performance and high reliability. Therefore, in order to obtain the truly required length of the LDD region, the tree inventors perform a motion analysis of the LDD region portion by simulation. In addition, the degree of power in the region where the electric field is applied was determined.
  • Figure 23 shows the simulated Vg-Id characteristics when the LDD region is varied from 0.5 m to 3 wm with the sheet resistance as a parameter.
  • -A graph showing the result of the shot.
  • V g-I d characteristic has a large dependence on the concentration of the LDD region, but does not have a dependence on the length of the LDD region. It was done. We will discuss this cause below.
  • the area where the electric field is applied depends on the sheet resistance.
  • the sheet resistance is 20 2 ⁇ ⁇ , it is about 0.4 m. It was confirmed that the sheet resistance was 1. ⁇ when the sheet resistance was ⁇ ⁇ ⁇ .
  • FIG. 25 shows the relationship between the length of the LDD region (AL), the OFF current, the length of the LDD region (AL), and the ON current of a TFT having an actual LDD region. This is the graph shown.
  • the sheet resistance in the LDD area is 100 ⁇ .
  • FIG. 26 is a simplified cross-sectional view of the thin-film transistor according to the embodiment 2-1.
  • FIG. 27 is a schematic plan view of FIG.
  • Embodiment 2-1 shows an example in which the present invention is applied to an n-channel thin film transistor.
  • the thin film transistor (hereinafter referred to as “FT”) 101 is a polycrystalline silicon layer having a film thickness of 500 A on a glass substrate 102. 1 0 3, thickness force 1 0 0 0 a of S i ⁇ 2 (dioxide Shi Li co down) mosquito ⁇ Naru Luo Ru gate insulating layer 1 0 4, a Le mini U beam or Naru Luo Ru gate one Bok
  • the electrode 105 and the inter-layer insulating layer 106 composed of Si 2 layers are stacked in this order. It is composed.
  • the gate electrode 105a is formed so as to be covered with a resist film 105b.
  • a metal film may be used in place of the resist film 105.
  • the polysilicon layer ⁇ 03 has a channel region 103c located immediately below the gate electrode 105a, and a silicon layer having a high impurity concentration.
  • Source region 103 a (n ten layers), drain region with high impurity concentration (n + layer) 103 b, and low-concentration impurity region with low impurity concentration (LDD area: II-layer) This is composed of 103d and 103e.
  • the low-concentration impurity region 103d is interposed between the source region 103a and the channel region 103c, and the low-concentration impurity region 103e is connected to the drain region. Between the channel region 103b and the channel region 103c.
  • These low-concentration small-pure regions 03d and 103e are portions 105b1 of the resist film 105b protruding from the gate electrode 105a. It is located just below 105b2. Therefore, the junction surface between the low-concentration impurity region 103 d and the source region 103 a is almost equal to the end surface of the resist film 105 b (the left end surface in FIG. 1). The junction surface between the low-concentration impurity region 103d and the channel region 103c is almost the same as the end surface of the gate electrode 105a (left end surface in FIG. 1). Align and review.
  • the junction between the low-concentration impurity region 103 e and the drain region 103 b is substantially equal to the end surface of the resist film 105 b (the right end surface in FIG. 1).
  • the junction surface between the low-concentration impurity region 103d and the channel region 103c is the same as the end surface of the gate electrode 105a (the right end surface in FIG. 1). ).
  • the length ⁇ L of the low-concentration impurity region is set to 1 m or more and 1.5 m or less, and the channel width W is set to 5 m.
  • the TFT 101 is further provided with a source electrode 107 made of, for example, aluminum and a drain electrode 108.
  • Source The electrode 107 is connected via a contact hole 109 a formed in the gate insulating layer 104 and the layer insulating layer 106 to the And the drain electrode 108 is formed in the gate insulating layer 104 and the inter-layer insulating layer 106. It is connected to the drain area 103b via the contact hole 109b.
  • FIGS. 28 and 29 are schematic cross-sectional views showing a method of manufacturing a thin-film transistor according to Embodiment 2-1 of the present invention
  • FIG. This is a flowchart showing a method of manufacturing a thin film transistor according to the embodiment 2-1 of the present invention.
  • an a-Si layer 105 with a thickness of 50 OA was deposited on the glass substrate 1002 by plasma CVD.
  • the dehydrogenation is performed at 400 (Fig. 28 (a)).
  • the purpose of this dehydrogenation treatment is to prevent the generation of abrasion of the Si film due to desorption of hydrogen during crystallization. Yes.
  • a process such as a decompression CVD / snotter other than the plasma CVD.
  • a polysilicon film can be directly deposited using plasma CVD or other methods. In this case, the anneal process by the laser described later is not required.
  • the polycrystalline silicon layer 1 16 is formed into islands in a predetermined shape to form the polycrystalline silicon layer 103 (FIG. 28 (c)). ).
  • the gate insulating layer 104 is formed on the glass substrate 102 so as to cover the polycrystalline silicon layer 103. Thickness force 1 0 0 0 A To form a Si ( 2 (dioxide silicon) layer (FIG. 28 (d)).
  • the metal layer 111 is patterned into a predetermined shape to form a gate electrode 105a (FIG. 28 (f)).
  • the gate electrode 105a as a mask and perform the first impurity doping (Fig. 28 (g)). Specifically, the ion ion is doped by ion ioning as a dopant. Thus, the channel region 103C located immediately below the gate electrode 105a is a region where impurities are not doped. Then, regions A and B excluding the channel region 103c of the multi-component silicon layer 103 become n-layers doped with impurities. .
  • FIG. 31 is a schematic cross-sectional view illustrating a process of forming an LDD region
  • FIG. 32 is a perspective view of a photomask and a substrate
  • FIG. 33 is a plan view of the same
  • FIG. 34 is a schematic cross-sectional view of the thin film transistor after the LDD region is formed.
  • the photomask 140 and the substrate 102 are arranged so as to face each other, and the photomask 140 is located above the photomask 140.
  • a positioning light source (not shown) is provided, and is formed on the photomask 140 and the substrate 102 respectively from the positioning light source. Done alignment A laser beam is incident on the set mark 1 4 1 ⁇ 1 4 2 and the position of each mark is read to read the position signal of the mark. Make sure that alignment is performed.
  • a substantially square alignment mark is provided at the position of the photomask 140 (102 cylinders at the corners of the photomask). Is formed. In the center of the photomask 140, a pattern (not shown) of a shielding film to be transferred to the substrate 102 is formed.
  • a positioning mark 142 is formed at a position corresponding to the positioning mark 141.
  • the alignment mark 142 is a substantially square transparent region whose periphery is surrounded by a black region.
  • the shape of the alignment mark 14 1 ⁇ 14 2 is not limited to a square shape, and may be, for example, a circular shape. You can also do
  • the photomask 140 and the substrate 102 are not displaced from each other, the photomask 140 is not displaced.
  • the alignment mark 14 1 formed on the substrate 140 is located at the center of the transparent area of the alignment mark 14 2 formed on the substrate 102.
  • the length ⁇ L of the LDD region 103 d ⁇ 103 e is 1.25 / m. It has been set.
  • the positions of the substrate and the photo mask 140 are shifted from each other, and the positioning mark 14 1 is included in the positioning mark 14 2. Otherwise, the length of the LDD region formed will be found to be greater than 1.5 xm, and therefore, in such cases, the alignment will be necessary.
  • the board and the photomask should be aligned so that the mark 14 1 is positioned within the mark 14 2. It should be noted that even if the alignment mark 14 1 is aligned with the center of the mark 14 2, actually, 33 As shown in (b), there is strong force when the paper is shaken left and right on the paper. However, in the case of the present invention, since the accuracy of the positioning device is ⁇ 0.25 m, the positioning mark is positioned within the positioning mark 42. To position mark 41.
  • the length of the LDD region 3d'3e it is possible to force the length of the LDD region 3d'3e to be formed to be within 1 to 1.5 m. It is. Note that the accuracy of the positioning device is ⁇ 0.25) im, and if a more accurate positioning device is used, the deviation of the LDD area will vary. It can be even smaller.
  • a photo resist serving as a shielding film is formed on the gate electrode 105a.
  • the photo resist is irradiated with S light via a photo mask 140 to perform development. Then, a predetermined pattern of the shielding film 105b is formed.
  • the resist film 105b is used as a mask, and the second impurity doping is performed.
  • the ion ion is doped as an impurity by the ion doping method.
  • the doping acceleration voltage is 12 kV
  • the beam current density is 0.5 A, / cm 2
  • an n-type region with low acceleration and high concentration is created. It is.
  • the ion force is applied to the region of the polycrystalline silicon layer 103 except for the region located immediately below the resist film 105b. Is locked. Yotsu Therefore, the resist film 105b of the region A.B in which impurities have already been doped by the first ion doping, the resist film 105b; In the undivided regions (source region 103a, drain region 103b: equivalent), the impurity power is further increased. In other words, the impurity-rich region (n + layer) is this.
  • the resist film 105b the region covered by the resist film (corresponding to the low concentration impurity regions 103d and 103e) According to the second ion doping, impurity doping is not performed, and a low-concentration impurity region (n-layer) is formed.
  • the source area 103 a the region covered by the resist film (corresponding to the low concentration impurity regions 103d and 103e)
  • a low-concentration impurity region 103d (n-layer) is formed between the (n + layer) and the channel region 103c, and a drain region 103b (n -Layer) and the channel region 103c can be used to form a low-concentration impurity region 103e (n-layer).
  • the first ion doping is performed using the gate electrode 105a as a mask, and further, the resist film is formed.
  • the source region 103 a and the low-concentration impurity regions 103 d and 10 3 e and the drain region 103 b are formed in a self-aligned manner;
  • contact holes 1109a and 109b are opened in the inter-layer insulating layer 106 and the gate insulating layer 104 (Fig. 2 9 (d)).
  • a metal layer such as A1 is connected to contact holes' 109a and 109b.
  • the upper part of the metal layer is patterned into a predetermined shape to form a source electrode 107 and a drain recess 108 (FIG. 29 ( e))).
  • the TFT 101 is manufactured.
  • the n-channel TFT has been described, but the p-channel TFT can be manufactured by a similar manufacturing process. You can do it.
  • Figure 35 shows the voltage and Z-voltage characteristics of the thin-film transistor made by the BiJ manufacturing method.
  • Fig. 36 shows the variation of the ⁇ F current in the substrate plane.
  • the LDD region which is a resistance region, is as small as i to 1.5 m. Therefore, a stable large ⁇ N current and a small 0 FF current could be secured.
  • the aligner accuracy of the aligner is improved, it goes without saying that the length of the LDD area can be further reduced, and that it is a power city capability.
  • the region where the electric field is applied becomes smaller, but the peak value of the electric field becomes higher. In order to achieve this, the current of the zero-th F increases.
  • Figure 37 shows the results of a simulation of the Vg_Id characteristics of a thin film transistor where the concentration of the LDD region was assumed to be normal.
  • the sheet resistance in the LDD region is 20 k ⁇ noro or less, the OFF current increases rapidly. Therefore, the sheet resistance in the n- region must be at least 2 Ok ⁇ ⁇ .
  • the sheet resistance in the LDD region is set to 100 k ⁇ or more, the ⁇ N current of the transistor decreases and the The operation of the cell became unstable.
  • the range of the sheet resistance in the LDD region should be not less than 20 kQZC] and not more than 10 ⁇ ⁇ ⁇ ⁇ , and in addition to the power requirement, the first impurity over pin grayed the acceleration voltage is 1 0 k V or more on the 3 0 k V hereinafter ⁇ beauty bicycloalkyl over beam current density 0 0 5 -. AZ cm 2 or more Interview a / cm 2 low-speed following
  • the ion accelerating voltage during ion-doping is so low that It can reduce damage at times.
  • the resist can be removed without being deteriorated. .
  • the second impurity doping is performed at an accelerating voltage of ';' higher than 30 kV and at a high speed with a beam current density of 1 AZcm 2 or higher. It is also possible to inject enough ions into the polysilicon even at the 2 1 ⁇ Jth ion doping by using the doping method. is there .
  • the length ⁇ L of the LDD region constituting the TFT 101 is 1 / im or more and 1.5 m or less, and the source-drain The inter-voltage VIc is 6 V, and the channel width W is 6 m.
  • the OFF current is determined by the electric field between the source and the drain, and V 1c is applied only to the channel region and the LDD region. Therefore, the strength of the electric field is expressed as V 1 c (solid static
  • Table 2 shows the characteristics of the TFT in which the length ⁇ L of the LDD region, the source-drain electrode V1c, and the channel width W are changed.
  • the above equation (4) indicates the limitation of the ⁇ ⁇ current, and the ⁇ ⁇ current is a condition derived from the fact that the ⁇ ⁇ current is proportional to W / L.
  • the ⁇ N current is calculated by the following equation (4). You can be assured.
  • the low-concentration impurity region becomes a high-resistance layer in which the carrier is depleted, so that the FF current can be reduced.
  • the expression (3) further satisfies the expression (4), and when the thin film transistor is at 0N, the action of the electric field from the gate electrode is obtained. Accordingly, the low-concentration impurity region under the gate electrode becomes a low-resistance region by accumulating the carrier electrons, and the ON current does not decrease. Therefore, a thin-film transistor satisfying the expressions (3) and (4) can suppress the OFF current small while securing a sufficient ⁇ N current. Will be possible.
  • the channel width is 5 m and the channel width W in the channel region is reduced to 2 m or less, the channel width is particularly small.
  • the above-mentioned relational expressions (3) and (4) serve as effective guidelines for producing a thin film transistor.
  • Embodiment 2-2 of the present invention when the resist film 105b is formed in the manufacturing process of Embodiment 2-1 described above, the alignment mark is formed.
  • the length of the LDD region is not limited to 1 or more and 1.5 or less,
  • the LDD region is not limited to 1.5 ⁇ ⁇ or less, but described in Embodiment 2-1 of this embodiment.
  • the range of equations (3) and (4) can be applied.
  • low-concentration impurity regions having one type of concentration have been described, but the present invention is not limited to this.
  • a plurality of low-concentration impurity regions having different concentration differences may be provided.
  • the low-concentration impurity region is directed to the channel region!
  • the impurity concentration gradually decreases, it is possible to change the impurity concentration in multiple stages by using a plurality of junction regions. Therefore, the concentration of the electric field in the semiconductor layer can be further reduced.
  • the low-concentration impurity region may be formed only between the drain region and the channel region. By configuring in this way, the OFF current can be reduced. In addition to the effect of reducing the size, it is possible to reduce the area of the thin-film transistor. Furthermore, such a thin film transistor can be applied to a device other than a liquid crystal display device.
  • the circuit is an overnight circuit of the C-MOS transistor, at least one of a p-channel thin-film transistor and an n-channel thin-film transistor is used.
  • the n-channel thin-film transistor can also be constituted by the thin-film transistor according to the embodiments 2-1 and 2-2.
  • the first invention group it is possible to secure a sufficient ⁇ N current and to suppress the photoconductive current at the time of light irradiation to a small extent, which leads to a reduction in power consumption.
  • the power is small, and the effect is extremely large for improving reliability and improving reliability.
  • the second invention group it is possible to secure a sufficient ON current and to suppress the OFF current to a small extent, thereby reducing power consumption.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

Selon l'invention, un transistor à couche mince très performant et très fiable est obtenu par suppression du courant de mise hors service (courant de photoconduction) pendant l'irradiation avec la lumière. Le transistor à couche mince comprend une couche semiconductrice en silicium polycristallin présentant une région de canal, une région source et une région de drain formées de part et d'autre de la région de canal, et une couche d'épuisement formée entre la région de canal et la région de drain. La largeur de la couche d'épuisement est proportionnelle au courant de photoconduction généré lorsque la région de canal est irradiée avec de la lumière. La largeur de la couche d'épuisement est égale ou inférieure à la valeur établie conformément au rapport proportionnel, afin de réguler le courant de photoconduction dans une plage attribuée précise.
PCT/JP2000/006330 2000-04-28 2000-09-14 Transistor a couche mince et son procede de fabrication, et ecran a cristaux liquides comprenant ledit transistor WO2001084635A1 (fr)

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Cited By (1)

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US9329309B2 (en) 2012-02-27 2016-05-03 E-Vision Smart Optics, Inc. Electroactive lens with multiple depth diffractive structures

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Publication number Priority date Publication date Assignee Title
KR100606450B1 (ko) * 2003-12-29 2006-08-11 엘지.필립스 엘시디 주식회사 주기성을 가진 패턴이 형성된 레이저 마스크 및 이를이용한 결정화방법
CN101488445B (zh) * 2008-01-15 2011-04-20 中芯国际集成电路制造(上海)有限公司 用于减轻65纳米以上节点的Ioff散射的方法
JP5305696B2 (ja) * 2008-03-06 2013-10-02 キヤノン株式会社 半導体素子の処理方法

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JPH0572555A (ja) * 1991-09-13 1993-03-26 Seiko Epson Corp 薄膜トランジスター
US5308998A (en) * 1991-08-26 1994-05-03 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode
JPH10293322A (ja) * 1997-04-21 1998-11-04 Canon Inc 液晶表示装置およびその製造方法
US5977559A (en) * 1995-09-29 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor having a catalyst element in its active regions

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US5308998A (en) * 1991-08-26 1994-05-03 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode
JPH0572555A (ja) * 1991-09-13 1993-03-26 Seiko Epson Corp 薄膜トランジスター
US5977559A (en) * 1995-09-29 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor having a catalyst element in its active regions
JPH10293322A (ja) * 1997-04-21 1998-11-04 Canon Inc 液晶表示装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9329309B2 (en) 2012-02-27 2016-05-03 E-Vision Smart Optics, Inc. Electroactive lens with multiple depth diffractive structures
US10054725B2 (en) 2012-02-27 2018-08-21 E-Vision Smart Optics, Inc. Electroactive lens with multiple depth diffractive structures

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TW474016B (en) 2002-01-21
KR100473237B1 (ko) 2005-03-09
CN1359541A (zh) 2002-07-17

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