TW474016B - Thin film transistor and method for producing the same, and liquid crystal display device using the same - Google Patents

Thin film transistor and method for producing the same, and liquid crystal display device using the same Download PDF

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TW474016B
TW474016B TW089118963A TW89118963A TW474016B TW 474016 B TW474016 B TW 474016B TW 089118963 A TW089118963 A TW 089118963A TW 89118963 A TW89118963 A TW 89118963A TW 474016 B TW474016 B TW 474016B
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region
aforementioned
film transistor
thin film
channel
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Yutaka Nanno
Takashi Okada
Atsunori Yamano
Kouji Senda
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Matsushita Electric Ind Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/42—Arrangements for providing conduction through an insulating substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/12—Materials and properties photoconductor

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention provides a thin film transistor having a high quality and reliability that can suppress a photoconduction current generated by incoming light. The thin film transistor has a polycrystalline silicon semiconductor layer in which a channel region, a source region, and a drain region are formed. And, the source region and the drain region are placed at opposite sides of the channel region, and a depletion layer is formed between the channel region and the drain region. The width of the depletion layer is in proportion to an amount of the photoconduction current generated when the channel region is irradiated with light. The width of the thin film transistor is to be maintained under a value obtained based upon the proportional relation, so that the amount of the photoconduction current is restricted within the range of predetermined allowed values.

Description

474016 A7474016 A7

五、發明說明（1 ) 【發明之技術領域】 本發明係有關於薄膜電晶體及其製造方法、以及使用 該薄膜電晶體之液晶顯示裝置。 【發明之技術背景】 習知上以非晶矽（以下稱Γ a—Si」）所形成之動態矩 陣型液晶顯示裝置之像素的驅動性能乃以Si即充分滿 足要求，惟，於同一基板上以相同的處理來構成信號線之 驅動電路的情形時具有性能上的困難，而係使用藉著單結 曰曰Si來形成之外加的驅動電路（Driver)以驅動顯示板。 然而，a—Si之移動度為〇· 5〜lcm2 · S—1 · V—1，今後 於液晶顯示面板之像素數增大的情形下，一般而言，將相 當於最大1水平期間之像素的TFT設為ON時間係愈來愈短而 寫入像素之能力呈現不足。 相對於此，以聚矽來製成像素之TFT，而此TFT之移動 度比較於以a— Si製成的情形，則以聚矽來製成像素之TFT 朝向高1格以至於2格以上像素之充電能力變高。因此，隨 著液晶顯示面板之高度精細化而以P—Si來形成像素TFT者 乃較有利（FPD Expo Forum97，2 — 14)。 一般而言，P—SiTFT之構造係存在有閘極電極設置於 通道層上方的上閘極型，以及閘極電極相對於通道層而存 在於基板側的底閘極型等2種類。上閘極型之構造比較於 底閘極型，係藉著以閘極電極作為遮罩而自行整合性地摻 入不純物，而能製成寄生容量小的TFT，其有利於微細化 〇 例如將上述上閘極型TFT應用於液晶顯示裝置而從該 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ij -------卜丨丨卜丨」——·----#裝--------訂I-——，----線#· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 【74016 r_______ B7 五、發明說明（2 ) TFT的背面照射光線時，背光之光線能直接照射於TFT的通 道區域。至於一旦前述通道區域被光線照射的話，則有在 此部分發生光傳導電流而使OFF電流變大的問題。在此， 即說明「光傳導電流」。 在半導體中發生光傳導電流之機械性構造上以太陽電 池等為中心者，至今為止已有許多的論文（例如，田中一 宣編著之”非晶質半導體的基礎”，1982年）被揭示，惟， 有關以P — SiTFT來構成發生光傳導電流之機械性構造者乃 未曾被提出。 一般而言，光傳導電流之發生，係以施加電場的狀態 透過頻帶間距而生成電子/正孔對，經生成之電子 對It者電％而漂移’對於在各別的區域多數載體的增加， 而可觀測到為載體之再結合電流形態者。閘極電極下的通 道區域在反偏壓條件下，雖然在通道之正下方引起正孔， 惟其載體之濃度極低。相對於此，作為汲極側之多數載體 的電子乃可推知η—區域之薄片阻抗為20kQ/□〜lOOkQ /□之範圍内為1016/cm3〜1018/cm3左右的載體密度。此 情形下，作為η—區域之多數載體的電子係朝著通道侧而 擴散並形成擴散電位Vd。又，空乏層之寬度以W來表示。 藉著照射光線，在此空乏化區域發生電子/正孔對。 所發生之電子/正孔對乃相互地被電場吸引之電子係朝没 極方向，而孔則朝通道方向移動。朝汲極側移動之電子及 朝通道側移動的正孔乃在各別的區域再結合而消滅。此此 再結合所消耗之電荷係分別藉由源極及汲極電極來供給， 此乃為光傳導電流而可觀測。 ，本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） ------ (請先閱讀背面之注意事項再填寫本頁) 言 Γ 經濟部智慧財產局員工消費合作社印製 474016V. Description of the invention (1) [Technical field of the invention] The present invention relates to a thin film transistor and a method for manufacturing the same, and a liquid crystal display device using the thin film transistor. [Technical Background of the Invention] Conventionally, the driving performance of a pixel of a dynamic matrix liquid crystal display device formed of amorphous silicon (hereinafter referred to as Γ a-Si ") fully satisfies the requirements, but on the same substrate In the case where the driving circuit of the signal line is constituted by the same process, there is a performance difficulty, and an additional driving circuit (Driver) is formed by using a single junction Si to drive the display panel. However, the mobility of a-Si is 0.5 to 1 cm2 · S-1 · V-1. In the future, when the number of pixels of a liquid crystal display panel increases, it will generally correspond to a maximum of one horizontal period. The time when the TFT is set to ON is shorter and shorter, and the ability to write pixels is insufficient. In contrast, the TFT of a pixel is made of polysilicon, and the mobility of this TFT is compared to the case of a-Si. The TFT of a pixel made of polysilicon is 1 grid higher than 2 grids. The charging capacity of the pixels becomes higher. Therefore, it is advantageous to form pixel TFTs with P-Si as the liquid crystal display panel becomes highly refined (FPD Expo Forum 97, 2-14). Generally, there are two types of P-SiTFT structures: an upper gate type in which a gate electrode is provided above a channel layer, and a bottom gate type in which the gate electrode is on the substrate side with respect to the channel layer. The structure of the upper gate type is compared with the bottom gate type. The gate electrode is used as a mask to incorporate impurities into the gate electrode itself, and it can be made into a TFT with a small parasitic capacity. The above gate-type TFT is applied to a liquid crystal display device, and from this -4- paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. —— · ## 装 -------- Order I -—— ， ---- 线 # (Please read the notes on the back before filling in this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative A7 [74016 r_______ B7 V. Description of the invention (2) When the back side of the TFT is irradiated with light, the backlight light can directly shine on the channel area of the TFT. When the aforementioned channel region is irradiated with light, there is a problem that a photoconductive current occurs in this portion and the OFF current becomes large. Here, the "photoconductive current" will be described. For the mechanical structure that generates photoconductive current in semiconductors, focusing on solar cells, etc., many papers have been published so far (for example, "The Foundation of Amorphous Semiconductors" by Tanaka Ichio, 1982). However, no proposal has been made regarding the use of P-SiTFT to constitute a mechanical structure that generates a photoconductive current. Generally speaking, the occurrence of photoconductive current is to generate an electron / positive hole pair through the frequency band gap in the state of an applied electric field. The generated electron pair drifts by% of its electricity. For the increase of the majority of carriers in each region, It can be observed that it is the recombination current pattern of the carrier. The channel area under the gate electrode under reverse bias conditions causes positive holes just below the channel, but its carrier concentration is extremely low. On the other hand, as the electrons of most carriers on the drain side, it can be inferred that the sheet impedance of the η-region is about 2016 / cm3 to 1018 / cm3 in the range of 20kQ / □ to 100kQ / □. In this case, the electron system, which is the majority carrier of the η-region, diffuses toward the channel side and forms a diffusion potential Vd. The width of the empty layer is represented by W. Electron / positive hole pairs occur in this empty region by irradiating light. The resulting electron / positive hole pair is an electron system attracted to each other by the electric field toward the electrode, while the hole moves toward the channel. The electrons moving toward the drain side and the positive holes moving toward the channel side are combined and eliminated in separate areas. The charges consumed in combination with this are supplied through the source and drain electrodes, respectively, which are observable for the photoconductive current. , This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ------ (Please read the precautions on the back before filling this page) 474016

經濟部智慧財產局員工消費合作社印製 五、發明說明（3 ) 藉著上述之光傳導電流，於增加（OFF特性之劣化）〇ff 電流的情形下，即產生以下的問題。 因OFF特性之劣化所引起之晝質劣化為輝度傾斜與串 擾。輝度傾斜乃如第38圖（a)所示，在畫面之上部及下部 ’因液晶之電流/輝度不同而產生者，而在畫面之上部及 下部產生輝度差。另一方面，串擾乃如第38圖（1))所示於 中央部顯示黑色之區塊圖樣的情形下，黑色之影像向上下 或左右方向拉著尾巴的現象。又，此外，特性之劣化 造成閃爍的增加、發生輝度不均等情形而對晝質影響很大 (第2背景技術） 又，由於P—Si TFT係高移動度，因此，能將畫面内的 動態矩陣元件與信號驅動電路動電路之一部分或全部同時 形成在玻璃基板上。但是P—SiTFT比較於a-SiTFT或MOS 型電解效果電晶體乃具有OFF電流大的缺點。 爰此，為了降低此OFF電流，如特開平5— 136417號所 揭示那般地，進行鄰接於TFT之源極區域或汲極區域之至 少一方而設置低濃度不純物質（LDD區域）的方法（第1習知 方法）。 又，形成LDD區域之其他方法乃已揭示有藉著有無TaOx 而控制LDD區域的方法（Euro Display，96 pp547)。 有關於LDD區域對於OFF電流區域有效的機械裝置乃如 特開平5— 136417號所揭示那般地，由於LDD區域相對於汲 極區域呈高阻抗，故設計在通孔/LDD區域之接合部的電 場相對於不設置LDD區域的情形為小。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 卜丨丨—·----·裝--------訂_——.----線_· (請先閱讀背面之注意事項再填寫本頁) A7Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (3) The above-mentioned photoconductive current increases the (deterioration of OFF characteristic) current by 0ff, which causes the following problems. The deterioration of the daytime quality due to the deterioration of the OFF characteristic is the brightness tilt and crosstalk. As shown in Fig. 38 (a), the luminance tilt is caused by the difference in the current / luminance of the liquid crystal in the upper and lower portions of the screen, and the luminance difference occurs in the upper and lower portions of the screen. On the other hand, crosstalk is a phenomenon where a black block pattern is displayed in the center as shown in Fig. 38 (1)), and the black image pulls the tail up or down or left and right. In addition, the degradation of characteristics has a large effect on daylight quality due to an increase in flicker and uneven brightness (second background art). Because P-Si TFTs have high mobility, the dynamics in the screen can be changed. A part or all of the matrix element and the signal driving circuit are formed on the glass substrate at the same time. However, compared with a-SiTFT or MOS type electrolytic effect transistor, P-SiTFT has the disadvantage of large OFF current. Therefore, in order to reduce this OFF current, as disclosed in Japanese Patent Application Laid-Open No. 5-136417, a method of providing a low-concentration impurity (LDD region) adjacent to at least one of the source region and the drain region of the TFT is performed ( No. 1 method). In addition, other methods of forming the LDD region have been disclosed as a method of controlling the LDD region by the presence or absence of TaOx (Euro Display, 96 pp547). The mechanism for the LDD region to be effective for the OFF current region is as disclosed in Japanese Patent Application Laid-Open No. 5-136417. Since the LDD region has a high impedance relative to the drain region, it is designed at the junction of the via / LDD region. The electric field is small compared to the case where the LDD region is not provided. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm). 丨 丨 —————— Installation -------- Order _——.---- Line_ · (Please read the notes on the back before filling this page) A7

^74010 五、發明說明（4 ) 以上所述之二種方法中的任合一種均藉著使LDD區域 合遮罩而控制有無TaOx，或控制有無光阻膜而形成摻入濃 度不同的部分。此方法為了確保LDD之區域而必須確保LDD 區域之長度在合遮罩之尺寸精度以上的長度。 相對於此，如特開平7一14〇485號所示，具有將LDD區 域相對於閘極電極而呈自行整合地形成的第3習知方法。 係藉著將形成閘極電極之A1予以陽極氧化而於其側面形成 A1的氧化物，將此作為遮罩而導入N型或p型之不純物元素 而能作成具有與源極區域、汲極區域及前述側面之氧化物 層約相同厚度的低濃度不純物層。 使用此方法的話，相對於閘極電極而能自行整合地形 成LDD區域，能削減用以形成LDD區域之遮罩，同時能將不 純物濃度高之區域的長度形成相當於存在陽極氧化之AH^j 面之氧化物膜厚的〇.l//m〜0.5/zm左右之極小狀態。 LDD構造對於降低OFF電流負具有高的效果，惟，TFT 之閘極電極下之通道在反轉之ON狀態下，藉著比較上較高 的阻抗層之LDD區域串聯地插入通道區域而具有ON電流降 低的缺點。 本來，LDD區域具有相對於源極及汲極區域部分，隨 著高阻抗之TFT特性的提昇而使其阻抗之影響顯著地顯現_ 的傾向。因此，此高阻抗區域之LDD區域的長度在降低其OFF 電流方面乃能具足，且在確保高ON電流方面必須是具有充 分的低阻抗值。 但是現實狀況乃全無決定LDD區域之長度之方針的方 法，為了降低OFF電流，有必要在必要以上確保LDD區域。 ，本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝-----I--訂！！ 線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7^ 74010 V. Description of the Invention (4) In any of the two methods described above, the presence or absence of TaOx is controlled by combining the LDD region with a mask, or the presence or absence of a photoresist film to form portions with different concentrations. In order to ensure the LDD area, this method must ensure that the length of the LDD area is longer than the dimensional accuracy of the mask. On the other hand, as shown in Japanese Patent Application Laid-Open No. 7-1440485, there is a third known method in which the LDD region is formed in a self-integrated manner with respect to the gate electrode. By anodic oxidation of A1 forming the gate electrode and forming an oxide of A1 on its side, this can be used as a mask to introduce an N-type or p-type impurity element to have a source region and a drain region. A low-concentration impurity layer of approximately the same thickness as the oxide layer on the side. Using this method, it is possible to form the LDD region in an integrated manner with respect to the gate electrode, reduce the mask used to form the LDD region, and at the same time, form the length of the region with a high impurity concentration equivalent to AH ^ j where anodization exists. The surface oxide film thickness is extremely small at about 0.1 // m to 0.5 / zm. The LDD structure has a high effect on reducing the negative of the OFF current. However, the channel under the gate electrode of the TFT is turned on in the reversed state, and is turned on by inserting the LDD region of the higher impedance layer in series to the channel region in series. Disadvantages of reduced current. Originally, the LDD region tends to have a significant effect on the impedance due to the improvement of the characteristics of the high-resistance TFT with respect to the source and drain regions. Therefore, the length of the LDD region of this high-impedance region is sufficient to reduce its OFF current, and it must have a sufficiently low impedance value to ensure a high ON-current. However, in reality, there is no method to determine the length of the LDD region. In order to reduce the OFF current, it is necessary to secure the LDD region more than necessary. , This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- Installation ----- I--Order! !! (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7

474016 五、發明說明（5 ) 一般而言，有必要確保比1 · 5 // m更長的LDD區域，其結果 即造成降低TFT之ON電流的原因。 又，依據第3習知例所示之方法，雖然能將LDD區域形 成〇· 1//m〜0· 5 # m左右之極小的狀態，惟，一般而言作為 液晶顯示面板之驅動器或像素之TFT來使用的情形下，其 驅動電壓為5〜15V左右，比較於一般的ic就顯得極高。因 此，LDD區域為0· 1 " m〜0· 5//m的情形下，其效果乃不充 分而在本實施中不能充分地降低OFF電流。 爰此，本發明乃有鑑於上述之問題點，其第i目的乃 在於藉由形成能構成抑制光照射時之OFF電流（光傳導電流 )而抑制輝度傾斜或串擾等之畫質劣化，而能提供實現高 性能、高信賴度之薄膜電晶體。 又，本發明之第2目的係在抑制OFF電流之同時， 藉著能—將LDD區域之長度宥限至最小限度而抑制on電流之 降低的構成，而能提供實現高性能、高信賴度之薄臈電晶 體。 【發明之揭示】 亦即，為了解決上述之問題，本發明之申請專利範圍 第1項所記載之發明係一種對膜電晶體，其特徵在於：具 有通道區域；由配置於該通道兩側之源極區域及汲極區域 所形成之多晶石夕半導體層；前述通道區域及前述没極區域 之間形成空乏層，該空乏層之寬度與前述通道區域被光照 射之情形下所發生之光傳導電流乃具有比例關係，為使前 述光傳導電流設於一定容許值内，乃將空乏層之寬度設定 在基於前述比例關係所求出之值如以下的構成者。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） h---_---*----#裝--------訂…---.----線# (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 B7474016 V. Description of the invention (5) Generally speaking, it is necessary to ensure an LDD region longer than 1 · 5 // m, and as a result, the reason for reducing the ON current of the TFT is caused. In addition, according to the method shown in the third conventional example, although the LDD region can be formed to a very small state of about 0.1 // m to 0.5 #m, it is generally used as a driver or a pixel of a liquid crystal display panel. When the TFT is used, the driving voltage is about 5 to 15V, which is extremely high compared to the general ic. Therefore, in the case where the LDD region is from 0.1 " m to 0.5 // m, the effect is insufficient and the OFF current cannot be sufficiently reduced in this embodiment. Therefore, the present invention has been made in view of the above-mentioned problems, and its i-th object is to suppress deterioration of image quality such as luminance tilt and crosstalk by forming an OFF current (photoconductive current) that suppresses light irradiation when light is irradiated. Provide thin film transistors that achieve high performance and high reliability. In addition, the second object of the present invention is to provide a structure capable of realizing high performance and high reliability by suppressing the reduction of the on current while suppressing the OFF current while minimizing the length of the LDD region. Thin chirped crystal. [Disclosure of the invention] That is, in order to solve the above problems, the invention described in the first patent application scope of the present invention is a pair of film transistors, which is characterized by: having a channel region; A polycrystalline silicon semiconductor layer formed in a source region and a drain region; an empty layer is formed between the aforementioned channel region and the aforementioned non-electrode region, and the width of the empty layer and the light generated when the aforementioned channel region is illuminated by light The conduction current has a proportional relationship. In order to set the photoconductive current within a certain allowable value, the width of the empty layer is set to a value obtained based on the aforementioned proportional relationship as follows. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) h ---_--- * ---- # 装 -------- Order ...---.-- -线 # (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7

474016 五、發明說明（6 ) 如上所述，空乏層寬度具有與光傳導電流的比例關係 乃新的發現，藉此，能提供藉著控制空乏層寬度而達到將 光傳導電流設於-定的容許值以下，而無輝度傾斜及串擾 等畫質劣化情形之薄膜電晶體。 又’申請專利範圍第2項之發明係如申請專利範圍約 項之薄膜電晶體，其特徵在於：將前述沒極區域之薄片阻 抗設為而將前述通道區域之通道寬度設為w( 以m)的情形下，滿足式子（1)之關係。 又，A係依據光傳導電流與光強度而設定之定數。 (R+30) · W < A …⑴ 又，申請專利範圍第3項之發明係如申請專利範圍第2 項之薄膜電晶體，其特徵在於：將前述沒極區域之薄片阻 抗設為R(kQ/[U),而將前述通道區域之通道寬度設為w( #m)的情形下，滿足式子（2)之關係。 (R+30) · W < 1* ίο3 …（2) 如上述式子（1)、式子（2)，藉由能新控制之因子（汲 極區域之薄片阻抗）與通道區域之通道寬度的關係而能規 定該控制光照射時之OFF電流（光傳導電流）的範圍。而滿 足上述式子（1)、式子（2)之關係的薄膜電晶體能抑制光照 射時之OFF電流的增加，因此，能防止串擾及輝度傾斜， 故能實現高性能、高信賴度者。 又，申請專利範圍第4項之發明係如申請專利範圍第3 項之薄膜電晶體，其特徵在於：前述通道區域之通道寬度 為2 /Z m以下。 上述式子（2)的關係即使將通道區域之通道寬度設於2 -9· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — I· i I I I I I I I I I I — - (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣474016 V. Description of the invention (6) As mentioned above, it is a new discovery that the width of the empty layer has a proportional relationship with the photoconductive current. By this, it can provide the photoconductive current at-fixed by controlling the width of the empty layer. Thin film transistor with less than allowable value and no image quality degradation such as brightness tilt and crosstalk. The invention of item 2 of the scope of patent application is a thin film transistor such as the scope of patent application, which is characterized in that the sheet impedance of the aforementioned non-polar region is set as the channel width of the aforementioned channel region as w (in m ), The relationship of expression (1) is satisfied. In addition, A is a fixed number set according to the photoconductive current and the light intensity. (R + 30) · W < A… ⑴ The invention of the third scope of the patent application is the thin film transistor of the second scope of the patent application, which is characterized in that the sheet impedance of the aforementioned electrodeless region is set to R (kQ / [U), and when the channel width of the aforementioned channel region is set to w (#m), the relationship of expression (2) is satisfied. (R + 30) · W < 1 * ίο3… (2) As in the above formulas (1) and (2), by the newly controllable factor (sheet impedance in the drain region) and the channel in the channel region The width relationship can define the range of the OFF current (photoconductive current) when the control light is irradiated. The thin film transistor satisfying the relationship of the above formulas (1) and (2) can suppress the increase of the OFF current during light irradiation. Therefore, it can prevent crosstalk and brightness tilt, so it can achieve high performance and high reliability. . In addition, the invention of the fourth scope of the patent application is a thin film transistor such as the third scope of the patent application, characterized in that the channel width of the aforementioned channel region is 2 / Z m or less. The relationship of the above formula (2) is even if the channel width of the channel area is set to 2-9. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). — — — — — I · i IIIIIIIIII — -(Please read the precautions on the back before filling out this page) Printed clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

經濟部智慧財產局員工消費合作社印製 474016 A7 五、發明說明（7) 厂"1以下的情形亦’依據薄片阻抗R及通道寬度而能抑制光 照射時之OFF電流的增加。 又’申請專利範圍第5項或第6項之發明係如申請專利 範圍第3項或第4項之薄膜電晶體，其特徵在於：前述汲極 區域之薄片阻抗係於20kD/□以上，i〇〇kQ/□以下。 如此地限制係由於薄片阻抗設在2〇k Ω / □以下時則 OFF電流急劇地變大，又，將薄片阻抗設於1〇〇1ίΩ/□以 上時則電晶體之ON電流降低而顯示板之動作呈現不安定。 藉著將沒極區域之薄片阻抗設於2〇kQ / □以上，100kQ / □以下則能達到降低OFF電流之目的，同時能提供不會 引起ON電流減少的薄膜電晶體。 又，申請專利範圍第7項之發明係一種薄膜電晶體， 具有通道區域；及，於該通道區域之兩側配置源極區域及 汲極區域之多晶矽半導體層，且於液晶顯示裝置具有開關 元件者’其特徵在於：構成前述液晶顯示裝置之背光的輝 度設於2000(cd/m2)以上時，於前述源極區域與前述通道 區域之間，或是前述汲極區域與前述通道區域之間至少任 何一方，形成不純物濃度係比源極區域及汲極區域低的低 濃度不純物區域，而該低濃度不純度區域的長度在1.0 /z m 〇 如此藉著形成低濃度不純度區域而能將空乏層之寬廣 度設在長度1.0//Π1以下之低濃度不純物質區域範圍内，因 此，能設成不會增加光傳導電流（OFF電流）之薄膜電晶體 〇 又，申請專利範圍第8項之發明係一種薄膜電晶體， -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂 i 丨丨"：丨_--^ (請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8) 具有通道區域；及，形成於配置於通道區域之兩側之源極 區域及汲極區域，於前述源極區域及汲極區域之間，或汲 極區域與通道區域之間之至少任何一方，形成不純物濃度 係比源極區域及汲極區域低的低濃度不純物區域之多晶矽 半導體層，其特徵在於：將前述低濃度不純物質區域之長 度設於ΔίΧ/ζηΟ、將源極一汲極間的電壓設為Vlc(V)、將 前述通道區域之通道寬度設為W(vm)的情形下，滿足式子 (3)的關係。 △ L > (W · Vlc)/36 …（3) 藉由滿足如此關係而，而於薄膜電晶體之OFF時，由 於前述低濃度不純物區域呈載體之枯渴的高阻抗層，因此 能達到降低電流。至於藉著前述式子〇)能決定LDD區域之 長度的方針，且因降低電流而不必要確保必要程度以上的 LDD區域。 又’申請專利範圍第9項之發明係如申請專利範圍第8 項之薄膜電晶體，其特徵在於：前述通道區域之長度設為 L(em)之情形下，滿足式子（4)之關係。 △ L < 1· 5 · (W/L)…（4) 藉著滿足此一關係而於薄膜電晶體ON時，藉著從閘極 來的電場作用而使閘極電極下之低濃度不純區域因形成載 體之電子的蓄積而形成低阻抗區域以致於不發生〇N電流的 減少。爰此，前述薄膜電晶體在十分確保⑽電流之同時， 能抑制OFF電流於最少程度。 又’申請專利範圍第10項之發明係如申請專利範圍第 9項之薄膜電晶體，其特徵在於：前述通道區域之通道 -11- 本紙張尺度適財@國家標準（CNS)A4規格（210 X 297公爱） --------I----裝 - ---— II 訂！ I 線 (請先閲讀背面之注意事項再填寫本頁) 474016Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 A7 V. Description of the Invention (7) The factory and "1" and below conditions can also suppress the increase of the OFF current during light irradiation based on the sheet impedance R and the channel width. The invention of item 5 or item 6 of the patent application scope is a thin film transistor such as item 3 or item 4 of the patent application scope, characterized in that the sheet impedance of the aforementioned drain region is above 20kD / □, i 〇〇kQ / □ or less. This limitation is because the OFF current increases sharply when the sheet impedance is set to less than 20k Ω / □, and the ON current of the transistor decreases when the sheet impedance is set to more than 1001 Ω / □, and the display panel The movement appears unstable. By setting the sheet impedance of the non-electrode area above 20kQ / □ and below 100kQ / □, the purpose of reducing the OFF current can be achieved, and at the same time, a thin-film transistor that does not cause a reduction in the ON current can be provided. In addition, the invention claimed in item 7 of the patent application is a thin film transistor having a channel region; and a polycrystalline silicon semiconductor layer having a source region and a drain region on both sides of the channel region, and a switching element in the liquid crystal display device It is characterized in that when the luminance of the backlight constituting the liquid crystal display device is set at 2000 (cd / m2) or more, between the source region and the channel region, or between the drain region and the channel region At least one of them forms a low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region, and the length of the low-concentration impurity region is 1.0 / zm. Thus, by forming a low-concentration impurity region, it can be empty. The breadth of the layer is set within the range of the low-concentration impurity substance region with a length of 1.0 // Π1 or less. Therefore, it can be set as a thin film transistor that does not increase the photoconductive current (OFF current). The invention is a thin film transistor. -10- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm). i丨 ": 丨 _-- ^ (Please read the notes on the back before filling out this page) 474016 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (8) There is a channel area; and, formed in The source region and the drain region arranged on both sides of the channel region are formed between the source region and the drain region, or at least one of the drain region and the channel region to form an impurity concentration ratio source region. And a polycrystalline silicon semiconductor layer with a low-concentration impurity region having a low drain region, characterized in that the length of the aforementioned low-concentration impurity region is set to Δίχ / ζηΟ, and the voltage between the source and the drain is set to Vlc (V), When the channel width of the aforementioned channel region is W (vm), the relationship of expression (3) is satisfied. △ L > (W · Vlc) / 36… (3) By satisfying this relationship, when the thin film transistor is turned off, the aforementioned low-concentration impurity region is a thirsty high-resistance layer of the carrier, so it can be achieved Reduce the current. As for the policy that the length of the LDD region can be determined by the aforementioned formula 0), it is not necessary to secure an LDD region that is more than necessary because the current is reduced. The invention of item 9 of the scope of patent application is the thin film transistor of item 8 of the scope of patent application, which is characterized in that when the length of the aforementioned channel region is set to L (em), the relationship of formula (4) is satisfied . △ L < 1 · 5 · (W / L) ... (4) When the thin film transistor is turned on by satisfying this relationship, the low concentration impurity under the gate electrode is impure by the action of an electric field from the gate electrode. The region forms a low-impedance region due to the accumulation of electrons forming the carrier, so that no reduction in ON current occurs. Therefore, the aforementioned thin film transistor is capable of suppressing the OFF current to a minimum while ensuring a sufficient current. The invention of item 10 of the scope of patent application is the thin film transistor of item 9 of the scope of patent application, which is characterized in that the channel in the aforementioned channel area is -11- This paper is suitable for financial standards @ National standard (CNS) A4 specification (210 X 297 public love) -------- I ---- install-----II Order! I line (Please read the precautions on the back before filling this page) 474016

五、發明說明（9 ) 度W(//m)在2/zm以下。 經濟部智慧財產局員工消費合作社印製 如此一來，藉由限制前述低濃度不純物區域之長度△ L而能達到降低GFF電流之同時，不會發生⑽電流之減少。 又，申#專利範圍第11項或第丨2項之發明係如申請專 利範圍第9項或第10項之薄膜電晶體，其特徵在於：前述 低濃度不純物區域之薄片阻抗為2〇kQ//□以上，i〇〇 /□以下。 又，申請專利範圍第13項之發明係如申請專利範圍第 Π項之薄膜電晶體，其特徵在於：前述低濃度不純物區域 係僅形成在汲極區域與通道區域之間。 在设置低濃度不純物區域方面，原本係用以緩和作用 於汲極區域之電場，以此觀點而論，於汲極區域與通道區 域之雙方不必要設置低濃度不純物區域。因此，汲極區域 與通道區域之間之至少一方形成低濃度不純物區域的話， 則能弄小薄膜電晶體之面積。 又’申請專利範圍第14項之發明係具備著具有將申請 專利範圍第1項之薄膜電晶體作為開關元件的液晶顯示面 板部；及從裡面側供給光線至前述液晶顯示面板部之背光 部之液晶顯示裝置’其特徵在於：將前述沒極區域之薄片 阻抗設為R(kQ/CJ)，將前述背光部之輝度設為B(cd/m2) ，而將前述通道區域之通道寬度設為W(以m)的情形下，滿 足式子（5)之關係。又，C係依據光傳導電流而設定之定數 〇 (R+30) · B · W < C …（5) 又，申請專利範圍第15項之發明係具備著具有將申請 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） #裝--------訂；---„----線#· (請先閱讀背面之注意事項再填寫本頁) :74016 A75. Description of the invention (9) The degree W (// m) is below 2 / zm. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In this way, by reducing the length ΔL of the aforementioned low-concentration impurity region, the GFF current can be reduced, and the reduction of krypton current will not occur. In addition, the invention claimed in item 11 or item 2 of the patent scope is a thin film transistor such as item 9 or item 10 in the patent scope, characterized in that the sheet impedance of the aforementioned low-concentration impurity region is 20 kQ / / □ or more, i〇〇 / □ or less. In addition, the invention in the thirteenth aspect of the patent application is a thin film transistor such as the one in the thirteenth aspect of the patent application, characterized in that the aforementioned low-concentration impurity region is formed only between the drain region and the channel region. In terms of setting a low-concentration impurity region, it was originally used to relax the electric field acting on the drain region. From this viewpoint, it is unnecessary to set a low-concentration impurity region on both the drain region and the channel region. Therefore, if at least one of the drain region and the channel region forms a low-concentration impurity region, the area of the thin film transistor can be reduced. The invention of item 14 of the scope of patent application includes a liquid crystal display panel section having the thin film transistor of the scope of patent application section 1 as a switching element; and a backlight section that supplies light from the back side to the liquid crystal display panel section. The liquid crystal display device is characterized in that the sheet impedance of the aforementioned electrodeless region is set to R (kQ / CJ), the luminance of the backlight portion is set to B (cd / m2), and the channel width of the channel region is set to In the case of W (in m), the relationship of expression (5) is satisfied. In addition, C is a fixed number (R + 30) · B · W < C (5) set in accordance with the photoconductive current. Moreover, the invention of the 15th patent scope is Paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) #pack -------- order; --- „---- line # (Please read the precautions on the back before (Fill in this page): 74016 A7

經· 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 發明說明（1CV 專利範圍第14項之洶液晶顯示裝置，其特徵在於：將前述 汲極區域之薄片阻抗設為R(kQ/[：])，將前述背光部之輝 度設為B(cd/m2)，而將前述通道區域之通道寬度設為w( #m)的情形下，滿足式子（6)之關係。(R+ 30) · B · W < 1 * 1〇6 …⑹ 又’申請專利範圍第14項所記載之發明係一種EL裝置 ’係於形成在具有薄膜電晶體之基板之像素電極上層具有 發光層’而在該發光層上層形成對向電極之乩裝置，其特 徵在於：前述薄膜電晶體係前述申請專利範圍第1項記載 之薄膜電晶體，將照射該薄膜電晶體之通道區域之光線強 度設為B(cd/m2)的情形下，滿足式子（5)的關係，又，c係 依據光傳導電流而設定之定數。(R+30) · B · W < C …（5) 又’申請專利範圍第17項所記載之發明係申請專利範 圍第16項之EL裝置，係於形成在具有薄膜電晶體之基板之 像素電極上層具有發光層，而在該發光層上層形成對向電 極之EL裝置，其特徵在於：將前述汲極區域之薄片阻抗設 為R(kQ/d)，將前述背光部之輝度設為B(cd/m2)，而將 前述通道區域之通道寬度設為W(//m)的情形下，滿足式子 (6)之關係。(R+30) · B · W < 1* 106 …（6) 又，申請專利範圍第18項之發明係一種薄膜電晶體之 製造方法，包含有··於絕緣性基板上形成多晶矽半導體層 之多晶矽半導體層形成步驟；於前述多晶矽半導體層上形 成閘極絕緣膜之閘極絕緣膜形成步驟；於前述閘極絕緣膜 -13 (請先閱讀背面之注意事項再填寫本頁) 裝 --線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 474016 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（11 ) 將閘極形成圖樣狀之閘極電極形成步驟；將前述閘極電 極之側面予以氧化而形成用以包覆該間極電極之側面之金 f氧化膜的陽極氧化步驟；及，對前述多晶料導體層將 刚述閘極電極作為遮罩而捧入不純物之不純物推入步驟·， 且其特徵在於：抑制前述陽極氧化步驟中所形成之金屬氧 化膜的膜厚而將前述不純物摻入步驟中所形成之低濃度不 純物區域之長度設為以下。 ，又申明專利範圍第19項之發明係一種薄膜電晶體之 製造方法，其特徵在於包含有：於絕緣性基板上形成多晶 矽半導體層之多晶矽半導體層形成步驟；於前述多晶矽半 導體層上形成閘極絕緣膜之閘極絕緣膜形成步驟；於前述 閘極絕緣膜上將閘極形成圖樣狀之閘極電極形成步驟；對 刚述多晶石夕半導體層將前述閘極電極作為遮罩而摻入不純 物之第1不純物摻入步驟；於掺入不純物之半導體區域上 形成遮蔽膜’且藉著使該遮蔽膜呈異方性而形成圖樣狀次 遮蔽膜形成步驟；及，對前述多晶矽半導體層將前述遮蔽 膜作為遮罩而摻入不純物，使遮蔽膜之下部區域與其以段卜 外之區域存在不純物濃度差而於源極電極與通道區域之間 ’或汲極區域與通道區域之間之至少任何一方形成不純物 濃度比源極區域及汲極區域低的低濃度不純物區域，並將 該低濃度不純物區域之長度設在1. 〇 # m以下之第2不純物 摻入步驟。 又，申請專利範圍第20項之記載的發明係如申請專利 範圍第19項之薄膜電晶體之製造方法，其中更包含前述低 濃度不純物區域之長度△ L在1. 0 // m以下則設定為良品之 14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 卜丨！I----#裝--------訂----------線#. (請先閱讀背面之注意事項再填寫本頁) 474016 A7The Ministry of Economic Affairs and Intellectual Property Bureau employee's consumer cooperative prints the invention description (1CV patent scope of the 14th liquid crystal display device, which is characterized by setting the sheet impedance of the aforementioned drain region to R (kQ / [:]), When the luminance of the backlight portion is set to B (cd / m2) and the channel width of the channel area is set to w (#m), the relationship of the expression (6) is satisfied. (R + 30) · B · W < 1 * 1 06 ... ⑹ Also, the invention described in item 14 of the scope of patent application is an EL device 'is a light emitting layer formed on a pixel electrode formed on a substrate having a thin film transistor, and the light emitting layer The device for forming a counter electrode on the upper layer is characterized in that: the thin film transistor described in the aforementioned thin film transistor system described in item 1 of the aforementioned patent application range, and the light intensity irradiating the channel region of the thin film transistor is set to B (cd / m2 ), The relationship of formula (5) is satisfied, and c is a fixed number set according to the photoconductive current. (R + 30) · B · W < C… (5) The invention described in item 17 is the EL device in the scope of patent application No. 16 An EL device having a light emitting layer formed on a pixel electrode formed on a substrate having a thin film transistor and a counter electrode formed on the light emitting layer is characterized in that the sheet impedance of the aforementioned drain region is set to R (kQ / d) When the luminance of the backlight portion is set to B (cd / m2) and the channel width of the channel area is set to W (// m), the relationship of expression (6) is satisfied. (R + 30) · B · W < 1 * 106… (6) In addition, the invention of claim 18 is a method for manufacturing a thin film transistor, which includes a polycrystalline silicon semiconductor in which a polycrystalline silicon semiconductor layer is formed on an insulating substrate. Layer formation steps; gate insulation film formation steps for forming a gate insulation film on the aforementioned polycrystalline silicon semiconductor layer; on the aforementioned gate insulation film-13 (please read the precautions on the back before filling this page) The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 474016 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (11) Steps for forming the gate electrode into a patterned gate electrode; Of the gate electrode Anodizing step of oxidizing the surface to form a gold f oxide film to cover the side surface of the interelectrode; and pushing the impure impurities of the polycrystalline material conductor layer into the impure impurities Step, and is characterized in that the thickness of the metal oxide film formed in the foregoing anodizing step is suppressed and the length of the low-concentration impurity area formed in the foregoing impurity incorporation step is set to the following. The invention of item 19 is a method for manufacturing a thin film transistor, which comprises the steps of: forming a polycrystalline silicon semiconductor layer on a polycrystalline silicon semiconductor layer on an insulating substrate; and forming a gate of a gate insulating film on the polycrystalline silicon semiconductor layer. An insulating film forming step; a gate electrode forming step of forming a gate electrode into a pattern on the foregoing gate insulating film; and for the polycrystalline stone semiconductor layer just described, the foregoing gate electrode is used as a mask and the first impurity is added to the impurity Doping step; forming a masking film on a semiconductor region doped with impurities and forming a pattern by making the masking film anisotropic A step of forming a masking film; and impregnating impurities into said polycrystalline silicon semiconductor layer by using said masking film as a mask, so that there is a difference in impurity concentration between the lower region of the masking film and the region other than the region, and the source electrode and the channel are different. Between regions or at least one of between the drain region and the channel region forms a low-concentration impurity region having a lower impurity concentration than the source region and the drain region, and the length of the low-concentration impurity region is set to 1. 〇 # The second impurity incorporation step below m. In addition, the invention described in the scope of patent application No. 20 is a method for manufacturing a thin film transistor such as the scope of patent application No. 19, which further includes the length of the aforementioned low-concentration impurity region Δ L is 1. 0 // m or less is set 14 is a good product-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) BU 丨! I ---- # 装 -------- Order ---------- 线 #. (Please read the precautions on the back before filling this page) 474016 A7

檢查步驟。 經濟部智慧財產局員工消費合作社印製 【圖式之簡單說明】 第1圖（a)〜（b)係表示構成TFT之通道區域之通道 與光傳導電流（OFF雷、治· τ 日^ a , ^ 电/爪· I〇FF)之關係，及背光輝度與光傳 導電流之關係的曲線圖。 第2圖（a)〜（b)係表示模擬將TFT設為〇ff狀態之情形 下之電場的結果的曲線圖。 第3圖係表示藉著模擬所獲得之薄片阻抗與空乏層寬 度之關係曲線圖。 第4圖係表示測定藉著模擬（W = 4 /i m之情形）而求出之 空乏層寬度與對應該空乏層寬度之薄片阻抗的光傳導電流 之關係之結果的曲線圖。 第5圖係表示動態矩陣之等價電路圖。 第6圖係表示損失像素電極之模擬結果的曲線圖。 第7圖係將本發明之實施樣態1 一 1之薄膜電晶體作為 開關元件而使用之液晶顯示裝置的概略斷面圖。 第8圖係本發明之實施樣態1 一 1之薄膜電晶體的概略 斷面圖。 第9圖係第8圖之概略俯視圓。 第10圖（a)〜（h)係表示本發明之實施樣態1 一 1之薄膜 電晶體之製造方法的概略斷面圖。 第11圖（i)〜（m)同樣表示薄膜電晶體之製造方法的概 略斷面圖。 第12圖同樣表示薄膜電晶體之製造方法的概略斷面圖 -15 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------— — ! — (請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（13 ) 第13圖係表示薄膜電晶體之電壓/電流特性之曲線圖 〇 第14圖係表示0FF電流之基板面内之不均的曲線圖。 第15圖係表示以n型區域之濃度作為參數而模擬薄膜 電晶體之Vg — Ig特性之結果的曲線圖。 第16圖（a)〜表示模擬將TFT設為〇FF狀態之情形 下之電場的結果的曲,缚圖。 第17圖（a)〜（^、丨系令示本發明之實施樣態1一2之薄膜 電晶體之製造方法的赛★斷面圖。 第18圖（h)〜（j)同樣表示薄膜電晶體之製造方法的概 略斷面圖。 第19圖係表示使用本發明之實施樣態ι — 3之薄膜電晶 體之C—M0S反向器之配線圖樣的俯視圖。 第20圖係其等價電路圖。 第21圖從箭頭方向觀看第19圖之χ—χ，斷面圖。 第22圖係C—MOS反向器之ΟΝ/OFF時之η— ch電晶體之 偏壓狀態之動作重點曲線圖。 第23圖（a)〜（d)係表示模擬將薄片阻抗作為步數而將 LDD區域從〇· 5 " 至3 " m為止之情形下之VG — Id特性 之結果的曲線圖。丨 ；(ly), 第24圖（a)〜（^)¾表示於通道區域與LDD區域中，模 擬將TFT設為OFF狀態^KVg = — 10V、Vd = 6V時）之電場的 結果。 ；i ：；(h) 第25圖（a)〜丨(#)孤表示具有實際之LDD區域之TFT之 LDD區域之長度（△L1&0FF電流及LDD區域之長度（△〇與 -16 · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂—:—線 (請先閱讀背面之注意事項再填寫本頁) 474016 A7 B7 五、發明說明（14) ON電流之關係的曲線圖。 第26圖係實施樣態2— 1之薄膜電晶體的簡略化斷面圖 〇 第27圖係第26圖之概略平面圖。 第28圖（a)〜（h)係表示本發明之實施樣態2— 1之薄膜 電晶體之製造方法的概略斷面圖。 第29圖（a)〜（e)係表示本發明之實施樣態2— 1之薄膜 電晶體之製造方法的概略斷面圖。 第30圖係表示本發明之實施樣態2 — 1之薄膜電晶體之 製造方法的流程圖。 第31圖（a)〜（d)係說明形成LDD區域之步驟的概略斷 面步驟圖。 第32圖係光罩與基板之立體圖。 第33圖（a)〜（b)同樣地為光罩與基板之俯視圖。 第34圖（a)〜（b)係LDD區域形成後之薄膜電晶體的概 略斷面圖。 第35圖係表示實施樣態2— 1之薄膜電晶體之電壓/電 流特性的曲線圖。 第36圖係表示實施樣態2_ 1之薄膜電晶體之OFF電流 之基板面内之不均的曲線圖。 第37圖係表示將LDD區域之濃度作為參數之TFT之Vg — Id特性予以模擬之結果的曲線圖。 第38圖（a)〜（b)係用以說明輝度傾斜與串擾之概略圖 〇 實施發明之最佳樣態： • 17 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） -------------UQn--- (請先閱讀背面之注意事項再填寫本頁) ί r 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 474016 A7 B7 五、發明說明（15) (第1發明群） (第1發明群之概念） 首先，於說明第1發明群之概念後，依據圖式來說明 具體的實施樣態。 第1發明群係以抑制對TFT照射光線時之光傳導電流為 目的。 爰此，為達成上述之目的，本發明人等乃探索與前述 光傳導電流具有相關性之參數，其結果乃新發現空乏層寬 度具有與光傳導電流之比例關係。並依據此比例關係而藉 著抑制（弄小）空乏層寬度而達成將光傳導電流設於容許值 以下，而能提供無輝度傾斜及串擾等畫質劣化的薄膜電晶 體。 又，前述「空乏層寬度」乃如將於後述之第2圖（a)所 示，係定義成電場強度提昇之2點之各別的接線間的距離 者。 又，習知上，可得知背光之輝度B及通道區域之通道 寬度W係與光傳導電流具有相關性，而依據此等2個控制參 數而進行TFT之設計。但是，僅前述2個控制參數乃不能充 分對光傳導電流加以抑制，而在TFT設計上亦會產生誤差 〇 因此，本發明人等乃對於前述「空乏層寬度與光傳導 電流之比例關係」更進一步地檢討，而發現到汲極區域之 薄片阻抗亦對光傳導電流具有相關性之特點。藉此，藉著 將所謂薄片阻抗R之新的因素作為評價基準而使控制參數 成為3個，因此比較於習知控制參數為2個之情形，則本發 -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ~ ------------裝--------訂 ----Ϊ----線 (請先閱讀背面之注意事項再填寫本頁) A7 B7 47401^ 五、發明說明（16) 明能提昇薄膜電晶體之設計精密度，且能顯著地控制光傳 導電流。以下首先說明空乏層寬度與光傳導電流之關係， 其後說明背光之輝度B、汲極區域之薄片阻抗R及通道區域 之通道見度W的關係。進而說明用以控制光傳導電流之tft 之具體上之製作方法的原理。 首先，本發明人等在測定構成TFT之通道區域的通道 寬度與光傳導電流之關係’同時並測定;I；及極區域之薄片阻 抗與光傳導電流之關係。且藉著模擬並進行動作解析而求 出空乏層寬度之範圍。 第1圖（a)係表示構成TFT之通道區域之通道寬度與光 傳導電流（OFF電流：I0FF)之關係，及背光輝度與光傳導電 流之關係的曲線圖。又，實線為表示照射6〇〇〇cd/cm2、 虛線為表示照射4000cd/cm2、1點鎖線為表示照射2000 cd /cm2光線時之通道寬度W與光傳導電流101?1?之關係。 從第1圖（a)，可得知光照射時之OFF電流101?1?係與通道 寬度W成比例之關係。又，第1圖（b)係表示背光輝度與光 傳導電流之關係的曲線圖，惟，可確認OFF電流I〇FF係與背 光輝度B成比例者。 第2圖（a)係表示模擬將TFT設為OFF狀態時之電場之結果的 曲線圖。藉著第2圖（a)所示之模擬結果，電場係約僅集中 於通道區/汲極區域之接合部，而LDD區域之薄片阻抗為 20kQ/C](實線）的情形下，可得知空乏層寬度約為0·5# m左右，其空乏層區域主要延伸至通道側。相對於此，可 確認薄片阻抗為lOOkD/CK實線）的情形下’空乏層寬度 約為0.9/zm左右，其擴展至LDD區域。 -19- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝------ --訂！！線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4016Check the steps. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [Simplified illustration of the diagram] Figures 1 (a) ~ (b) show the channels and photoconductive currents (OFF thunder, cure · τ days ^ a) of the channel area constituting the TFT , ^ Electric / claw · 10FF), and the relationship between backlight brightness and light conduction current. Figures 2 (a) to (b) are graphs showing the results of simulating the electric field when the TFT is set to the 0FF state. Fig. 3 is a graph showing the relationship between the sheet impedance obtained by the simulation and the width of the empty layer. Fig. 4 is a graph showing the results of measuring the relationship between the width of the empty layer obtained by simulation (w = 4 / i m) and the photoconductive current corresponding to the sheet impedance corresponding to the width of the empty layer. Fig. 5 is an equivalent circuit diagram showing a dynamic matrix. FIG. 6 is a graph showing a simulation result of a lost pixel electrode. Fig. 7 is a schematic cross-sectional view of a liquid crystal display device using a thin film transistor of Embodiment 1 to 1 of the present invention as a switching element. Fig. 8 is a schematic cross-sectional view of a thin film transistor of embodiment 1 to 1 of the embodiment of the present invention. FIG. 9 is a schematic plan circle of FIG. 8. Figs. 10 (a) to (h) are schematic cross-sectional views showing a method for manufacturing a thin film transistor of the embodiment 1 to 1 of the present invention. 11 (i) to (m) are schematic cross-sectional views showing a method for manufacturing a thin film transistor. Figure 12 also shows the schematic cross-section of the manufacturing method of thin film transistors. Figure 15-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^ -----------! — (Please read the precautions on the back before filling out this page) 474016 Printed by A7, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, 5. A description of the invention (13) Figure 13 is a graph showing the voltage / current characteristics of thin film transistors. Fig. 14 is a graph showing unevenness in the plane of the substrate at 0FF current. Fig. 15 is a graph showing the results of simulating the Vg-Ig characteristics of a thin film transistor using the concentration of the n-type region as a parameter. Fig. 16 (a) ~ Curves and diagrams showing the results of simulating the electric field when the TFT is set to the 0FF state. Figures 17 (a) ~ (^, 丨) are cross-sectional views showing a method for manufacturing a thin film transistor of the embodiment 1 to 2 of the present invention. Figures 18 (h) ~ (j) also show films A schematic sectional view of a method for manufacturing a transistor. FIG. 19 is a plan view showing a wiring pattern of a C-M0S inverter using the thin film transistor of the embodiment ˜3 of the present invention. FIG. 20 is an equivalent view thereof Circuit diagram. Figure 21: χ-χ, cross-sectional view of Figure 19 viewed from the direction of the arrow. Figure 22 is the key curve of the bias state of the η-ch transistor when the C-MOS inverter is ON / OFF. Fig. 23 (a) to (d) are graphs showing the results of VG-Id characteristics in the case where the LDD region is simulated from 0.5 " to 3 " m using sheet impedance as the number of steps. (Ly), Figures 24 (a) ~ (^) ¾ show the results of simulating the electric field when the TFT is set to the OFF state in the channel area and the LDD area (KVg = —10V, Vd = 6V). ; I :; (h) Figure 25 (a) ~ 丨 (#) indicates the length of the LDD region of the TFT with the actual LDD region (△ L1 & 0FF current and the length of the LDD region (△ 〇 and -16 · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- installation -------- order-:-line (please read the Note this page, please fill in this page again) 474016 A7 B7 V. Explanation of the invention (14) The graph of the relationship of the ON current. Figure 26 is a simplified sectional view of the thin film transistor of implementation mode 2-1. Figure 27 Fig. 26 is a schematic plan view. Figs. 28 (a) to (h) are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment 2-1 of the present invention. Fig. 29 (a) to (e) ) Is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to the aspect 2-1 of the present invention. FIG. 30 is a flowchart showing a method for manufacturing a thin film transistor according to the aspect 2-1 of the present invention. Figures 31 (a) to (d) are schematic cross-sectional step diagrams illustrating the steps for forming an LDD region. Figure 32 is a perspective view of a photomask and a substrate. Figures 33 (a) to (b) are also light. Top view of the cover and substrate. Figures 34 (a) ~ (b) are schematic cross-sectional views of thin film transistors after the LDD region is formed. Figure 35 shows the voltage / current of the thin film transistor in implementation form 2-1. The graph of the characteristic. Fig. 36 is a graph showing the unevenness in the OFF plane of the substrate of the thin film transistor in implementation mode 2_1. Fig. 37 is the Vg of the TFT using the concentration of the LDD region as a parameter. A graph of the results of simulation of Id characteristics. Figures 38 (a) ~ (b) are schematic diagrams for explaining the tilt and crosstalk of brightness. 0 The best form of implementing the invention: • 17-This paper scale applies Chinese national standards. (CNS) A4 specification (210 x 297 mm) ------------- UQn --- (Please read the precautions on the back before filling out this page) ί r Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives Printed by Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 A7 B7 V. Description of Invention (15) (First Invention Group) (Concept of First Invention Group) First, after explaining the concept of the first invention group, The specific implementation mode will be described based on the drawings. The first invention group is to suppress the TFT photo The purpose of the photoconductive current at the time of light is to achieve this. In order to achieve the above-mentioned purpose, the inventors have explored parameters that are related to the aforementioned photoconductive current. As a result, the width of the empty layer has a new ratio to the photoconductive current. According to this proportional relationship, by suppressing (decreasing) the width of the empty layer, the photoconductive current can be set below the allowable value, and a thin film transistor with no degradation in brightness such as luminance tilt and crosstalk can be provided. In addition, the aforementioned "empty layer width" is defined as the distance between the individual wiring points at which the electric field strength is increased by 2 points as shown in Fig. 2 (a) which will be described later. In addition, conventionally, it can be known that the luminance B of the backlight and the channel width W of the channel region are related to the photoconductive current, and the TFT is designed based on these two control parameters. However, only the aforementioned two control parameters cannot sufficiently suppress the photoconductive current, and an error may also occur in the design of the TFT. Therefore, the present inventors etc. After further review, it was found that the sheet impedance in the drain region is also relevant to the photoconductive current. Therefore, by using the new factor of the so-called sheet impedance R as an evaluation criterion, the control parameters are reduced to three. Therefore, compared with the case where the conventional control parameters are two, this paper-18- Standard (CNS) A4 specification (210 X 297 mm) ~ ------------ install -------- order ---- Ϊ ---- line (please read first Note on the back, please fill out this page again) A7 B7 47401 ^ V. Description of the invention (16) It can improve the design precision of thin film transistors, and can significantly control the photoconductive current. The relationship between the width of the empty layer and the photoconductive current is explained first, and then the relationship between the luminance B of the backlight, the sheet resistance R of the drain region, and the channel visibility W of the channel region are explained. Furthermore, the principle of the specific manufacturing method of tft for controlling the photoconductive current will be explained. First, the inventors measured the relationship between the channel width of the channel region constituting the TFT and the photoconductive current at the same time and measured I; and the relationship between the sheet impedance of the polar region and the photoconductive current. The range of the width of the empty layer is obtained by simulating and analyzing the operation. Fig. 1 (a) is a graph showing the relationship between the channel width of the channel region constituting the TFT and the photoconductive current (OFF current: I0FF), and the relationship between the backlight luminance and the photoconductive current. In addition, the solid line indicates the irradiation of 6000 cd / cm2, the broken line indicates the irradiation of 4000 cd / cm2, and the 1-point lock line indicates the relationship between the channel width W and the photoconductive current 101? 1? When irradiated with 2000 cd / cm2 light. From Fig. 1 (a), it can be seen that the OFF current 101? 1? During light irradiation is proportional to the width W of the channel. Fig. 1 (b) is a graph showing the relationship between the backlight luminance and the photoconductive current. However, it can be confirmed that the OFF current IFF is proportional to the backlight luminance B. Fig. 2 (a) is a graph showing a result of simulating an electric field when the TFT is turned off. Based on the simulation results shown in Figure 2 (a), the electric field is only concentrated at the junction of the channel region / drain region, and the sheet impedance of the LDD region is 20kQ / C] (solid line). It is known that the width of the empty layer is about 0.5 m, and the area of the empty layer mainly extends to the channel side. On the other hand, in the case where the sheet impedance is 100 kD / CK solid line), the width of the empty layer is about 0.9 / zm, which extends to the LDD region. -19- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation ------ --Order! !! (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4016

五、發明說明（17) 藉此，新發現依據薄片阻抗之變化而使空乏層寬度亦 會變化之情形。因此，本發明人等乃著手調查薄片阻抗與 空乏層寬度之關係。其結果則如第3圖所示，第3圖係表示 藉著模擬所獲得之薄片阻抗與空乏層寬度之關係。而可確 認空乏層寬度Wd係與薄片阻抗R成比例。可得知此乃與1)/ η接合之情形下的空乏層的擴展相同，乃因空乏層延伸至 載體濃度低的區域者。而第3圖之薄片阻抗與空乏層寬度 之關係以下述式子（7)表示。 Wd=8*l〇 —3.r+〇24 …⑺ 第4圖係表示測定藉著模擬（界=4//11)之情形）而求出之 空乏層寬度與對應該空乏層寬度之薄片阻抗的光傳導電流 之關係之結果的曲線圖。 各別以對數來繪出空乏層寬度與光傳導電流時，約可 獲得傾斜為一直線。此乃表示光傳導電流藉著空乏層區域 而產生之情形者。而空乏層寬度恥與光傳導電流之關係能 以下述式子（8)來表示。 ------------f _ — 1 (請先閱讀背面之注意事項再填寫本頁) -«J· IPh〇t〇= 5氺 10 — 15 · Wd (8) 線· 經濟部智慧財產局員工消費合作社印製 又，上述式子（8)之中，lph〇t。係通道區域為4私m之光 強度相當於l(cd/m2)之值。 藉著如上述式子（8)，可看出空乏層寬度⑽具有與光 傳導電流Iphc)t。比例關係，藉此，以控制（弄小）空乏層寬度 而能將光傳導電流設在容許值以下，而能提供無輝度傾斜 及串擾等畫質劣化，且能實施樣態現具高性能、高信賴度 之薄膜電晶體。又，前述之「容許值」係例如將於後述， 而或為ΙΟρΑ以下的值。 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4?4〇ΐβ (9) 0 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（18 ) 又，從前述之第1圖（a)來看，I〇ff例與通道寬度w及光 強度B成比例，因此IQfi&iphQt〇滿足下述式子（9)的關係。 [off= Iphoto · (W/4) · 因此，從上述式子（9)與式子（8)除去Iph〇t。時，即得下 述式子（10)。V. Description of the invention (17) Based on this, it is newly discovered that the width of the empty layer also changes according to the change of the sheet resistance. Therefore, the present inventors set out to investigate the relationship between the sheet impedance and the width of the empty layer. The results are shown in Figure 3. Figure 3 shows the relationship between the sheet impedance obtained by simulation and the width of the empty layer. It can be confirmed that the width Wd of the empty layer is proportional to the sheet resistance R. It can be seen that this is the same as the expansion of the empty layer in the case of 1) / η junction, because the empty layer extends to a region with a low carrier concentration. The relationship between the sheet impedance in FIG. 3 and the width of the empty layer is expressed by the following formula (7). Wd = 8 * l0—3.r + 〇24… ⑺ Figure 4 shows the measurement of the width of the empty layer and the impedance of the sheet corresponding to the width of the empty layer, which are obtained by simulation (boundary = 4 // 11). A graph of the results of the relationship of the photoconductive current. When plotting the width of the empty layer and the photoconductive current in logarithm, respectively, the slope can be obtained as a straight line. This is the case where the photoconductive current is generated through the empty layer area. The relationship between the width of the empty layer and the photoconductive current can be expressed by the following formula (8). ------------ f _ — 1 (Please read the notes on the back before filling this page)-«J · IPh〇t〇 = 5 氺 10 — 15 · Wd (8) line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the above formula (8), lph〇t. The light intensity of the channel area is 4 m, which is equivalent to 1 (cd / m2). According to the above formula (8), it can be seen that the width of the empty layer ⑽ has a value corresponding to the photoconductive current Iphc) t. The proportional relationship can be used to control (reduce) the width of the empty layer and set the photoconductive current below the allowable value. It can provide image quality degradation such as no brightness tilt and crosstalk. High reliability thin film transistor. The "permissible value" mentioned above is, for example, a value which will be described later, or may be 10 ρΑ or less. -20- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 4 ~ 4〇ΐβ (9) 0 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (18) In addition, from the above-mentioned first graph (a), since the Iff example is proportional to the channel width w and the light intensity B, IQfi & iphQt0 satisfies the relationship of the following formula (9). [off = Iphoto · (W / 4) · Therefore, IphOt is removed from the above equations (9) and (8). Then, the following formula (10) is obtained.

Ioff(4(W · B)) = 5* 10-15 · Wd …（10) 而從上述式子（7)、（10)除去空乏層寬度恥時，即得 下述式子（11)。於此，從第1圖（a)I〇ff則與通道區域成比 例。 I〇ff · 1〇~17/(Β · W)-30 - (11) 然而，一般而言為了維持高品位之畫質，I〇ff有必要 為10PA以下之值。其理由將說明如下。於第5圖中表示動 態矩陣之等價電路。 TFT之OFF阻抗RQff變小時，直到其次之寫入為止，不 能保持電荷而呈電壓損失的狀態。時間T後之像素電壓v則 以式子（12)記述。 V= V0{1 - exp(T/(Roff * Ctot)))…（12) 在此，Ctot = Cs + Clc 又，將丁叮之(^電流〇^。"=^(1/1。"）設為參數時，則 時間與電壓損失之模擬結果以第6圖表示。從第6圖來看， 以16msec(l/60Hz)之保持時間，為了將電壓損失抑制在 0.02V以下，可確認在背光照射狀態下，有必要將〇FF電流 設於ΙΟρΑ以下。 爰此，將前述式子（11)之IQff設在ΙΟρΑ以下時，可得 到以下的式子。 -21- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） -------------裝--------訂·--------線 (請先閱讀背面之注意事項再填寫本頁) 474016Ioff (4 (W · B)) = 5 * 10-15 · Wd (10) When the empty layer width shame is removed from the above formulas (7) and (10), the following formula (11) is obtained. Here, from Figure 1 (a) Iff is proportional to the channel area. I00ff · 10 ～ 17 / (Β · W) -30-(11) However, in order to maintain high-quality image quality, I00ff must be a value of 10 PA or less. The reason will be explained as follows. Fig. 5 shows the equivalent circuit of the dynamic matrix. The OFF resistance RQff of the TFT becomes small until it is written next, and the charge cannot be maintained and voltage loss occurs. The pixel voltage v after time T is described by equation (12). V = V0 {1-exp (T / (Roff * Ctot))) ... (12) Here, Ctot = Cs + Clc, and Ding Dingzhi (^ Current〇 ^. &Quot; = ^ (1/1. ") When the parameter is set, the simulation result of time and voltage loss is shown in Fig. 6. From the view of Fig. 6, with a holding time of 16msec (l / 60Hz), in order to suppress the voltage loss below 0.02V, It can be confirmed that in the backlight irradiation state, it is necessary to set the 0FF current to be less than 10ρΑ. Therefore, when IQff of the aforementioned formula (11) is set to less than 10ρΑ, the following formula can be obtained. -21- This paper scale Applicable to China National Standard (CNS) A4 specification (210 χ 297 mm) ------------- Installation -------- Order · -------- Line ( (Please read the notes on the back before filling out this page) 474016

五、發明說明（19) (R+30) B · w &lt; 10 · 10-12 · 1〇i7= j * 1〇6 …（12) 又，依據使用薄膜電晶體之條件，而使控制OFF電流 之值改變，故能以下述式子（5)來表示。 (R+30) · B· W &lt; C …（12) 又，C係依據光傳導電流而決定之定數。 如此一來’要滿足上述式子（6)之薄膜電晶體乃能抑 制光傳導電流者’因此’能防止串擾及輝度傾斜而能實現 畫質優良、高性能、高信賴度。 又’上述式子（6)係包含液晶顯示面板之背光的式子， 惟’一般之薄膜電晶體係經常具有背光之透過型則不在此 限。麦此’將背光輝度B暫定為最高5〇〇〇cd/m2時，前述 式子（6)就成為： (R+30) · W &lt; 2氺 1〇2 ··· (2，） 而要滿足前述式子（2，）的薄膜電晶體乃與背光之輝度 B無關，亦即，能設為不論是透過、反射型之薄膜電晶鱧。 又’上述式子（2，）以滿足下述式子（2)的話就能作為 性能更佳的薄膜電晶體。 (R+ 30) · W &lt; 1 * ίο3 ··· (2) 又’前述式子（11)能以下述式子（11，）來表示。即： (R+30) · W &lt; (Ioff · ι〇π)/β …⑴，） 將上述（11，）之右邊以藉由I()ff&amp;B所定之定數Α來置換 時，則能以下述式子（1)來表示。 (R+30) · W〈 A …（1) (A係依據光傳導電流與光強度而決定之定數） 又，在前述TFT之構成之中，藉由形成LDD區域而使空 -22- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------#裝--------訂-----„----線-φ- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 五 經濟部智慧財產局員工消費合作社印製 474016 、發明說明（） 乏層不擴展於該LDD區域以上，而如前述一般，能抑制與 空乏層寬度成比例關係之光傳導電流。第16圖係表示於通 道區域與LDD區域之中，模擬將TFT設為OFF狀態之情形下 (Vg= — 10V，Vd=6V時）之電場的結果。 由前述模擬結果，可確認電場之相關區域係依存於薄 片阻抗，而在LDD區域之薄片阻抗為2〇kfi/□時為〇·4# m，當薄片阻抗為ΙΟΟΙςΩ/□時為10^^。 又，前述通道寬度係在進行，惟，將通道區域之 通道寬度W予以微細化而設在2“ m以下時，特別是前述關 係式之式子（1)、式子（2)在製作薄膜電晶體方面為有效之 指南。 又，在以下之實施樣態中，將具體地說明依據前述模 擬來說明製作TFT之情形。 (實施樣態1 一 1) 第7圖係將本發明之實施樣態丨之薄膜電晶體作為像素 開關元件來使用之液晶顯示裝置的概略斷面圖，第8圖係 本發明之實施樣態1之薄膜電晶體之概略斷面圖，第9圖係 第8圖之概略俯視圖。 如第7圖所示，液晶顯示裝置5〇係具有液晶顯示面板 部51，及配置於該液晶顯示面板部51之裡側的背光部犯等 之透過型液晶顯示裝置。前述液晶顯示面板部51係由偏光 板53 · 53、玻璃基板2 · 54b、配置成陣列狀之薄祺電晶鱧 1、像素電極55、像素電極55、配向膜56、液晶層57、丘 通電極58等所構成。 在前述玻璃基板2上形成薄犋電晶體丨（以下稱打^^及 -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（21 ) 像素電極55，在前述基板54b形成共通電極58。又，於前 述基板2 · 54b各別形成由驟醯亞胺樹脂基板脂等所構成之 配向膜56 · 56，而將前述配向膜56 · 56預先摩擦處理成配 向方向為相互正交之方向，至於基板2 · 54b就未以圖式來 顯示，係透過間隔構件而被對向配置。 又，在前述基板2 · 54b之間失持著液晶層57，而前述 液晶層57内的液晶係呈9〇度扭曲配向。而且，在前述基板 2 · 54b之外側面，偏光板53 · 53係配置成所限制之光線的 振動方向相互平行狀態。 又’於前述液晶顯示面板部51之裡面（下方）配置背光 部52。前述背光部52係由冷陰極管等的發光元件，與用以 使光線均一化的光分散板等所構成。 其次以第8、9圖來說明前述薄膜電晶趙。 薄膜電晶體1係由在玻璃基板2上依順序地積層膜厚為 500埃之多晶石夕層3、膜厚為1〇〇〇埃之Si 〇2(二氧化石夕）所構 成的閘極絕緣層4、鋁所構成之閘極電極5a、及Si 02所構 成之層間絕緣膜6而構成者。 又，前述多晶矽層3係由位於閘極電極5a之正下方的 通道區域3c、濃度高的源極區域3a(n +層）、及不純物濃 度高的沒極區域（n +層）3b所構成。又，在本實施例中，LDD 區域（η —層）3d · 3e之長度設定為〇.4ym。又，前述通道 區域3c之通道寬度W係設定為5 // m。 在此，將前述汲極區域之薄片阻抗設為R(kQ/[I])， 將使用此動態矩陣TFT之液晶顯示裝置50之背光部52的輝 度設為B(cd/m2)，將前述通道區域3c之通道寬度設為W(/z -24· 張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--------訂 ί—^—線 ί請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 _______B7___ 五、發明說明（22 ) m)的情形下，則設計成滿足以下式子（6)。 (R+30)-B-W= Ioff &lt; 1*106 ··· (6) 又，在TFT 1更設置例如由紹所構成之源極電極7及沒 極電極8，源極電極7乃藉由形成於閘極絕緣層4及層間絕 緣層6之連接孔9 a而連接於源極區域3 a，又，沒極電極8係 藉由形成於閘極絕緣層4及層間絕緣層6之連接孔9b而連接 於汲極區域3b。 其次說明薄膜電晶體之製造方法。第1 〇圖係表示本發 明之實施樣態1 — 1之薄膜電晶體之製造方法的概略斷面 圖，第11圖同樣是表示薄膜電晶體之製造方法的概略斷面 圖，第12圖同樣是表示薄膜電晶體之製造方法的流程圖。 (1) 首先以電漿CVD法在玻璃基板2上堆積膜厚為500埃 之a—Si層15，接著以400°C來進行脫氫處理（第10圖（a))。 此脫氫處理之目的乃在於防止進行結晶化之際，因氫之脫 離所造成Si膜的消融（ablation)。又，形成a—Si之步驟 係除了使用電漿CVD之外，亦能使用減壓CVD及濺鍍法等處 理。又，亦能使用電漿CVD以外的方法來直接堆積聚矽膜。 此情形下，則不須要將於後述之使用雷射來回火的步驟。 (2) 其次，藉著使用波長為308nm之準分子雷射的雷射 回火處理而進行a—Si層15之熔化再結晶化（p — Si化）而形 成多晶矽層16(第10圖（b))。 (3) 其次，將多晶石夕層16島化成一定形狀而形成多晶 矽層3(第10圖（c))。 (4) 接著於玻璃基板2上形成閘極絕緣層4用以覆蓋多 晶矽層3，而形成厚度為1000埃之Si02(二氧化矽）層（第1〇 -25 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝-------I訂·！ I! !線 (請先閱讀背面之注意事項再填寫本頁) 474016 A7 B7 五、發明說明（23) 圖⑷）。 (5) 接著作成閘極電極5a，而製膜成由鋁所構成之金 屬層17(第10圖（e))。 (請先閱讀背面之注意事項再填寫本頁) (6) 接著將金屬層17予以圖樣化成一定形狀而形成閘 極電極5a(第10圖（〇)。 (7) 接著將閘極電極5a作為遮罩來使用而進行不純物 的摻入（第10圖（g))。具體而言，即以離子摻入法來摻入 作為不純物之磷離子。藉此，位於閘極電極5a之正下方的 通道區域3c乃為未摻入不純物的區域。至於除去多晶矽層 3之通道區域3c的區域則成為摻入不純物之層。又，此情 形下之摻入加速電壓設為80kV而電束電流密度設為1以A/ cm2，而以高加速來作成η型區域者。 (8) 接著覆蓋閘極電極5a而製膜成光阻膜18(第10圖 ⑻）。 (9) 接著以異方性蝕刻使光阻膜8形成圖樣化而形成阻 抗膜5b(第11圖（〇)。此時能以異方性蝕刻來形成正確的 阻抗膜5b的圖樣。 (10) 接著如第11圖（j)所示，將阻抗膜5b作為遮罩使 經濟部智慧財產局員工消費合作社印製 用並進行第二次的摻入不純物。具體而言，係以離子摻入 法來摻入作為不純物之磷離子。此時之摻入加速電壓設為 12kV而電束電流密度設為0. A/cm2，以低加速來作成高 濃度之η型區域。 (11) 其次製膜成層間絕緣層（SiOx)6(第11圖（k))。 (12) 其次於層間絕緣層6及閘極絕緣層4進行連接孔 9a、9b之開口（第 11 圖（L)) -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 474016 A7 B7 五、發明說明（24) (13)以濺鍍法將A1等金屬層充填於連接孔9a、9b，將 金屬層之上部圖樣化成一定形狀而形成源極電極7及汲極 電極8(第ll(m)圖）。以製作TFn。 前述之例子雖已說明了 η通道TFT，惟，對於p通道TFT 亦能以同樣的製造處理來製造。 從以前述製造方法所製造之薄膜電晶體的裡面照射 5000cd/m2之光線時，OFF電流約呈5pA。如前述一般，由 於在背光照射狀態下有必要將OFF電流設於ΙΟρΑ以下，因 此，本實施樣態之薄膜電晶體能確保良好的顯示性能。 又，以第13圖來表示薄膜電晶體之電壓/電流特性， 且以第14圖來表示OFF電流之基板面内之不均。如第13圖 所示，本實施樣態之TFT1CL3之曲線圖）乃能確保穩定之大 的ON電流及小的OFF電流。又，從第14圖可得知如此製作 的TFT1乃能使基板面内上之不均變小。 於第15圖中係將η型區域之濃度作為參數，而模擬薄 膜電晶體之Vg— Id特性的結果。LDD區域之薄片阻抗在20k Ω/□以下而OFF電流乃急劇地變大。爰此，LDD區域之薄 片阻抗有必要至少設於100kQ/□以上。另一方面，LDD 區域之薄片阻抗設在1000kQ/□以上時，電晶體之ON電 流會降低而使顯示面板之動作變得不穩定。因此，LDD區 域之薄片阻抗的範圍最好是設於20kQ/□以上ΙΟΟΙίΩ/ □以下。V. Description of the invention (19) (R + 30) B · w &lt; 10 · 10-12 · 1〇i7 = j * 1〇6… (12) The control is turned off according to the conditions of using thin film transistors Since the value of the current changes, it can be expressed by the following formula (5). (R + 30) · B · W &lt; C… (12) C is a fixed number determined based on the photoconductive current. In this way, 'the thin film transistor that satisfies the above formula (6) is capable of suppressing the photoconductive current'. Therefore, it is possible to prevent crosstalk and luminance tilt and realize excellent image quality, high performance, and high reliability. Also, the above formula (6) is a formula including a backlight of a liquid crystal display panel, but the general thin film transistor system often has a backlight transmissive type. In the case of Mai this, when the backlight luminance B is tentatively set to a maximum of 5000 cd / m2, the aforementioned formula (6) becomes: (R + 30) · W &lt; 2 氺 10 2 ··· (2,) and The thin film transistor that satisfies the aforementioned formula (2,) has nothing to do with the brightness B of the backlight, that is, it can be set as a transmissive or reflective thin film transistor. If the above formula (2) satisfies the following formula (2), a thin film transistor with better performance can be obtained. (R + 30) · W &lt; 1 * ίο 3 ··· (2) Also, the aforementioned formula (11) can be expressed by the following formula (11,). That is: (R + 30) · W &lt; (Ioff · ι〇π) / β… ,,) When the right side of the above (11,) is replaced by a fixed number A determined by I () ff &amp; B, It can be expressed by the following formula (1). (R + 30) · W <A… (1) (A is a fixed number determined by the photoconductive current and light intensity) In the structure of the aforementioned TFT, the LDD region is formed to make the space -22- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- # 装 -------- Order ----- „--- -线 -φ- (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Five Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 Extending above the LDD region, as described above, it is possible to suppress the photoconductive current proportional to the width of the empty layer. Figure 16 shows the channel region and the LDD region, and the simulation of the case where the TFT is turned OFF (Vg = — 10V, Vd = 6V). From the simulation results, it can be confirmed that the relevant area of the electric field depends on the sheet impedance, and when the sheet impedance in the LDD region is 20kfi / □, it is 0 · 4 # m, 10 ^^ when the sheet impedance is ΙΟΟΙς Ω / □. Also, the aforementioned channel width is underway, but the channel area When the width W be provided in miniaturization 2 "m or less, in particular, the relational expression of Equation (1), equation (2) in terms of making a thin film transistor is valid directory. In the following embodiment, a case where a TFT is manufactured based on the aforementioned simulation will be specifically explained. (Embodiment mode 1 to 1) FIG. 7 is a schematic cross-sectional view of a liquid crystal display device using a thin film transistor of the embodiment of the present invention as a pixel switching element, and FIG. 8 is an embodiment of the present invention. The schematic cross-sectional view of the thin film transistor of FIG. 1 is a schematic plan view of FIG. 8. As shown in Fig. 7, the liquid crystal display device 50 is a transmissive liquid crystal display device including a liquid crystal display panel portion 51 and a backlight portion disposed on the back side of the liquid crystal display panel portion 51. The aforementioned liquid crystal display panel portion 51 is composed of a polarizing plate 53 · 53, a glass substrate 2 · 54b, a thin film transistor arranged in an array, a pixel electrode 55, a pixel electrode 55, an alignment film 56, a liquid crystal layer 57, and a hill pass. The electrode 58 is configured. Form thin thin transistors on the aforementioned glass substrate 2 (hereinafter referred to as ^^ and -23- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) --------- ---- Equipment -------- Order --------- line (Please read the precautions on the back before filling this page) 474016 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Explanation of the invention (21) The pixel electrode 55 is formed with a common electrode 58 on the substrate 54b. Further, alignment films 56 and 56 made of an imide resin substrate grease and the like are formed on the substrates 2 and 54b, respectively. The alignment films 56 and 56 are rubbed in advance so that the alignment directions are orthogonal to each other. As for the substrates 2 and 54b, which are not shown in the drawings, they are arranged to face each other through the spacer member. The substrates 2 and 54b are disposed opposite to each other. The liquid crystal layer 57 is misaligned, and the liquid crystal system in the liquid crystal layer 57 is twisted at 90 degrees. Moreover, on the outer side of the substrate 2 · 54b, the polarizing plates 53 · 53 are arranged in a restricted light. The vibration directions are parallel to each other. A backlight is disposed inside (below) the liquid crystal display panel portion 51. 52. The backlight 52 is composed of a light emitting element such as a cold cathode tube and a light dispersing plate for uniformizing light. The thin film transistor is described next with reference to Figs. 8 and 9. The thin film transistor 1 is a gate insulating layer composed of a polycrystalline stone layer with a film thickness of 500 angstroms and a silicon film with a film thickness of 1000 angstroms. 4. A gate electrode 5a made of aluminum and an interlayer insulating film 6 made of Si 02. The polycrystalline silicon layer 3 is a high-concentration source formed by a channel region 3c directly below the gate electrode 5a. The electrode region 3a (n + layer) and the non-electrode region (n + layer) 3b having a high impurity concentration are configured. In this embodiment, the length of the LDD region (n-layer) 3d · 3e is set to 0. 4ym. In addition, the channel width W of the aforementioned channel region 3c is set to 5 // m. Here, the sheet impedance of the aforementioned drain region is set to R (kQ / [I]), and the liquid crystal using this dynamic matrix TFT will be used. The luminance of the backlight portion 52 of the display device 50 is set to B (cd / m2), and the channel width of the aforementioned channel area 3c is set to W (/ z -24 · Zhang ruler Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------ install -------- order ί — ^ — line Please read the note on the back first Please fill in this page again for matters) 474016 Printed by A7 _______B7___ of Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs 5. In the case of invention description (22) m), it is designed to satisfy the following formula (6). (R + 30) -BW = Ioff &lt; 1 * 106 ··· (6) Further, the TFT 1 is further provided with a source electrode 7 and a non-electrode 8 composed of, for example, a source electrode 7 by The connection hole 9 a formed in the gate insulating layer 4 and the interlayer insulating layer 6 is connected to the source region 3 a. The non-electrode 8 is a connection hole formed in the gate insulating layer 4 and the interlayer insulating layer 6. 9b is connected to the drain region 3b. Next, a method for manufacturing a thin film transistor will be described. FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to the embodiment 1-1 of the present invention. FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor, and FIG. 12 is the same. It is a flowchart showing a method of manufacturing a thin film transistor. (1) First, an a-Si layer 15 having a thickness of 500 angstroms was deposited on a glass substrate 2 by a plasma CVD method, and then a dehydrogenation treatment was performed at 400 ° C (Fig. 10 (a)). The purpose of this dehydrogenation treatment is to prevent the ablation of the Si film due to the desorption of hydrogen during crystallization. The step of forming a-Si can be performed by using a reduced pressure CVD or a sputtering method in addition to plasma CVD. In addition, a method other than plasma CVD can be used to directly deposit a polysilicon film. In this case, it is not necessary to use the laser to fire back and forth as described later. (2) Next, the polycrystalline silicon layer 16 is formed by melting and recrystallization (p-Si) of the a-Si layer 15 by laser tempering with an excimer laser having a wavelength of 308 nm (Fig. 10 (Fig. 10) b)). (3) Next, the polycrystalline silicon layer 16 is islanded into a certain shape to form a polycrystalline silicon layer 3 (Fig. 10 (c)). (4) Next, a gate insulating layer 4 is formed on the glass substrate 2 to cover the polycrystalline silicon layer 3, and a SiO2 (silicon dioxide) layer having a thickness of 1000 angstroms is formed (No. 10-25-This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) ------------- install ------- I order ·! I!! Line (Please read the precautions on the back before (Fill this page) 474016 A7 B7 V. Description of the invention (23) Figure ⑷). (5) The gate electrode 5a is formed next, and a metal layer 17 made of aluminum is formed into a film (Fig. 10 (e)). (Please read the precautions on the back before filling in this page) (6) Next, pattern the metal layer 17 into a certain shape to form the gate electrode 5a (Figure 10 (0). (7) Next, use the gate electrode 5a as The mask is used for doping of impurities (Fig. 10 (g)). Specifically, the impurities are doped with phosphorus ions by the ion doping method. As a result, the electrode directly below the gate electrode 5a is doped. The channel region 3c is a region where impurities are not doped. As for the region where the channel region 3c of the polycrystalline silicon layer 3 is removed, it becomes a layer doped with impurities. Further, in this case, the doping acceleration voltage is set to 80 kV and the beam current density is set to The η-type region is formed with A / cm2 and high acceleration for 1. (8) Next, the gate electrode 5a is covered to form a photoresist film 18 (Fig. 10). (9) Next, anisotropic Etching patterned the photoresist film 8 to form a resistive film 5b (FIG. 11 (0). At this time, an accurate pattern of the resistive film 5b can be formed by anisotropic etching. (10) Next, as shown in FIG. 11 (j As shown in the figure, using the impedance film 5b as a mask allows the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to print and use it concurrently. A / cm2 ， The second impure impurity is added. Specifically, the impurity ion is doped with phosphorus ions as an impurity. At this time, the acceleration voltage is set to 12kV and the beam current density is set to 0. A / cm2 ， A high-concentration n-type region is formed with low acceleration. (11) Next, an interlayer insulating layer (SiOx) 6 is formed (Fig. 11 (k)). (12) Next is an interlayer insulating layer 6 and a gate insulating layer 4 Open the connection holes 9a and 9b (Figure 11 (L)) -26- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 474016 A7 B7 V. Description of the invention (24) (13 ) Fill the connection holes 9a, 9b with a metal layer such as A1 by sputtering, and pattern the upper part of the metal layer into a certain shape to form the source electrode 7 and the drain electrode 8 (Figure 11 (m)). To make TFn Although the previous example has described the n-channel TFT, it can also be manufactured with the same manufacturing process for the p-channel TFT. When 5000 cd / m2 of light is irradiated from the inside of the thin-film transistor manufactured by the aforementioned manufacturing method, it turns off. The current is about 5 pA. As mentioned above, it is necessary to set the OFF current to 10 in the backlight state. Below A, therefore, the thin film transistor of this embodiment can ensure good display performance. The voltage / current characteristics of the thin film transistor are shown in FIG. 13, and the in-plane of the substrate with OFF current is shown in FIG. 14. The unevenness. As shown in FIG. 13, the TFT1CL3 curve of this embodiment) can ensure a stable ON current and a small OFF current. In addition, it can be seen from FIG. 14 that the TFT1 thus produced is It can make the in-plane unevenness of the substrate smaller. In Fig. 15, the concentration of the n-type region is used as a parameter, and the result of simulating the Vg-Id characteristic of the thin film transistor is simulated. The sheet impedance in the LDD region is less than 20k Ω / □ and the OFF current increases sharply. Therefore, it is necessary to set the sheet impedance of the LDD region to at least 100kQ / □ or higher. On the other hand, when the sheet impedance of the LDD region is set to be more than 1000kQ / □, the ON current of the transistor will decrease and the operation of the display panel will become unstable. Therefore, the range of the sheet impedance in the LDD region is preferably set at 20kQ / □ or more and 100 ΙΩ / □ or less.

一般而言，背光輝度為最大為5000cd/m2，此情形下， 為求出用以將光傳導電流抑制在ΙΟρΑ以下之空乏層寬度Wd 時，則如以下所述。即，於前述（10)式子中帶入W=4、B -27- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝—— (請先閱讀背面之注意事項再填寫本頁) 訂： --線- 經濟部智慧財產局員工消費合作社印製 474016 經濟部智慧財產局員工消費合作社印製 A7 B7___ 五、發明說明（25 ) = 5000、Ioff =10*10—12而能求出空乏層寬度，而呈而= 0_ 4 // m 〇 · 前述空乏層寬度不達LDD區域之長度以上，因此，將LDD 區域之長度AL設於0·4απι以下而使實效上的空乏層區域 呈0· 4//m以下，而能作成抑制（ι〇ρΑ以下）光傳導電流之構 成。又，LDD區域比0· 1 # m小的話，則無電場緩和效果， 如第2圖（b)所示，由於OFF電流增大，故前述LDD區域最好 是比0· 1 // m大。 又，上述式子（10)之中，背光輝度B例如為2000cd/m2 以上時，則空乏層寬度Wd為1 //m。 爰此，由於空乏層寬度不達LDD區域之長度以上，因 此，藉著將LDD區域之長度AL設於1.0/zm以下而使實效上 的空乏層區域呈l.〇#m以下，而能作成抑制光傳導電流。 而且最好是設於〇.4#m以下。 又’檢查步驟中’ LDD區域超過1.0//m之裝置則不能 滿足OFF特性❶因此，藉著進行將LDD區域之長度AL在1.0 V in以下視為良品之檢查步驟，而能選別出良品、不良品， 進而能降低在顯示板製造步驟中的材料損失。 又，如表1所示，實驗例1〜3(即滿足前述式子（2)者） 雖能抑制照射光線時之OFF電流，惟，實驗例4、5(即滿足 前述式子（6)者）乃確定不能抑制照射光線時之〇FF電流。 (下頁續） -28- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 卜——.——.----_裝--------訂_-----------線#- (請先閱讀背面之注意事項再填寫本頁) 474016 Α7 一 Β7 五、發明說明（26) 表1 ··Generally speaking, the backlight luminance is 5000 cd / m2 at the maximum. In this case, in order to obtain the empty layer width Wd for suppressing the photoconductive current to 10 ρΑ or less, it is as follows. That is, bring W = 4, B -27 into the above formula (10). This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- --- Pack—— (Please read the precautions on the back before filling this page) Order: --Line-Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 Printed by the Employee Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ V. Description of the invention (25) = 5000, Ioff = 10 * 10-12, and the width of the empty layer can be obtained, and is = 0_ 4 // m 〇 · The width of the empty layer does not exceed the length of the LDD region, so the LDD The length AL of the region is set to less than or equal to 0.4αm, so that the practically empty layer region becomes equal to or less than 0.4m / m, and a structure capable of suppressing (less than or equal to) the photoconductive current can be made. In addition, if the LDD region is smaller than 0 · 1 # m, there is no electric field relaxation effect. As shown in Fig. 2 (b), the OFF current is increased, so the LDD region is preferably larger than 0 · 1 // m . Further, in the above formula (10), when the backlight luminance B is, for example, 2000 cd / m2 or more, the width Wd of the empty layer is 1 // m. Therefore, since the width of the empty layer is not more than the length of the LDD region, the effective empty layer region can be made less than 1.0 mm by setting the length AL of the LDD region to 1.0 / zm or less. Suppress photoconductive current. Moreover, it is preferable to set it below 0.4 # m. Also, in the "inspection step", the device with an LDD area exceeding 1.0 // m cannot satisfy the OFF characteristic. Therefore, by performing the inspection step that considers the length AL of the LDD area to be less than 1.0 V in, a good product can be selected. Defective products can further reduce material loss in the manufacturing process of the display panel. As shown in Table 1, Experimental Examples 1 to 3 (that satisfies the aforementioned formula (2)) can suppress the OFF current when irradiated with light, but Experimental Examples 4, 5 (that satisfies the aforementioned formula (6) It is determined that the FF current cannot be suppressed when the light is irradiated. (Continued on the next page) -28- This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). —————————————————————— ----------- 线 #-(Please read the precautions on the back before filling out this page) 474016 Α7 一 Β7 V. Description of the invention (26) Table 1 ··

B(cd/m2) W(/zm) R(kQ/ □) OFF電流 實驗例1 3000 4 50 〇 實驗例2 5000 2 50 〇 實驗例3 5000 3 30 〇 實驗例4 3000 1 4 80 X 實驗例5 5000 4 50 X 如此一來，藉著前述式子（6)則藉由能新控制之因子 (汲極區域之薄片阻抗）與通道區域之通道寬度的關係而能 限制其抑制照射光線時之OFF電流（光傳導電流）的範圍。 因此，藉由製作滿足上述式子（6)關係的薄膜電晶體而能 抑制OFFf：流之增加，因此，能防止串擾及輝度傾斜，而 能實現高性能、高信賴度之薄膜電晶體。 (實施樣態1 一 2) 說明本發明之實施樣態1 _ 2之薄膜電晶體的製造方 法。 本實施樣態1 一 2之薄膜電晶醴係藉由陽極氧化而使 LDD區域之長度弄小形成為〇.2/zm〜0.5/zm者。藉此，由 於汲極側之區域成為高濃度之不純物區域，而使空乏層寬 度不會擴展至LDD區域之長度以上，因此，成為能抑制光 傳導電流者。以下即說明具體上的製造方法的說明。第17 圖係表示本發明之實施樣態1 一 2之薄膜電晶體的製造方法 的概略斷面圖，第18圖同樣是薄膜電晶體的製造方法的概 略斷面圖。 與前述實施樣態1一 1同樣地’在玻璃基板2上堆積膜a — Si層15，接著使用波長為308nm之準分子雷射的雷射回 -29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） -------------09^ --- (請先閱讀背面之注意事項再填寫本頁) r 經濟部智慧財產局員工消費合作社印製 474016 A7 B7 五、發明說明（27) (請先閱讀背面之注意事項再填寫本頁) 火處理而進行a — Si層15之熔化再結晶化（p— Si化）而形成 多晶石夕層16。其次，將多晶矽層16島化成一定形狀而形成 多晶石夕層3。接著於玻璃基板2上形成閘極絕緣層4用以覆 蓋多晶矽層3。（第17圖（a)〜（d))。 (5)接著作成金屬層17，而將金屬層17上將光阻膜17a 予以圖樣化，並藉著蝕刻來圖樣化前述金屬層17而形成閘 極電極5a。接著陽極氧化閘極電極5a之側面而形成氧化絕 緣層5b。（第17圖（〇)。 其次如第17圖（a)所示地進行，而將閘極電極5a作為 遮罩使用並進行不純物之摻入。具體上係以離子摻入法來 將作為不純物之磷予以摻入。藉此，閘極電極5a之正下方 位置之通道區域3c乃成為無摻入不純物之區域。而在氧化 絕緣層5b· 5b正下方位置之區域形成LDD區域3d· 3e，tc2yy3 此等區域之外側形成通道區域3a、汲極區域3b。 接著如第18圖（h)〜（j)所示，製膜成層間絕緣層 (SiOx)6，其次於層間絕緣層6及閘極絕緣層4進行連接孔 9a、9b之開口，並以濺鍍法例如將A1等金屬層充填於連接 孔9a、9b，將金屬層之上部圖樣化成一定形狀而形成源極 電極7及汲極電極8。以製作TFT。 經濟部智慧財產局員工消費合作社印製 依據本實施樣態之陽極氧化的話，能將LDD區域之長 度弄小形成為0· 2/zm〜0· 5//m者。藉此，由於没極側之區 域成為高濃度之不純物區域，而使空乏層寬度不會擴展至 LDD區域之長度以上，因此，成為能抑制光傳導電流者。 如上所述，在於薄膜電晶體之OFF時，由於前述低濃 度不純物區域成為載體之枯渴的高阻抗層，因此能達到降 -30- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 474016 A7 B7 五、發明說明（28) 低電流。至於藉著前述式子（2)能決定LDD區域之長度的方 針’且因降低電流而不必要確保必要程度以上的LDD區域。 又’前述式子（2)係藉著更滿足式子（6)而於薄膜電晶體ON 時，藉著從閘極來的電場作用而使閘極電極下之低濃度不 純區域因形成載體之電子的蓄積而形成低阻抗區域以致於 不發生ON電流的減少。爰此，要滿足前述式子（2)及式子（6) 之薄膜電晶體在十分確保ON電流之同時，能抑制OFF電流 於最少程度。 而且，摻入不純物係使用加速電壓為10kV以上30kV以 1下及電束電流密度設為〇. 5 // A/ cm2以上1 // A/ cm2以下之 低速的離子摻入法，而用以使離子摻入時之離子的加速電 壓為低，而能減少於摻入時的損傷。又，即使摻入不純物 時將光阻膜作為遮罩的情形下，光阻亦不會變質而能確實 施樣態地去除。 (實施樣態1一3) 參照第19〜第22圖來說明本發明之實施樣態1 — 3。 第19圖係表示使用本發明之實施樣態1 一 3之薄膜電晶 體之C—M0S反向器之配線圖樣的俯視圖，第20圖係其等價 電路圖’第21圖係從箭頭方向觀看第19圖之X—X，斷面圖。 C— M0S反向器50係例如構成液晶顯示裝置之驅動電 路，此C—M0S反向器50係由η—通道TFT22與p通道TFT23所 構成。Ν通道TFT22係具有與上述實施樣態1之η通道TFT1同 樣的構成，相對應的部分賦予同一元件標號。Ρ通道TFT23， 係於玻璃基板2上依順序地積層由多晶矽2層24、Si02(二 氧化矽）所構成之閘極絕緣層4，鋁所構成之閘極電極25、 -31- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--- (請先閱讀背面之注意事項再填寫本頁) ta· -線· 經濟部智慧財產局員工消費合作社印製 474016 A7 B7 五、發明說明（29) 及Si〇2所構成之層間絕緣層6。多晶石夕層24係由位於閘極 電極25之正下方的通道區域24c、配置於通道區域24c之兩 側之源極區域24a(p+層）及汲極區域24b(p+層）所構成。 (請先閱讀背面之注意事項再填寫本頁) 而且在此TFT23設置例如由鋁所構成之源極電極26及汲極 電極27。源極電極26係藉由形成於閘極絕緣層4及層間絕 緣層6之連接孔28a而連接於源極區域24a。又，沒極電極27 係藉由形成於閘極絕緣層4及層間絕緣層6之連接孔28b而 連接於源極區域24b。η通道TFT22之閘極電極5及p通道 TFT23之閘極電極25如第25圖所示般地共通地連接於輸入 端子30。又，η通道TFT22之没極電極8及ρ通道TFT23之汲 極電極27如第19圖所示般地共通地連接於輸出端子31。 本實施樣態1 一 3之中，僅將η通道TFT之汲極側作為在 前述實施樣態1 — 1所說明之LDD構造，而能弄小TFT之尺 寸，且能將汲極間距離抑制到6 範圍，比較於在源極、 没極之兩方形成LDD區域的情形下，約能作成5〇%以下的 尺寸而能達到TFT之微細化。 經濟部智慧財產局員工消費合作社印製 又，亦可將η通道TFT及p通道TFT兩者均作為LDD構造。 但是為了抑制向列基板所占有之電路面積，而僅將^通道 TFT及p通道TFT之中的任何一方作為LDD構造時，則最好是 η通道TFTMs!。此原因乃在於，比較於作為p通道τρτ之載體 的孔，與作為η通道TFT之載體的電子的各移動度之時，則 電子的一方乃明顯為大。因此，對n通道TP7及p通道tft施 加相同的電場時，η通道TFT之一方乃藉著載體而受到大的 衝擊’故η通道TFT之一方較易劣化。因此，從謀求防止tft 之劣化而在提昇信賴度的觀點來看時，最好是以η通道tft •32· 本紙張尺度適用中國國家標準（CNS)A4規格⑵〇 χ 297公餐） 474016 五 Φ 經濟部智慧財產局員工消費合作社印製 A7 B7__ 、發明說明（3Q) 之一方來作為LDD構造為宜。 以第22圖來表示在c—MOS反向器之ΟΝ/OFF時之n—ch 電晶體之偏壓狀態的動作要點。在如此的反向器之ch 中’對負極側之電源的閘極電極的極性經常以比〇v高的電 壓來作動。因此負極側之電源經常呈為n— chTFTi源極電 極而作用，而輸出側則經常作為汲極電極而作用。爰此， 使用此部分以僅輸出側部分作為上述構成的電路者，乃能 增進其縮小向列基板之電路部分所占有的面積。又，能增 進在此部分之寄生容量的減少。 (其他事項） 實施樣態1— 1〜1一 3之中，雖已說明了具有一種類濃 度的LDD區域，惟，本發明並非僅限於此，而即使是設置 濃度差為不同之多數LDD區域亦可。即，將LDD區域朝通道 區域藉由連同使不純物濃度呈階段性地降低之多數接合區 域的構成而能以多階段性地變化不純物濃度，因此，能更 加緩和在半導體層之電場的集中。 又，前述LDD區域亦可僅形成在汲極區域與通道區域 之間，藉著如此構成，在能達到降低0FF電流等的效果之 同時，亦能弄小薄膜電晶體之面積。 又，實施樣態1 一 1〜1 一 3之中，雖已說明了使用上閘 極型之TFT，惟，本發明亦可適用於底閘極型之FT。 又，在實施樣態1 — 1〜1 — 3之中所說明之薄膜電晶 體’除了適用於液晶顯示裝置之外，亦可適用於EL裝置。 亦即’將實施樣態1 一1〜1 一 3所記載之薄膜電晶體作為開 關元件而於基板上多數形成，藉著具有該基板之EL裝置而 -33- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ----------II-----—— — — — ^^— — 1 — II A (請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（31) 能作成抑制光傳導電流的構成。 (第2發明群的概念） 本發明之目的係在抑制薄膜電晶體（以下稱TFT)之〇FF 電流之同時’藉著將LDD區域之長度抑制在必要的最小限 度而抑制ON電流之減少的構成而達到實施樣態現具有高信 賴度之TFT。因此，本發明人等為了求得真正必要的ldd區 域的長度，而错由模擬LDD區域部分而進行動作解析，並 求出電場之相關區域為多少程度。 第23圖係表示模擬將薄片阻抗作為步數而將LDD區域 從0· 5/z m變化至3/zm為止之情形下之VG — Id特性之結果的 曲線圖。 藉由此一結果，雖然VG—Id特性相對於LDD區域之濃 度乃具有大的依存性，惟，可確認相對於LDD區域之長度 並不具有依存性。以下即探究其原因。 在第24圖之通道區域與LDD區域中，表示模擬將TFT設 為OFF狀態之情形下（Vg= — 10V、Vd=6V時）之電場的結 果。 由前述模擬結果可確認電場之相關區域係依存著薄片 阻抗，當其薄片阻抗為2〇ΙςΩ/□的情形下為0.4/zm，而 薄片阻抗為lOOkD/□的情形下則為1· 〇m。 爰此’可確認即使將LDD區域弄大至電場之相關區域 以上亦對緩和電場之效果上無效，且僅於電晶鱧之通道區 域上阻抗串聯地插入。 又，第25圖係表示具有實際之LDD區域之TFT之LDD區 域之長度（△0與OFF電流及LDD區域之長度（△!〇與ON電流 -34- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） ^——-——.------------π·ίιτ---- (請先閱讀背面之注意事項再填寫本頁) 47401^ Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（32) 之關係的曲線圖。又，LDD區域之薄片阻抗為i〇〇kQ /匚]。 如第2 5圖所示，即使將LDD區域設得比1 &quot; m長亦無降 低OFF電流的效果，而反映前述之模擬結果。又，如第25 圖所示，一旦將LDD區域設得比l//m長的話，不能充分確 保ON電流而使ON電流降低。依此結果，藉著將LDD區域之 範圍設在1 V m以上而在充分確保ON電流之同時，能抑制〇ff 電流至於小。又，以下之實施樣態係依據前述模擬而具體 地說明製作TFT者。又，實際上的TFT製作步驟中，為了確 保前述之LDD區域而將於之後說明，然而，係能藉著在合 對遮罩之際的合對標記而決定。 (貫施樣態2 — 1) 第26圖係實施樣態2— 1之薄膜電晶體之簡略化斷面 圖’第27圖係第26圖的概略俯視圖。 在本實施樣態2—1中，表示著將本發明應用於n通道 薄膜電晶體之例子。此薄膜電晶體（以下稱TFT) 101係由在 玻璃基板102上依順序地積層膜厚為500埃之多晶矽層 1〇3、膜厚為1〇〇〇埃之si〇2(二氧化矽）所構成的閘極絕緣層 1〇4、鋁所構成之閘極電極105a、及Si〇2所構成之層間絕緣 膜1〇6而構成者。前述閘極電極l〇5a係被光阻膜105b覆蓋 而形成。又，亦可取代前述光阻膜l〇5b而使用金屬膜。 又’前述多晶矽層103係由位於閘極電極1055a之正下 方的通道區域l〇3c、不純物濃度高的源極區域i〇3a(n + 層）、不純物濃度高的汲極區域l〇3b(n+層）、及不純物濃 度低的高的低濃度不純物區域（LDD區域：η—層）103d、103e 所構成。低濃度不純物區域l〇3d係介在於源極區域l〇3a與 -35- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） -- (請先閱讀背面之注意事項再填寫本頁) ί 言 Τ 良 A7 474016 B7__ 五、發明說明（33 ) 通道區域103c之間，低濃度不純物區域l〇3e係介在於汲極 區域103b與通道區域103c之間。此等低濃度不純物區域 103d、103e乃位於從光阻膜105b之閘極電極l〇5a延伸出的 部分105bl、105b2之正下方。因此，低濃度不純物區域l〇3d 與源極區域103a之接合面乃約與光阻膜l〇5b之端面（第1圖 之左側端面）一致，低濃度不純物區域l〇3d與通道區域103c 之接合面乃約與閘極電極105a之端面（第1圖之左側端面） 一致。又，低濃度不純物區域103e與汲極區域103b之接合 面乃約與光阻膜105b之端面（第1圖之右侧端面）一致，而 低濃度不純物區域103d與通道區域l〇3c之接合面乃約與閘 極電極105a之端面（第1圖之右側端面）一致。又，本發明 之低濃度不純物區域的長度△ L係設定在l//m以上1.5/ζιη 以下，而通道寬度W則設定在5# m。 再者，在TFT101更設有例如由鋁所構成之源極電極107 及汲極電極108，源極電極107乃藉由形成於閘極絕緣層104 及層間絕緣層106之連接孔109a而連接於源極區域103a， 又，汲極電極108係藉由形成於閘極絕緣層104及層間絕緣 層106之連接孔109b而連接於汲極區域l〇3b。 其次說明本發明之實施樣態2— 1之薄膜電晶體之製造 方法。第28圖、29圖係表示本發明之實施樣態1一 1之薄膜 電晶體之製造方法的概略斷面圖，第30圖係表示本發明之 實施樣態1 — 1之薄膜電晶體之製造方法的流程圓。 (1)首先以電漿CVD法在玻璃基板102上堆積膜厚為500 埃之a—Si層105，接著以400°C來進行脫氫處理（第28圖 (a))。此脫氫處理之目的乃在於防止進行結晶化之際，因 -36- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-----------#裝-------訂------1---線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 474016 A7 B7 五、發明說明（34) 氫之脫離所造成Si膜的消融（ablation)。又，形成a—Si 之步驟係除了使用電漿CVD之外，亦能使用減壓CVD及濺鍍 法等處理。又，亦能使用電漿CVD以外的方法來直接堆積 聚矽膜。此情形下，則不須要將於後述之使用雷射來回火 的步驟。 (2) 其次，藉著使用波長為308nm之準分子雷射的雷射 回火處理而進行8 —Si層115之溶化再結晶化（p—Si化）而 形成多晶矽層116(第28圖（b))。 (3) 其次，將多晶矽層116島化成一定形狀而形成多晶 矽層103(第28圖（c))。 (4) 接著於玻璃基板102上形成閘極絕緣層104用以覆 蓋多晶矽層103，而形成厚度為1000埃之Si02(二氧化矽）層 (第 28圖（d))。 (5) 接著作成閘極電極105a，而製膜成由鋁所構成之 金屬層117(第28圖（e))。 (6) 接著將金屬層117予以圖樣化成一定形狀而形成閘 極電極105a(第28圖（〇)。 (7) 接著將閘極電極105a作為遮罩來使用而進行不純 物的摻入（第28圖（g))。具體而言，即以離子摻入法來摻 入作為不純物之磷離子。藉此，位於閘極電極105a之正下 方的通道區域103c乃為未摻入不純物的區域。至於除去多 晶矽層103之通道區域103c的區域則成為摻入不純物之 層。又，此情形下之摻入加速電壓設為80kV而電束電流密 度設為1#A/cm2，而以高加速來作成低濃度之η型區域 者。 -37- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） ------------- (請先閱讀背面之注意事項再填寫本頁) 言 r 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 474016 A7 B7 五、發明說明（35) (8) 接著覆蓋閘極電極105a而製膜成光阻膜ιΐ8(第28 圖⑻）。 (9) 接著使光阻膜118形成圖樣化而形成阻抗膜i〇5b( 第29圖（i))。在此，對於（9)之步驟係使用第31〜34圖來 詳細說明。第31圖係係說明形成LDD區域之步驟的概略斷 面步驟圖，第32圖係光罩與基板之立體圖，第33圖同樣地 為俯視圖，第34圖係LDD區域形成後之薄膜電晶體的概略 斷面圖。 如第7圖所示，光阻膜140與基板1〇2呈相對向地配置 ，光阻膜140之上方位置配置著合對位置用的光源（圖式未 顯示），從前述合對位置用的光源對光阻膜14〇及基板〇2所 各別形成之合對位置標記141、142射入雷射光束，並藉由 讀取各別的合對位置標記的位置信號而進行合對位置。 前述光阻膜140之一定位置（光阻膜之角落的1〇2位置） 形成略正方形狀之合對位置標記141。又，光阻膜140之中 央位置形成複寫至基板102之遮蔽膜的圖樣（圖式未顯示） 〇 又，於玻璃基板102上，且於與前述合對位置標記141 對應的位置形成合對位置標記142。該合對位置標記142係 設成周圍以黑色區域包圍之略正方形狀之透明的區域。又 ，雖然未以圖式顯示，惟，前述合對位置標記141、142之 形狀並非限定為正方形，例如設為圓形狀亦可。 如第33圖（a)所示，在光罩140與基板102之位置未偏 移的情形下，形成光罩140之合對位置標記141係位於形成 在基板102之合對位置標記142之透明的區域的中央，以其 -38- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） h---,---.----#裝--------訂----r----線 (請先閱讀背面之注意事項再填寫本頁) 474〇ΐβ 經 濟- 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 Α7 五、發明說明（36 ) 狀態形成LDD區域的情形下，該LDD區域l〇3d、103e之長度 △ L係設定為1. 25 // m。 又，前述基板102與光罩140之位置偏移，而使合對位 置標記141不能進入合對位置標記142内的話，可瞭解所形 成之LDD區域的長度變得為1.5/zm大，因此，在此種情形 下，為使合對位置標記141進入合對位置標記142而要合對 基板與光罩的位置。又，即使將前述合對位置標記141合 對於合對位置標記142之中央亦在實際上如第33圖（b)所示 ，紙面上向左右搖擺的情形。然而，本發明因合對位置裝 置之精密度為±0· 25 // m，故能將合對位置標記141置於合 對位置標記142内。如此一來如第34圖所示，能將所形成 之LDD區域3d、3e之長度設在1〜1· 5// m以内。又，合對位 置裝置之精密度雖然為±〇· 25 em，但若是使用精密度更 好的裝置時則能更弄小LDD區域之不均。 其次說明前1述光罩之合對位置的步驟。 如第31圖（a)所示，於閘極電極i〇5a上形成作為遮蔽 膜之光阻。 其次如第31圖（b)、（c)所示，藉由光阻140而對該光 阻進行曝光，進行顯像而形成一定形狀之圖樣狀的遮蔽膜 105b 〇 此情形下如前述一般，確認合對位置標記141進入合 對位置標記142之透明部分内之後進行曝光。 (1〇)接著如第29圖（b)所示，將阻抗膜i〇5b作為遮罩 使用並進行第二次的掺入不純物。具體而言，係以離子摻 入法來摻入作為不純物之鱗離子。此時之摻入加速電壓設 ----------- 裝 i I ! I I I 訂！！ (請先閱讀背面之注意事項再填寫本頁) •39- 474016 經濟部智慧財產局員工消費合作社印製 A7 _ B7_ 五、發明說明（37 ) 為12kV而電束電流密度設為0· 5 // A/cm2，以低加速來作成 高濃度之η型區域。 藉此，在多晶矽層103之中，除掉位於光阻膜205b之 正下的區域會被摻入離子。因此，在藉著第一次之離子摻 入而使不純物已被摻入之區域之中，在未被光阻膜l〇5b覆 蓋的區域（相當於源極區域103a、汲極區域i〇3b)更呈現被 摻入不純物，而呈不純物高濃度區域（η +層）。另一方面， 區域A、Β之中，被光阻膜105b覆蓋的區域（相當於低濃度 不純物區域103d、103e)，藉由第二次之離子摻入的話， 則不摻入不純物而呈低濃度不純物區域（n—層）。如此一 來，源極區域l〇3a(n+層）與通道區域l〇3c之間形成低濃 度不純物區域l〇3d(n—層），又，能在汲極區域i〇3b(n + 層）與通道區域103c之間形成低濃度不純物區域i〇3e(n — 層）。又，將閘極電極105a作為遮罩而進行第一次之離子 摻入，而且將光阻膜105b作為遮罩而進行第二次之離子摻 入，故能將源極區域103a、低濃度不純物區域i〇3d · 103e 及汲極區域l〇3b予以自行整合上的形成，且能將閘極電極 5與源極區域i〇3a之重疊部分，以及閘極電極1〇5與汲極區 域103b之重疊部分以甚至不須考慮的情形下抑制為小。麦 此’肖b形成LDD區域之長度為1〜1β5μπι之薄膜電晶體，而 在能降低OFF電流之同時，能儘可能地抑制ON電流的降低。 (11) 其次製膜成層間絕緣層（Si〇x)106(第29圖（c ))。 (12) 其次於層間絕緣層1〇6及閘極絕緣層104進行連接 孔 109a、l〇9b之開口（第 29圖（d)) (13) 以濺鍍法將A1等金屬層充填於連接孔109a、 -40- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐Γ-------- (請先閱讀背面之注意事項再填寫本頁) ►裝 •線· 474016 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（38) l〇9b’將金屬層之上部圖樣化成一定形狀而形成源極電極 107及汲極電極108(第29(e)圖）。以製作TFT101。 前述之例子雖已說明了 η通道TFT，惟，對於p通道TFT 亦能以同樣的製造處理來製造。 以第35圖來表示藉由前述製造方法所製造之薄膜電晶 體之電壓/電流特性，且以第36圖來表示OFF電流之基板 面内之不均。 如第13圖所示’本實施樣態2—1之TFT101CL3之曲線 圖），係將高阻抗區域之LDD區域為1〜1·5μιη那樣小，因此， 能確保穩定之大的ON電流及小的〇ff電流。 又’當然對準之合對精密度提昇的話，則更能弄小LDD 區域的長度。又，藉著將n—區域之載體濃度弄大而會使 電場相關區域變小，惟，在另一方面由於電場之峰值會變 高，故會增加OFF電流。 在第37圖中係將LDD區域之濃度作為參數而表示模擬 薄膜電晶體之Vg — Id特性的結果。 LDD區域之薄片阻抗在2〇kQ/□以下而OFF電流乃急 劇地變大。爰此，LDD區域之薄片阻抗有必要至少設於20k Ω/□以上。另一方面，LDD區域之薄片阻抗設在lOOkQ /□以上時，電晶體之ON電流會降低而使顯示面板之動作 變得不穩定。因此，LDD區域之薄片阻抗的範圍最好是設 於20kQ/□以上100kD/□以下。 又，最初之摻入不純物係藉著使用加速電壓為10kV以 上30kV以下，以及電束電流密度為〇.〇5μΑ/αη2以上ΙμΑ/ cm2以下之低速的離子摻入法而使離子摻入時之離子的加 -41- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------I---裝------訂！！線 (請先閱讀背面之注意事項再填寫本頁) 474016 A7 B7 五、發明說明（39) 速電壓低，因此，能使摻入時之損傷變小。 又，將第一次之摻入不純物時的光阻作為遮麥 下亦能使光阻不會變質且乾淨地去除。 或是第二次之摻入不純物係使用加速電壓為 及電束電流密度為l#m/cm2以上之高速的離子摻A 而在第二次的離子摻入時亦能充分地將離子注入黎# 又，本實施樣態2—1之構成TFT101之LD區域的長 L係設為lem以上1.5/zm以下，而將源極一汲極間的 Vic設為6V、將通道寬度設為6//m的條件下進行 樣對 般而言OFF電流係依源極/汲極間的電場而定，VP'/Α 通道區域/LDD區域施加，因此，電場之強度以vlC/ 表示（Solid State Electron，38，2075(1995))。多 場之強度則以其次的式子表示。4* 106&lt; Vlc/AL&lt;6* 106 OFF電流與通道寬度W成比例，故前述ldd區威么 € 長虞關孫 經濟部智慧財產局員工消費合作社印製 △ LDD區域與前述源極一没極間電壓71〇通道寬度 能以下記式子（3)表示。 △ L&gt; (W · Vlc)/36 …（3) 接著卜說明前述式子（3)之意義。TFTi小型化的進展 情形下，前述AL、W值會變小，伴隨於此，源極一汲極間 電壓Vic會降低。因此，以下記表2來表示變化LDD區域之 長度AL、源極·汲極間電極Vic與通道寬度特性。 (下頁續）B (cd / m2) W (/ zm) R (kQ / □) OFF Current Experimental Example 1 3000 4 50 〇 Experimental Example 2 5000 2 50 〇 Experimental Example 3 5000 3 30 〇 Experimental Example 4 3000 1 4 80 X Experimental Example 5 5000 4 50 X In this way, according to the aforementioned formula (6), the relationship between the newly controllable factor (the sheet impedance of the drain region) and the channel width of the channel region can be used to limit the time when it suppresses the light. Range of OFF current (photoconductive current). Therefore, by forming a thin-film transistor satisfying the relationship of the above formula (6), the increase in OFFf: current can be suppressed, so that crosstalk and luminance tilt can be prevented, and a thin-film transistor with high performance and high reliability can be realized. (Embodiment 1 to 2) A method for manufacturing a thin film transistor according to Embodiments 1 to 2 of the present invention will be described. In this embodiment, the thin film transistors 1-2 are formed by anodic oxidation to reduce the length of the LDD region to 0.2 / zm to 0.5 / zm. Thereby, since the region on the drain side becomes a high-concentration impurity region, and the width of the empty layer does not extend beyond the length of the LDD region, it becomes a person capable of suppressing photoconductive current. The following is a description of a specific manufacturing method. Fig. 17 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to aspects 1 to 2 of the present invention, and Fig. 18 is a schematic cross-sectional view also showing a method for manufacturing a thin film transistor. The film a-Si layer 15 is deposited on the glass substrate 2 in the same manner as in the foregoing embodiment 1-1, and then a laser back with an excimer laser with a wavelength of 308 nm is used. -29- This paper applies Chinese national standards (CNS ) A4 specification (210 χ 297 mm) ------------- 09 ^ --- (Please read the precautions on the back before filling out this page) r Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 474016 A7 B7 V. Description of the invention (27) (Please read the precautions on the back before filling out this page) Fire treatment to melt and recrystallize (p-Si) the a-Si layer 15 to form polycrystalline stones Evening floor 16. Next, the polycrystalline silicon layer 16 is islanded into a certain shape to form a polycrystalline silicon layer 3. Then, a gate insulating layer 4 is formed on the glass substrate 2 to cover the polycrystalline silicon layer 3. (Figures 17 (a) to (d)). (5) The metal layer 17 is formed next, and the photoresist film 17a is patterned on the metal layer 17, and the metal layer 17 is patterned by etching to form the gate electrode 5a. Next, the side surfaces of the gate electrode 5a are anodized to form an oxidation insulating layer 5b. (Fig. 17 (〇). Next, as shown in Fig. 17 (a), the gate electrode 5a is used as a mask and impurities are introduced. Specifically, the impurities are used as impurities by the ion doping method.) Phosphorus is doped. As a result, the channel region 3c immediately below the gate electrode 5a becomes a region free from impurities, and an LDD region 3d · 3e is formed in a region directly below the oxide insulating layer 5b · 5b. tc2yy3 Channel regions 3a and drain regions 3b are formed outside these regions. Next, as shown in Figs. 18 (h) to (j), an interlayer insulating layer (SiOx) 6 is formed, followed by the interlayer insulating layer 6 and the gate. The electrode insulating layer 4 opens the connection holes 9a and 9b, and fills the connection holes 9a and 9b with a metal layer such as A1 by a sputtering method. The upper portion of the metal layer is patterned into a certain shape to form the source electrode 7 and the drain electrode. Electrode 8. TFT is produced. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the anodization in accordance with this embodiment, which can reduce the length of the LDD area to 0.2 · zm ~ 0.5 · / m. As a result, since the region on the non-polar side becomes a high-concentration impurity region , So that the width of the empty layer does not extend beyond the length of the LDD region, so it becomes a person who can suppress the photoconductive current. As mentioned above, when the thin film transistor is turned off, the aforementioned low-concentration impurity region becomes a thirsty carrier. High impedance layer, so it can reach -30- This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 474016 A7 B7 V. Description of the invention (28) Low current. As for the above formula ( 2) A policy that can determine the length of the LDD region ', and it is not necessary to ensure an LDD region that is more than necessary because the current is reduced. Also, the aforementioned expression (2) is to turn on the thin film transistor by satisfying the expression (6) more. At this time, the low-impurity region under the gate electrode is formed by the accumulation of electrons forming a carrier by the action of the electric field from the gate electrode to form a low-impedance region so that the reduction of the ON current does not occur. The thin film transistor of the formula (2) and the formula (6) can ensure the ON current at the same time, and can suppress the OFF current to a minimum. In addition, the impure material should be used with an acceleration voltage of 10kV or more and 30kV or less. The beam current density is set to 0.5 // A / cm2 above 1 // A / cm2 below the low-speed ion doping method, and the acceleration voltage of the ions used for ion doping is low, which can reduce the doping Damage during entry. In addition, even when a photoresist film is used as a mask when impure substances are incorporated, the photoresist will not be deteriorated and can be removed in an exact manner. (Implementation Modes 1 to 3) Refer to Section 19 ~ Fig. 22 is a diagram for explaining Embodiments 1 to 3 of the present invention. Fig. 19 is a plan view showing a wiring pattern of a C-M0S inverter using a thin film transistor of Embodiments 1 to 3 of the present invention, and Fig. 20 Figure 21 is the equivalent circuit diagram. Figure 21 is a sectional view of X-X in Figure 19 viewed from the direction of the arrow. The C-MOS inverter 50 is, for example, a driving circuit for a liquid crystal display device. The C-MOS inverter 50 is composed of an n-channel TFT22 and a p-channel TFT23. The N-channel TFT 22 has the same configuration as that of the n-channel TFT 1 of the first embodiment, and the corresponding components are given the same reference numerals. The P-channel TFT23 is a gate insulating layer 4 composed of polycrystalline silicon 2 layer 24, SiO2 (silicon dioxide), and a gate electrode 25 composed of aluminum on a glass substrate 2 in order. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- install --- (Please read the precautions on the back before filling this page) ta · -line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 A7 B7 V. Description of the invention (29) and the interlayer insulation layer 6 composed of Si02. The polycrystalline stone layer 24 is composed of a channel region 24c directly below the gate electrode 25, a source region 24a (p + layer) and a drain region 24b (p + layer) arranged on both sides of the channel region 24c. (Please read the cautions on the back before filling in this page.) The TFT 23 is provided with a source electrode 26 and a drain electrode 27 made of aluminum, for example. The source electrode 26 is connected to the source region 24a through a connection hole 28a formed in the gate insulating layer 4 and the interlayer insulating layer 6. The non-polar electrode 27 is connected to the source region 24b through a connection hole 28b formed in the gate insulating layer 4 and the interlayer insulating layer 6. The gate electrode 5 of the n-channel TFT 22 and the gate electrode 25 of the p-channel TFT 23 are commonly connected to the input terminal 30 as shown in FIG. The electrode electrode 8 of the n-channel TFT 22 and the drain electrode 27 of the p-channel TFT 23 are commonly connected to the output terminal 31 as shown in FIG. 19. In aspects 1 to 3 of this embodiment, only the drain side of the n-channel TFT is used as the LDD structure described in the foregoing embodiment 1 to 1, so that the size of the TFT can be reduced, and the distance between the drains can be suppressed. In the range of 6, compared with the case where the LDD region is formed on both the source and the electrode, the size can be made smaller than about 50% and the TFT can be miniaturized. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Both η-channel TFT and p-channel TFT can be used as LDD structures. However, in order to suppress the circuit area occupied by the nematic substrate, when only one of the ^ -channel TFT and the p-channel TFT is used as the LDD structure, it is preferable to use η-channel TFTMs !. The reason for this is that when comparing the pores of the carrier serving as the p-channel τρτ with the respective mobility of the electrons serving as the carrier of the n-channel TFT, the electron is significantly larger. Therefore, when the same electric field is applied to the n-channel TP7 and the p-channel tft, one of the n-channel TFTs is greatly impacted by the carrier ', so one of the n-channel TFTs is more likely to deteriorate. Therefore, from the viewpoint of improving the reliability in order to prevent the deterioration of tft, it is best to use the η channel tft • 32. This paper size is applicable to the Chinese National Standard (CNS) A4 standard ⑵〇χ 297 public meal) 474016 5 Φ One of the employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 B7__ and Invention Note (3Q) as the LDD structure. Figure 22 shows the main points of the bias state of the n-ch transistor when the c-MOS inverter is ON / OFF. In such an inverter ch, the polarity of the gate electrode of the power source on the negative side is often operated at a voltage higher than 0V. Therefore, the power supply on the negative side often functions as an n-chTFTi source electrode, while the output side often functions as a drain electrode. Therefore, those who use this part with only the output side part as the circuit of the above-mentioned configuration can increase the area occupied by the circuit part of the nematic substrate. In addition, the reduction in parasitic capacity in this portion can be increased. (Other matters) Although the LDD regions having one kind of concentration have been described in the implementation patterns 1 to 1 to 1 to 3, the present invention is not limited to this, and even if a plurality of LDD regions having different concentration differences are provided, Yes. That is, since the LDD region is directed toward the channel region, the impurity concentration can be changed in multiple stages by the configuration of a plurality of junction regions in which the impurity concentration is gradually reduced. Therefore, the concentration of the electric field in the semiconductor layer can be more relaxed. In addition, the aforementioned LDD region may be formed only between the drain region and the channel region. With such a structure, the effect of reducing the 0FF current and the like can be achieved, and the area of the thin film transistor can be reduced. In addition, in the implementation modes 1 to 1 to 1 to 3, although the use of an upper gate type TFT has been described, the present invention can also be applied to a bottom gate type FT. In addition, the thin film electro-crystals' described in the embodiments 1-1 to 1-3 can be applied to an EL device in addition to a liquid crystal display device. That is, most of the thin film transistors described in Implementation Modes 1-1 to 1-3 are used as switching elements on the substrate, and the EL device with the substrate is used. -33- This paper standard applies to Chinese national standards ( CNS) A4 specification (210 x 297 mm) ---------- II -----—— — — — ^^ — — 1 — II A (Please read the notes on the back before filling (This page) 474016 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (31) It can make a structure that suppresses light conduction current. (Concept of the second invention group) The object of the present invention is to suppress the reduction of ON current by suppressing the 0FF current of a thin film transistor (hereinafter referred to as a TFT) while reducing the length of the LDD region to a necessary minimum. The TFT that has been constructed to achieve the implementation state now has high reliability. Therefore, in order to obtain the length of the ldd area which is really necessary, the present inventors performed operation analysis by simulating the LDD area part, and calculated how much the electric field related area is. Fig. 23 is a graph showing the results of VG-Id characteristics in a case where the LDD region is changed from 0.5 / zm to 3 / zm using the sheet impedance as the number of steps. From this result, although the VG-Id characteristic has a large dependency on the concentration of the LDD region, it can be confirmed that it does not have a dependency on the length of the LDD region. Here's why. In the channel area and the LDD area in Fig. 24, the results of the simulation of the electric field when the TFT is turned OFF (when Vg = -10V and Vd = 6V) are shown. From the foregoing simulation results, it can be confirmed that the relevant area of the electric field depends on the sheet impedance, which is 0.4 / zm when the sheet impedance is 20 ΙΩ / □, and 1.0 · m when the sheet impedance is 100 kD / □. . In this case, it can be confirmed that even if the LDD region is enlarged to the relevant region of the electric field, the effect of mitigating the electric field is not effective, and the impedance is inserted in series only in the channel region of the transistor. In addition, Figure 25 shows the length of the LDD region of the TFT with the actual LDD region (△ 0 and OFF current and the length of the LDD region (△! 〇 and ON current -34-) This paper standard is applicable to the Chinese National Standard (CNS) A4 specifications (21〇X 297 mm) ^ ——-——.------------ π · ίιτ ---- (Please read the precautions on the back before filling this page) 47401 ^ Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The graph of the relationship between the invention description (32). In addition, the sheet impedance in the LDD region is 100kQ / 匚]. As shown in Figure 25, Even if the LDD region is set longer than 1 &quot; m, the effect of reducing the OFF current is not reflected, and the aforementioned simulation results are reflected. As shown in FIG. 25, once the LDD region is set longer than 1 // m, The ON current cannot be sufficiently ensured to reduce the ON current. As a result, by setting the range of the LDD region to 1 V m or more, the ON current can be sufficiently ensured while suppressing the ff current to be small. The following implementation is also implemented. The aspect is to specifically describe the TFT producer based on the simulation described above. In addition, in actual TFT fabrication steps, in order to ensure the aforementioned The LDD region will be described later, however, it can be determined by the pair mark in the case of the pair mask. (Continuous application mode 2-1) Figure 26 shows the thin film of implementation mode 2-1. A simplified cross-sectional view of a transistor 'FIG. 27 is a schematic top view of FIG. 26. In aspect 2-1 of this embodiment, an example in which the present invention is applied to an n-channel thin film transistor is shown. This thin film transistor ( Hereinafter referred to as TFT) 101 is a gate electrode composed of a polycrystalline silicon layer 10 with a thickness of 500 angstroms and a SiO 2 (silicon dioxide) with a thickness of 1000 angstroms on a glass substrate 102 in this order. The insulating layer 104, the gate electrode 105a made of aluminum, and the interlayer insulating film 106 made of Si02 are formed. The gate electrode 105a is formed by covering with a photoresist film 105b. Alternatively, a metal film may be used instead of the photoresist film 105b. The polycrystalline silicon layer 103 is formed by a channel region 103c located directly below the gate electrode 1055a, and a source region i03 with a high impurity concentration. n + layer), the drain region 103b (n + layer) with a high impurity concentration, and the low-concentration impurity with a high impurity concentration The area (LDD area: η-layer) is composed of 103d and 103e. The low-concentration impurity area 103d is interposed between the source area 103a and -35- This paper standard applies to China National Standard (CNS) A4 specification (210 χ 297 mm)-(Please read the precautions on the back before filling out this page) ί 言 良 良 A7 474016 B7__ V. Description of the invention (33) Between the channel area 103c, the low-concentration impurity area 1033e is located in the drain Between the pole region 103b and the channel region 103c. These low-concentration impurity regions 103d and 103e are located directly below the portions 105bl and 105b2 extending from the gate electrode 105a of the photoresist film 105b. Therefore, the joint surface between the low-concentration impurity region 103d and the source region 103a is approximately the same as the end surface of the photoresist film 105b (the left end surface in FIG. 1), and the low-concentration impurity region 103d and the channel region 103c The bonding surface approximately matches the end surface of the gate electrode 105a (the left end surface in FIG. 1). In addition, the joint surface between the low-concentration impurity region 103e and the drain region 103b is approximately the same as the end surface of the photoresist film 105b (the right end surface in FIG. 1), and the joint surface between the low-concentration impurity region 103d and the channel region 103c. The agreement is consistent with the end surface of the gate electrode 105a (the right end surface in FIG. 1). In addition, the length ΔL of the low-concentration impurity region of the present invention is set to 1 // m or more and 1.5 / ζm or less, and the channel width W is set to 5 # m. Furthermore, the TFT 101 is further provided with a source electrode 107 and a drain electrode 108 made of, for example, aluminum. The source electrode 107 is connected to the connection hole 109 a formed in the gate insulating layer 104 and the interlayer insulating layer 106. The source region 103a and the drain electrode 108 are connected to the drain region 103b through a connection hole 109b formed in the gate insulating layer 104 and the interlayer insulating layer 106. Next, a method for manufacturing a thin film transistor according to embodiment 2-1 of the present invention will be described. 28 and 29 are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to Embodiment 1 to 1 of the present invention, and FIG. 30 is a diagram showing the production of a thin film transistor according to Embodiment 1 to 1 of the present invention. Method flow round. (1) First, an a-Si layer 105 having a thickness of 500 angstroms was deposited on the glass substrate 102 by a plasma CVD method, and then a dehydrogenation treatment was performed at 400 ° C (Fig. 28 (a)). The purpose of this dehydrogenation treatment is to prevent crystallization, because -36- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I ----------- # 装 ------- Order ------ 1 --- line (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 474016 A7 B7 V. Invention Explanation (34) Ablation of the Si film caused by the release of hydrogen. The step of forming a-Si can be performed by using a reduced pressure CVD or a sputtering method in addition to plasma CVD. In addition, a method other than plasma CVD can be used to directly deposit a polysilicon film. In this case, it is not necessary to use the laser to fire back and forth as described later. (2) Second, the 8-Si layer 115 is melted and recrystallized (p-Siized) by laser tempering using an excimer laser with a wavelength of 308 nm to form a polycrystalline silicon layer 116 (Fig. 28 (Fig. 28) b)). (3) Next, the polycrystalline silicon layer 116 is islanded into a certain shape to form a polycrystalline silicon layer 103 (Fig. 28 (c)). (4) Next, a gate insulating layer 104 is formed on the glass substrate 102 to cover the polycrystalline silicon layer 103 to form a Si02 (silicon dioxide) layer having a thickness of 1000 angstroms (Fig. 28 (d)). (5) The gate electrode 105a is formed next, and a metal layer 117 made of aluminum is formed (FIG. 28 (e)). (6) Next, pattern the metal layer 117 into a certain shape to form the gate electrode 105a (Fig. 28 (0). (7) Next, use the gate electrode 105a as a mask to incorporate impurities (p. 28). (G)). Specifically, the impurity ion is doped with phosphorus ions by the ion doping method. As a result, the channel region 103c located directly below the gate electrode 105a is a region where the impurity is not doped. The region except the channel region 103c of the polycrystalline silicon layer 103 becomes a layer doped with impurities. Also, in this case, the doped acceleration voltage is set to 80 kV and the beam current density is set to 1 # A / cm2. For low-concentration η-type areas. -37- This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) ------------- (Please read the note on the back first Please fill in this page for further information.) Rr Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Employees' Cooperatives of the Ministry of Economic Affairs and the Consumers' Cooperatives printed by 474016 A7 B7 V. Invention Description (35) Into a photoresist film (Figure 28) (9). 118 is patterned to form a resistive film i05b (Fig. 29 (i)). Here, the steps of (9) are described in detail using Figs. 31 to 34. Fig. 31 is an illustration of forming the LDD region. Figure 32 is a schematic sectional view of a step. Figure 32 is a perspective view of a photomask and a substrate. Figure 33 is a top view, and Figure 34 is a schematic sectional view of a thin film transistor after the LDD region is formed. It is shown that the photoresist film 140 is disposed opposite to the substrate 102, and a light source (not shown) for the paired position is arranged above the photoresist film 140, and the photoresist is blocked from the light source for the paired position. The paired position marks 141 and 142 formed by the film 14 and the substrate 02 are irradiated into the laser beam, and the paired position is performed by reading the position signals of the respective paired position marks. A certain position of 140 (a position of 102 in the corner of the photoresist film) forms a slightly square paired position mark 141. Furthermore, the center position of the photoresist film 140 forms a pattern of a masking film that is copied to the substrate 102 (illustration not shown) (Shown) 〇 Again, on the glass substrate 102, and in a paired position with the aforementioned The position corresponding to the note 141 forms a paired position mark 142. The paired position mark 142 is a slightly square transparent area surrounded by a black area. Although not shown in the diagram, the aforementioned paired position The shape of the marks 141 and 142 is not limited to a square shape, and may be, for example, a circular shape. As shown in FIG. 33 (a), when the positions of the photomask 140 and the substrate 102 are not shifted, the photomask 140 is formed. The pair position mark 141 is located in the center of the transparent area of the pair position mark 142 formed on the substrate 102, and its -38- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) h- -, ---.---- # 装 -------- Order ---- r ---- line (Please read the precautions on the back before filling this page) 474〇ΐβ Economy- Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative A7. V. Invention Description (36) In the case where the LDD region is formed, the length ΔL of the LDD region 103d, 103e is set to 1. 25 // m. In addition, if the positions of the substrate 102 and the photomask 140 are shifted so that the paired position mark 141 cannot enter the paired position mark 142, it can be understood that the length of the formed LDD region becomes 1.5 / zm. Therefore, In this case, the positions of the substrate and the photomask need to be aligned in order for the alignment position mark 141 to enter the alignment position mark 142. In addition, even if the center of the paired position mark 141 is aligned with the center of the paired position mark 142, as shown in FIG. 33 (b), the paper surface swings left and right. However, according to the present invention, since the precision of the paired position device is ± 0 · 25 // m, the paired position mark 141 can be placed in the paired position mark 142. In this way, as shown in Fig. 34, the length of the formed LDD regions 3d and 3e can be set within 1 to 1.5 m. In addition, although the precision of the paired position device is ± 0.25 em, if the device with a higher precision is used, the unevenness of the LDD region can be further reduced. Next, the procedure for matching the positions of the photomasks described above will be described. As shown in FIG. 31 (a), a photoresist is formed on the gate electrode i05a as a shielding film. Next, as shown in FIGS. 31 (b) and (c), the photoresist is exposed by the photoresist 140 and developed to form a patterned masking film 105b in a certain shape. In this case, it is as described above. After confirming that the paired position mark 141 has entered the transparent portion of the paired position mark 142, exposure is performed. (10) Next, as shown in FIG. 29 (b), the impedance film i05b is used as a mask, and impurities are doped a second time. Specifically, the scale ion is doped as an impurity by an ion doping method. At this time, add the acceleration voltage setting ----------- Install i I! I I I Order! !! (Please read the precautions on the back before filling this page) • 39- 474016 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7_ V. Description of the invention (37) is 12kV and the beam current density is set to 0.5 · 5 / / A / cm2 to create a high-concentration n-type region with low acceleration. Thereby, in the polycrystalline silicon layer 103, a region located directly under the photoresist film 205b is removed, and ions are doped. Therefore, among the regions where impurities have been incorporated by the first ion doping, the regions not covered by the photoresist film 105b (equivalent to the source region 103a and the drain region 103b) ) Is more doped with impurities, but shows a high concentration region (η + layer) of impurities. On the other hand, among the areas A and B, the area covered by the photoresist film 105b (corresponding to the low-concentration impurity regions 103d and 103e) has a low impurity level and does not include impurities. Impurity area (n-layer). In this way, a low-concentration impurity region 103d (n-layer) is formed between the source region 103a (n + layer) and the channel region 103c, and the drain region i03b (n + layer) can be formed. ) A low-concentration impurity region i03e (n-layer) is formed between the channel region 103c and the channel region 103c. In addition, since the gate electrode 105a is used as a mask for the first ion doping, and the photoresist film 105b is used as a mask for the second ion doping, the source region 103a and low-concentration impurities can be incorporated. The regions i03d · 103e and the drain region 103b are formed by self-integration, and can overlap the gate electrode 5 and the source region i03a, and the gate electrode 105 and the drain region 103b. The overlapping portion is suppressed to a small extent without even considering it. This 'Shaw b' forms a thin film transistor with a length of 1 to 1 β 5 μm in the LDD region, and can reduce the OFF current while suppressing the reduction of the ON current as much as possible. (11) Next, an interlayer insulating layer (SiOx) 106 is formed (FIG. 29 (c)). (12) Open the connection holes 109a and 10b next to the interlayer insulation layer 106 and the gate insulation layer 104 (Figure 29 (d)). (13) Fill the connection with a metal layer such as A1 by sputtering. Holes 109a, -40- This paper size applies to China National Standard (CNS) A4 (21〇X 297mm Γ -------- (Please read the precautions on the back before filling this page) ►Installation • Line · 474016 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (38) 10b 'The upper part of the metal layer is patterned into a certain shape to form the source electrode 107 and the drain electrode 108 (section 29 ( e) Figure). TFT101 is made. Although the previous example has described the n-channel TFT, p-channel TFT can also be manufactured by the same manufacturing process. Figure 35 shows the manufacturing method by the aforementioned manufacturing method. The voltage / current characteristics of the thin-film transistor, and the unevenness in the substrate surface of the OFF current is shown in Fig. 36. As shown in Fig. 13 'the graph of the TFT101CL3 of this embodiment 2-1), it will be high The LDD region of the impedance region is as small as 1 to 1.5 μm. Therefore, a stable ON current can be ensured. Small 〇ff current. Of course, if the precision of the alignment is improved, the length of the LDD region can be further reduced. In addition, by increasing the carrier concentration in the n-region, the electric-field-related region becomes smaller. However, on the other hand, the peak value of the electric field becomes higher, which increases the OFF current. Fig. 37 shows the results of simulating the Vg-Id characteristics of the thin film transistor using the concentration of the LDD region as a parameter. The sheet impedance in the LDD region is below 20 kQ / □ and the OFF current is rapidly increased. Therefore, it is necessary to set the sheet impedance of the LDD region to at least 20k Ω / □ or more. On the other hand, when the sheet impedance of the LDD region is set to 100kQ / □ or more, the ON current of the transistor will decrease and the operation of the display panel becomes unstable. Therefore, the range of the sheet impedance in the LDD region is preferably set to be more than 20kQ / □ and less than 100kD / □. In addition, the impurity was initially doped by using a low-speed ion doping method with an acceleration voltage of 10 kV or more and 30 kV or less and a beam current density of 0.05 μA / αη2 or more and 1 μA / cm2 or less. Ion's plus-41- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) --------- I --- install ------ order! !! Wire (Please read the precautions on the back before filling this page) 474016 A7 B7 V. Description of the invention (39) The speed voltage is low, so that the damage during incorporation can be reduced. In addition, the photoresist when it is first impregnated with impurities is used as a mask to prevent the photoresist from being deteriorated and removed cleanly. Or the second impurity doping system uses a high-speed ion doping A with an acceleration voltage and a beam current density of 1 # m / cm2 or more, and the ions can be fully implanted in the second ion doping. # In addition, in the embodiment 2-1, the length L of the LD region constituting the TFT101 is set to be greater than lem and 1.5 / zm, and the Vic between the source and the drain is set to 6V, and the channel width is set to 6 / Under normal conditions, the OFF current depends on the electric field between the source and the drain. The VP '/ Α channel region / LDD region is applied. Therefore, the strength of the electric field is represented by vlC / (Solid State Electron , 38, 2075 (1995)). The intensity of multiple fields is expressed by the following formula. 4 * 106 &lt; Vlc / AL &lt; 6 * 106 OFF The current is proportional to the width of the channel W, so the above ldd area is not the same as the one in the previous section. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of Changyu Guansun Ministry of Economic Affairs △ The LDD area is not the same as the source The inter-electrode voltage of 71 ° can be expressed by the following formula (3). △ L &gt; (W · Vlc) / 36 (3) Next, the meaning of the aforementioned formula (3) will be explained. With the progress of miniaturization of TFTi, the aforementioned values of AL and W will become smaller, and the source-to-drain voltage Vic will decrease with this. Therefore, Table 2 below shows the characteristics of the length AL of the LDD region, the source-drain electrode Vic, and the channel width. (Continued on next page)

42- 4?4〇16 A742- 4? 4〇16 A7

五、發明說明（40 ) 表2 ··V. Description of the invention (40) Table 2 ··

Vic (V) △ L (&quot;m) Vlc/AL W (θ π〇 ff · Vlc/36 3 · (ff/L) ON 電流 OFF 電流 |驗例1 6 1 6 · 106 5 0. 83 1. 25 〇 !驗例2 6 1.5 4 · 106 5 0. 83 1. 25 X 〇 !驗例3 3 0. 5 6 · 106 5 0. 41 1. 25 〇 〇 !驗例4 3 0. 75 4 · ΙΟ6 3 0. 25 0. 75 〇 〇 !驗例5 16 2 3 · ΙΟ6 5 0. 83 1. 25 X 〇 1驗例6 6 0. 5 12 · 106 5 0. 83 1 1. 25 〇 X !驗例7 3 1 3 · ΙΟ6 3 0. 25 0. 75 X 〇 (L = 12 // m、ON電流〇：確保ON電流；OFF電流〇：抑制OFF電流） 經濟部智慧財產局員工消費合作社印製 如表2所示，實驗例1〜5、7(即，滿足前述式子（1)者） 乃能抑制OFF電流，惟，實驗6(即，不滿足前述式子（3)者） 乃不能抑制OFF電流。 又，將前述通道區域之通道寬度設為W的情形下，則LDD 區域之長度ALDD區域與通道區域之通道寬度L與通道寬度 W之關係能以下記式子（4，）表示。 △ L&lt;3 · (W/L)……（4，） 前述式子（4)表示限制ON電流者，而ON電流為藉著與W /L成比例而被導出的條件，ON電流之條件係藉著W/L = 0.5，而ALDD區域在1.5/zm以下減少的實驗結果而被導出 者。而如表1所示一般，滿足前述式子（4)之實驗例1、3、 4、6乃能確保ON電流。 又，比上述式子（4，）更能確保ON電流的條件乃藉著下 述式子（4)而能確保ON電流。 △ L&lt; 1. 5 · (W/L)……(4) 如此一來，於薄膜電晶體之OFF時，前述低濃度不純 物區域乃能達到降低會造成載體枯渴之高阻抗層的OFF電 流。而藉著前述式子（3)能決定LDD區域1之長度的方針， -43- 紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） &quot; ' -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 474016Vic (V) △ L (&quot; m) Vlc / AL W (θ π〇ff · Vlc / 36 3 · (ff / L) ON current OFF current | Examination example 1 6 1 6 · 106 5 0. 83 1. 25 〇! Test example 2 6 1.5 4 · 106 5 0. 83 1. 25 X 〇! Test example 3 3 0. 5 6 · 106 5 0. 41 1. 25 〇! Test example 4 3 0. 75 4 · ΙΟ6 3 0. 25 0. 75 〇〇! Test example 5 16 2 3 · ΙΟ6 5 0. 83 1. 25 X 〇1 Test example 6 6 0. 5 12 · 106 5 0. 83 1 1. 25 〇X! Test example 7 3 1 3 · 10 6 3 0. 25 0. 75 X 〇 (L = 12 // m, ON current 〇: ensure ON current; OFF current 〇: suppress OFF current) The system is shown in Table 2. Experimental Examples 1 to 5, 7 (that is, those satisfying the aforementioned formula (1)) can suppress the OFF current, but Experiment 6 (that is, those not satisfying the aforementioned formula (3)) is The OFF current cannot be suppressed. When the channel width of the aforementioned channel region is set to W, the relationship between the length of the LDD region, the channel width L and the channel width L and the channel width W can be expressed by the following formula (4,) △ L &lt; 3 · (W / L) …… (4,) The aforementioned formula (4) indicates that the ON current is limited, and ON The flow is a condition derived by being proportional to W / L, and the condition of the ON current is derived by the experimental result that W / L = 0.5 and the ALDD region decreases below 1.5 / zm. As shown in Table 1 In general, the ON current can be ensured in Experimental Examples 1, 3, 4, and 6 that satisfy the aforementioned formula (4). The conditions for ensuring the ON current more than the above formula (4,) are as follows. (4) to ensure the ON current. △ L &lt; 1.5 · (W / L) ...... (4) In this way, when the thin film transistor is turned off, the aforementioned low-concentration impurity region can be reduced to cause Off current of the carrier ’s thirsty high-impedance layer. By the above formula (3), the length of the LDD region 1 can be determined. -43- The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) &Quot; '------------- install -------- order --------- line (please read the precautions on the back before filling this page) 474016

而t以不必要確保在降低01^電流之必要上的LDD區域。又 經濟部智慧財產局員工消費合作社印製 一剛述式子（3)藉著更滿足式子（4)而於薄膜電晶體⑽時， 藉由來自閘極電極之電場的作用而使閘極電極下的低濃度 不純物區域蓄積著成為載體的電子而形成低阻抗區域，而 不會造成減少ON電流的情形。爰此，要滿足式子（3)及式 子（4)的薄膜電晶體乃能充分確保〇N電流之同時能能抑制 OFF電流至小。 又’前述通道寬度係以5&quot;m來進行，惟，要微細化通 道區域之通道寬度W而將其設在2//m以下時，前述式子（3) 及式子（4)特別在製作薄膜電晶體時成為有效的方針。 (實施樣態2 — 2) 本實施樣態2 — 2係對於前述實施樣態2 — 1，在形成光 阻膜105b之情形下，並不使用前述合對位置標記而不將ldd 區域之長度設在l#m以上1.5/zm以下，而藉由將滿足y)D 區域之長度為1/zro以上1.5//m以下之條件者視為良品，以 能獲得將LDD區域設在前述範圍内之薄膜電晶體。因此， 在能充分確保ON電流之同時能能抑制OFF電流至小。又， 本實施樣態2 — 2並非將LDD區域設定在l//m以上1. 5#m以 下者，而係能設定在前述實施樣態2—1所說明之式子（3) 、式子（4)的範圍。 (其他事項） 前述實施樣態2—1、2—2之中，雖已說明了具有一種 類濃度之低濃度不純物區域，惟，本發明並非僅限於此， 即使是設置濃度差為不同之多數的低濃度不純物區域那般 情形亦可。即，將低濃度不純物區域朝通道區域藉由連同 -44- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I---.——.----#^i —-----^--------- (請先閱讀背面之注意事項再填寫本頁) 474016 經濟部智慧財產局員工消費合作社印製 A7 、發明說明（42 ) 使不純物濃度呈階段性地降低之多數接合區域的構成而&amp; 以多階段性地變化不純物濃度，因此，能更加緩和在半導 體層之電場的集中。 又’前述低濃度不純物區域亦可僅形成在汲極區域與 通道區域之間，藉著如此構成，在能達到降低〇卯電流等 的效果之同時，亦能弄小薄膜電晶體之面積。而且，如此 的薄膜電晶體亦能適合應用於液晶顯示裝置以外的裝置。 又，在C—MOS反向器電路之p通道薄膜電晶體與n通道 薄膜電晶體之中，至少能以實施樣態2—1、2—2所記載之 薄膜電晶體來構成η通道薄膜電晶體。 【產業上之可利用性】 如上所述，依據本發明即能十足地達到解決本發明所 示之問題。 即’第1發明群乃在充分確保⑽電流之同時，能將照 射光線時之光傳導電流抑制成為小，並降低電力消耗，而 在提昇信賴度及提昇特性上極具大的功效。 又’第2發明群乃在夫供充分確保0N電流之同時，能 將OFF電流抑制成為小，並降低電力消耗，且在提昇信賴 度及提昇特性上極具大功效的薄膜電晶體。 【主要元件標號對照】 1 薄膜電晶體 3 多晶矽層 3a 源極區域 3b 汲極電極 3c 通道區域 -45- — — — — — — — — — — — — — 11 I i — t (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） 474016 經濟部智慧財產局員工消費合作社印製 _B7 3d、3e LDD區域（n —層 4 閘極絕緣層 5a 之閘極電極 6 層間絕緣膜 7 源極電極 8 汲極電極 9a、9b 連接孔 15 a— Si 層 16 多晶石夕層 17 金屬層 18 光阻膜 50 液晶顯示裝置 51 液晶顯示面板部 52 背光部 53、54 偏光板 2、54b 玻璃基板 55 像素電極 56 配向膜 57 液晶層 58 共通電極 A7 五、發明說明（43 ) -46- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）And t does not necessarily ensure the LDD region on the need to reduce the current of 01 ^. Also, the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a formula (3) to satisfy the formula (4), and when the thin film transistor is ⑽, the gate is made by the electric field from the gate electrode. A low-concentration impurity region under the electrode accumulates electrons that become a carrier to form a low-impedance region without causing a reduction in the ON current. Therefore, the thin film transistor that satisfies the expressions (3) and (4) can sufficiently ensure the ON current while suppressing the OFF current to a minimum. The above-mentioned channel width is performed by 5 &quot; m. However, when the channel width W of the channel area is to be miniaturized and set to 2 // m or less, the aforementioned formulas (3) and (4) are particularly It becomes an effective policy when manufacturing thin film transistors. (Embodiment 2-2) This embodiment 2-2 is the same as the foregoing embodiment 2-1, in the case of forming the photoresist film 105b, the aforementioned paired position mark is not used without the length of the ldd area It is set at l # m or more and 1.5 / zm or less, and those who satisfy the condition that the length of y) D area is 1 / zro or more and 1.5 // m or less are considered good products, so that the LDD area can be set within the aforementioned range. Thin film transistor. Therefore, it is possible to suppress the OFF current to a minimum while sufficiently securing the ON current. In addition, the aspect 2-2 of this embodiment does not set the LDD region to 1 // m or more and 1.5 # m or less, but can be set to the formula (3) and the formula described in the foregoing embodiment 2-1. The range of sub (4). (Other matters) Although in the foregoing embodiment 2-1, 2-2, a low-concentration impurity region having a kind of concentration has been described, the present invention is not limited to this, even if the difference in concentration is set to a majority This is also the case for the low-concentration impurity regions. That is, the area of low-concentration impurities is directed toward the channel area together with -44- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I ---.——.---- # ^ i —----- ^ --------- (Please read the precautions on the back before filling out this page) 474016 Printed A7 by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Description of Invention (42) Impurity concentration The structure of the majority of the junction regions that are gradually reduced and the impurity concentration is changed in multiple stages. Therefore, the concentration of the electric field in the semiconductor layer can be more relaxed. In addition, the aforementioned low-concentration impurity region may be formed only between the drain region and the channel region. With this structure, the area of the thin film transistor can be reduced while achieving the effect of reducing the current of 卯. In addition, such a thin film transistor can be suitably applied to a device other than a liquid crystal display device. In addition, among the p-channel thin film transistor and the n-channel thin film transistor of the C-MOS inverter circuit, at least the thin film transistor described in the implementation state 2-1, 2-2 can be used to constitute an η channel thin film transistor. Crystal. [Industrial Applicability] As described above, according to the present invention, it is possible to sufficiently solve the problems shown in the present invention. That is, the "first invention group" is capable of suppressing the photoconductive current when irradiating light to a small size and sufficiently reducing the power consumption, while having sufficient electric current, and is extremely effective in improving reliability and characteristics. In addition, the second invention group is a thin-film transistor which can suppress the OFF current to be small while reducing the power consumption while ensuring sufficient 0N current, and is extremely effective in improving reliability and improving characteristics. [Key component comparison] 1 Thin film transistor 3 Polycrystalline silicon layer 3a Source region 3b Drain electrode 3c Channel region -45- — — — — — — — — — — — — — 11 (Please read the back first Please pay attention to this page, please fill in this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 297 mm) 474016 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs_B7 3d, 3e LDD area (n — layer 4 Gate electrode 5a 6 Gate electrode 6 Interlayer insulating film 7 Source electrode 8 Drain electrode 9a, 9b Connection hole 15 a—Si layer 16 Polycrystalline layer 17 Metal layer 18 Photoresist film 50 Liquid crystal display device 51 Liquid crystal display Panel section 52 Backlight section 53, 54 Polarizing plate 2, 54b Glass substrate 55 Pixel electrode 56 Alignment film 57 Liquid crystal layer 58 Common electrode A7 V. Description of the invention (43) -46- (Please read the precautions on the back before filling this page ) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

474016 as C8 D8 '______ 六、申請專利範圍 1. 一種薄膜電晶體，其特徵在於： 具有通道區域及配置於該通道區域之兩側的源極區域 及沒極區域所形成之多晶石夕半導體層； 前述通道區域與前述汲極區域之間形成有空乏層， 該空乏層之見度與刖述通道區域被光線照射時所發生 之光傳導電流具有比例關係，用以將前述光傳導電流設於 一定容許值内，而將空乏層之寬度設在依據前述比例關係 所求出之值以下的構成。 2. 如申請專利範圍第1項之薄膜電晶體，其中將前述汲極 區一域之薄片阻抗設為R(kQ/[U)，而將前述通道區域 之通i道寬度設為w(/zm)的情形下，滿足式子（1)之關係 :』R+30) · W &lt; A ··· (1)。 3. 如申請專利範圍第2項之薄膜電晶體’其中將前述没極 區域之薄片阻抗設為R(kD/[I])，而將前述通道區域 丨之_道寬度設為W(/zm)的情形下，滿足式子（1)之關係 '魏\ 參:丨(R+30) · W &lt; 1*103 …（2)。 4. 如申請專利範圍第3項之薄膜電晶體，其中將前述通道區 域之通道寬度W為2μπι以下。 5. 如申請專利範圍第3項之薄膜電晶體，其中前述没極區域 之薄片阻抗係於20kQ/□以上，ΙΟΟΙίΩ/□以下。 6. 如申請專利範圍第4項之薄膜電晶體，其中前述沒極區域 之薄片阻抗係於20kQ/□以上，lOOkQ/□以下。 (請先閱讀背面之注意事項再填寫本頁) · n I I ϋ 訂 ----_· 經濟部智慧財產局員工消費合作社印製 -線-φι—u----------Ji — J---- -47 - ^紙張尺度適用中_私楳+ (CNS)A4規格（210 X 297公釐） 474016474016 as C8 D8 '______ 6. Scope of patent application 1. A thin film transistor characterized by having a channel region and a polycrystalline silicon semiconductor formed by a source region and an electrodeless region arranged on both sides of the channel region An empty layer is formed between the channel region and the drain region, and the visibility of the empty layer is proportional to the photoconductive current that occurs when the channel region is illuminated by light, and is used to set the photoconductive current A configuration in which the width of the empty layer is set to a value less than a value obtained based on the foregoing proportional relationship within a certain allowable value. 2. For example, the thin film transistor of the first patent application range, wherein the sheet impedance of the aforementioned drain region is set to R (kQ / [U), and the channel width of the aforementioned channel region is set to w (/ zm), the relationship of expression (1) is satisfied: "R + 30) · W &lt; A ··· (1). 3. For the thin film transistor of item 2 of the patent application, where the sheet impedance of the aforementioned electrodeless region is set to R (kD / [I]), and the channel width of the aforementioned channel region is set to W (/ zm In the case of), the relationship of formula (1) is 'Wei \' Ref: 丨 (R + 30) · W &lt; 1 * 103… (2). 4. For the thin film transistor of item 3 of the patent application, wherein the channel width W of the aforementioned channel region is 2 μm or less. 5. For the thin-film transistor in the third item of the patent application, the sheet impedance of the aforementioned non-polar region is above 20 kQ / □ and below 100 ΙΩ / □. 6. For the thin-film transistor in the fourth item of the patent application, the sheet impedance of the aforementioned non-polar region is above 20kQ / □ and below 100kQ / □. (Please read the notes on the back before filling out this page) · n II ϋ Order ----_ · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-line-φι-u ---------- Ji — J ---- -47-^ Paper size applicable _Private + (CNS) A4 size (210 X 297 mm) 474016 、申請專利範圍 經濟部智慧財產局員工消費合作社印製 7. 一種薄膜電晶體，係具有通道區域；及，於該通道區域之 兩側配置源極區域及汲極區域之多晶矽半導體層，且對於 液晶顯示裝置係作為開關元件者，其特徵在於： 構成前述液晶顯示裝置之背光的輝度設於2000(cd/ m2)以上時，於前述源極區域與前述通道區域之間，或是 月!1述&gt;及極區域與前述通道區域之間至少任何一方，形成不 純物濃度比源極區域及没極區域低的低濃度不純物區域， 該低濃度不純度區域之長度為1.0/zm。 8· —種薄膜電晶體，係具有通道區域；及，形成配置在通 道區域之兩側之源極區域及汲極區域，於前述源極區域 及沒極區域之間，或没極區域與通道區域之間之至少任 何一方，形成不純物濃度係比源極區域及汲極區域低的 低濃度不純物區域之多晶矽半導體層，其特徵在於： 將前述低濃度不純物質區域之長度設於# m)、 將渾極一汲極間的電壓設為Vlc(V)、將前述通道區域 , &gt;卜·..〆ί 之編道寬度設為W(itzm)的情形下，滿足式子（3)的關係 陶 丨獨 dd &gt; (W · Vlc)/36 …（3) : p」 —一~ \ fi： .· · i I. ' .: 9·如申請專利範圍第8項之薄膜老毒雜，其中前述通毕區: ； 域之長度設為L(以m)之情形下，碎足:式子（4)之關係 △ L〈 1.5 · (W/L)…（4)瞭； 误; 10·如申請專利範圍第9項之薄膜電體）其中前述通道^ i ； 域之通道寬度W(//m)在2vm以下 11.如申請專利範圍第9項之薄膜電晶體，其中前述低濃度 -48 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 474016 A8 B8 C8 D8 申請專利範圍 不純物區域之薄片阻抗為□以上，H)〇 ki}/ □以下。 12·如申請專利範圍第1〇項之薄膜電晶體，其中前述低濃 度不純物區域之薄片阻抗為201ίΩ/□以上，1〇0 /□以下。 13.如申請專利範圍帛u項之薄膜電晶體，其中前述低濃 度不純物區域係僅形成在汲極區域與通道區域之間。 14· 一種液晶顯示裝置，係具有將前述申請專利範圍第丨項 之薄膜電晶體作為開關元件的液晶顯示面板部；及，從 裡面側供給光線至前述液晶顯示面板部之背光部之液晶 顯示裝置，其特徵在於： 將前述没極區域之薄片阻抗設為J^kQ/匚])，將 ^述背光部之輝度設為B(cd//m2)，而將前述通道區域 π，道寬度設為W(em)的情形下，滿;^_丨（5)之關係 ，C係依據光傳導電流而設爱 •0).B.W&lt;C …⑸ |V&quot;_ 15.如申請專利範圍第14項之液晶i」顯老裝置1中將前述 汲極區域之薄片阻抗設為將前述背光部 之輝度設為B(cd/m2)，而將前述通道區域A魯道寬度 設為W(//m)的情形下，滿足式子（6丨)之啊係今1 I ：·.、了 \ (6) 16. —種EL裝置，係於形成在具有薄丨蹲電j晶艎變^基板之像 一:^τ，Ι 素電極上層具有發光層，而在該發上層形成對向電 極之EL裝置，其特徵在於：前述薄膜電晶體係前述申 -49 - 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -费--------訂-I-——^----線 1·1!-1 (R+ 30) · B · W &lt; 1 * 1〇6 474016 A8 B8 C8 D8 六 申請專利範圍 請專利範圍第1項記載之薄膜電晶體，將照射該薄膜電 晶體之通道區域之光線強度設為B(cd/m2)的情形下， 滿足式本（5_j的關係，又，C係依據光傳導電流而設定 i Λ':;· i 之定數釦 (R+30&gt; .；B W &lt; C (5)； I» / :: 17·如申請專利範圍第16項之Ei裝/置，其中將前述汲極區 域之薄片阻抗設為R(kQ/b5，％尊:述背光部之輝度 、 丨丨 設為B(cd/m2)，而將前述通道區墒；^道寬度設為w( 的情形下，滿足式子（6)之關係丨就: (R+30) · Β · W &lt; 1*106 …_ ❹ 經 濟、 部 智 慧 財 產 局 員 工- 消 費 合- 作 社 印 製 18· 一種薄膜電晶體之製造方法，其特徵在於〔包音|有： 多晶矽半導體層形成步驟，係於絕緣了&amp;基板上形成 多晶矽半導體層； 閘極絕緣膜形成步驟，係於前述多晶矽半導體層上 形成閘極絕緣膜； 閘極電極形成步驟，係於前述閘極絕緣膜上將閘極 形成圖樣狀； 陽極氧化步驟，係將前述閘極電極之側面予以氧化 而形成用以包覆該閘極電極之側面之金屬氧化膜；及 不純物摻入步驟，係對前述多晶石夕半導體層將前述 閘極電極作為遮罩而摻入不純物； 且抑制前述陽極氧化步驟中所形成之金躲化膜的 膜厚而將前述不純物摻入步驟中所形成之低濃度不純物 區域之長度AL設為i.0//m以下。Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 7. A thin film transistor with a channel region; and a polycrystalline silicon semiconductor layer with a source region and a drain region on both sides of the channel region, and A liquid crystal display device is used as a switching element, and is characterized in that when the brightness of the backlight constituting the liquid crystal display device is set to 2000 (cd / m2) or more, between the source region and the channel region, or month! 1 As described above, at least one of the polar region and the channel region forms a low-concentration impurity region having a lower impurity concentration than the source region and the non-polar region, and the length of the low-concentration impurity region is 1.0 / zm. 8 · A thin film transistor having a channel region; and forming a source region and a drain region arranged on both sides of the channel region between the source region and the non-polar region, or between the non-polar region and the channel At least one of the regions forms a polycrystalline silicon semiconductor layer of a low-concentration impurity region having an impurity concentration lower than that of the source region and the drain region, wherein the length of the aforementioned low-concentration impurity region is set to # m), In the case where the voltage between the squiggly pole and the drain pole is set to Vlc (V), and the channel width is set to W (itzm), the formula (3) is satisfied. Relationship Tao 独 dd &gt; (W · Vlc) / 36… (3): p ″ —a ~ \ fi:. · · I I. '.: 9 · As in the case of the patent application No. 8 film old poison , Where the aforementioned complete zone:; the length of the domain is set to L (in m), broken foot: the relationship of the formula (4) △ L <1.5 · (W / L) ... (4) is wrong; 10. The thin film electric body as in item 9 of the scope of patent application) wherein the aforementioned channel ^ i; the channel width W (// m) of the domain is below 2 vm 11. The thin film transistor around item 9, in which the aforementioned low concentration -48-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- pack- ------- Order --------- Line (Please read the precautions on the back before filling this page) 474016 A8 B8 C8 D8 The impedance of the sheet in the area of the impurity applied for patent application is □ or more, H) 〇ki} / □ or less. 12. If the thin film transistor of item 10 of the scope of patent application, the sheet impedance of the aforementioned low-concentration impurity region is 201 201 / □ or more and 100 / □ or less. 13. The thin film transistor according to item (u) of the patent application, wherein the aforementioned low-concentration impurity region is formed only between the drain region and the channel region. 14. A liquid crystal display device, which is a liquid crystal display panel portion having a thin film transistor as the switching element in the aforementioned patent application; and a liquid crystal display device that supplies light from a back side to a backlight portion of the liquid crystal display panel portion. , Characterized in that the sheet impedance of the aforementioned non-polar region is set to J ^ kQ / 匚]), the brightness of the backlight section is set to B (cd // m2), and the channel region π and the channel width are set In the case of W (em), the relationship of ^ _ 丨 (5), C is based on the light conduction current • 0). B.W &lt; C… ⑸ | V &quot; _ 15. If the scope of patent application In the liquid crystal i '' display device 1 of item 14, the sheet impedance of the aforementioned drain region is set to the luminance of the aforementioned backlight portion as B (cd / m2), and the width of the channel region A is set to W ( // m), which satisfies the formula (6 丨), which is now 1 I: ·. ,, and (6) 16. A kind of EL device, which is formed in a thin film ^ Image one of the substrate: ^ τ, Ι EL device with a light emitting layer on the upper layer of the electrode, and an EL device forming a counter electrode on the upper layer of the electrode, which is characterized by: -49-Private paper size applies to China National Standard (CNS) A4 (210 X 297 Public Love) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- Fee -------- Order-I ----- ^ ---- Line 1.1 · -1 (R + 30) · B · W &lt; 1 * 106 474016 A8 B8 C8 D8 Six patent applications For the range, please refer to the thin film transistor described in item 1 of the patent scope. When the light intensity irradiating the channel region of the thin film transistor is set to B (cd / m2), the formula (5_j relationship is satisfied, and C is based on I Λ ':; · i fixed number buckle (R + 30 &gt;.; BW &lt; C (5); I »/ :: 17 Where the sheet impedance of the aforementioned drain region is set to R (kQ / b5,% z: the brightness of the backlight, and 丨 丨 is set to B (cd / m2), and the aforementioned channel region 墒 is set to ^; the channel width is set to In the case of w (, the relationship of formula (6) is satisfied 丨 just: (R + 30) · Β · W &lt; 1 * 106… _ ❹ Employees of the Ministry of Economy and Intellectual Property Bureau-Consumption Cooperation-Printed by the Agency 18 · A kind of thin The manufacturing method of a transistor is characterized in that [including sounds include: a step of forming a polycrystalline silicon semiconductor layer, forming a polycrystalline silicon semiconductor layer on an insulated substrate; and a step of forming a gate insulating film, forming a gate on the aforementioned polycrystalline silicon semiconductor layer Gate insulating film; the gate electrode forming step is to form the gate electrode on the gate insulating film; the anodizing step is to oxidize the side of the gate electrode to form a gate electrode to cover the gate electrode; A metal oxide film on the side; and an impurity-doping step, wherein the impurity is doped with the gate electrode as a mask to the polycrystalline silicon semiconductor layer; and a film that suppresses the gold dodging film formed in the anodizing step The length AL of the low-concentration impurity region formed in the aforementioned impurity incorporation step is set to be i.0 // m or less. -50 - -------------裝--------訂·！！！ ·線 (請先閱讀背面之注意事項再填寫本頁) A8 B8 C8 D8 474016 六、申請專利範圍 19. 一種薄膜電晶體之製造方法，其特徵在於包含有： 多晶矽半導體層形成步驟，係於絕緣性基板上形成 多晶碎半導體層； 閘極絕緣膜形成步驟，係於前述多晶矽半導體層上 形成閘極絕緣膜； 閘極電極形成步驟，係於前述閘極絕緣膜上將閘極 形成圖樣狀； 第1不純物摻入步驟，係對前述多晶矽半導體層將 前述閘極電極作為遮罩而推入不純物； 遮蔽膜形成步驟，係於摻入不純物之半導體區域上 形成遮蔽膜，且藉著使該遮蔽膜呈異方性而形成圖樣狀 ;及 第2不純物摻入步驟，係對前述多晶矽半導體層將 前述遮蔽膜作為遮罩而摻入不純物，使遮蔽膜之下部區 域與其以腓外之區域存在不純物濃度差而於源極電極與 通道區域之間，或汲極區域與通道區域之間之至少任何 一方形成不純物濃度比源極區域及汲極區域低的低濃度 不純物區域，並將該低濃度不純物區域之長度設在1.0 // m以下。 20. 如申請專利範圍第19項之薄膜電晶體之製造方法，其 中更包含前述低濃度不純物區域之長度AL在1.0/zm 以下則設定為良品之檢查步驟。 -51 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 I· I ϋ ϋ ϋ H ϋ ϋ · I I ϋ ϋ ϋ ϋ ϋ I I ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ^1 ϋ ϋ ϋ ϋ ϋ ϋ I ϋ ϋ ϋ ϋ ·-50-------------- Install -------- Order! !! !! · Wire (please read the precautions on the back before filling this page) A8 B8 C8 D8 474016 6. Application for patent scope 19. A method for manufacturing a thin film transistor, which comprises: a polycrystalline silicon semiconductor layer forming step, which is based on insulation A polycrystalline broken semiconductor layer is formed on a flexible substrate; a gate insulating film forming step is to form a gate insulating film on the aforementioned polycrystalline silicon semiconductor layer; a gate electrode forming step is to form a gate pattern on the aforementioned gate insulating film The first impurity impurity incorporation step is to push the aforementioned gate electrode as a mask into the impurity in the polycrystalline silicon semiconductor layer; the masking film forming step is to form a masking film on the semiconductor region into which the impurity is doped, and by making the The masking film is anisotropic to form a pattern; and the second impurity incorporation step is to incorporate the aforementioned masking film as a mask and impure impurities in the polycrystalline silicon semiconductor layer, so that the lower region of the masking film and its region outside the perone exist. Impurity concentration difference between at least any of the source electrode and the channel region, or between the drain region and the channel region Forming a low concentration side is lower than the impurity concentration of the source region and drain region of the impurity region, and the low-concentration impurity region of the length thereof provided 1.0 // m or less. 20. If the thin-film transistor manufacturing method according to item 19 of the patent application scope further includes the length AL of the aforementioned low-concentration impurity region below 1.0 / zm, it is set as a good product inspection step. -51-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I · I ϋ ϋ ϋ H ϋ II · II ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ^ 1 ϋ ϋ ϋ ϋ ϋ ϋ I ϋ ϋ ϋ ϋ ·
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