WO2001056081A1 - Dispositif de connexion par bossage - Google Patents

Dispositif de connexion par bossage Download PDF

Info

Publication number
WO2001056081A1
WO2001056081A1 PCT/GB2001/000335 GB0100335W WO0156081A1 WO 2001056081 A1 WO2001056081 A1 WO 2001056081A1 GB 0100335 W GB0100335 W GB 0100335W WO 0156081 A1 WO0156081 A1 WO 0156081A1
Authority
WO
WIPO (PCT)
Prior art keywords
bump
substrate
layer
under
solder
Prior art date
Application number
PCT/GB2001/000335
Other languages
English (en)
Inventor
Giles Humpston
David John Warner
James Hugh Vincent
Original Assignee
Bookham Technology Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bookham Technology Plc filed Critical Bookham Technology Plc
Publication of WO2001056081A1 publication Critical patent/WO2001056081A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01021—Scandium [Sc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01043—Technetium [Tc]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Definitions

  • the invention relates to a flip-chip bonding arrangement, a flip-chip bonded circuit arrangement incorporating such a flip-chip bonding arrangement, a method for providing a flip-chip bonding arrangement and a method for the flip-chip bonding of two substrates.
  • Flip-chip bonding is one of a number of known methods of interconnecting two electronic components or circuits, another method being, for example, tape automated bonding.
  • Flip-chip bonding basically involves the application of an "under-bump" metal to the surface to be bonded and the subsequent application of a pillar or sphere of an "interconnect metal" (so-called “bumps") onto the under-bump metal.
  • an "under-bump” metal to the surface to be bonded
  • a pillar or sphere of an "interconnect metal” so-called "bumps”
  • One of the components may lack the bumps, in which case it is simply provided with bond pads for mating with the bumps on the other component.
  • FIG. 1 Such a situation is shown in Figure 1, in which an electronic chip 10 is seen to be provided with an array of hemispherical bumps 12 on its mating side, while a substrate 14 on which the chip is to be mounted has a corresponding array of bonding pads 16 connected to respective interconnection tracks 18.
  • the connection between the chip and the substrate is made either by heating so as to melt the interconnect metal of the bumps or by pressing the two components together to form a cold compression weld.
  • the former is termed "solder-bump bonding”
  • the latter is known as “indium-bump bonding” due to the common use of indium as the interconnect metal in that case.
  • Flip-chip technology is commonly used in the manufacture of, e.g., pixel detector arrays, and in the attachment of ball-grid array (BGA) packages to printed-circuit boards (PCBs) and, more recently, in the assembly and attachment of some forms of chip-scale package (CSP).
  • BGA ball-grid array
  • PCBs printed-circuit boards
  • CSP chip-scale package
  • flip-chip bump bonds are inherently short and squat and are thereby ideally suited for interconnects at microwave frequencies.
  • the series inductance of a bump bond can be as much as a thousand times smaller than that of a ware or tape interconnect, making this technology indispensable for, for example, the recently released 77GHz automotive band and the 124GHz imaging band.
  • the active component of most microwave circuits is a gallium arsenide (GaAs) semiconductor chip, often in the form of a monolithic microwave integrated circuit (MMIC). All of the active circuitry on an MMIC is on one face of the chip, referred to as the top or active face or side
  • An MMIC is designed to function with a substantial thickness of dry air or inert gas over the circuitry. If an MMIC is to be mounted on a substrate by flip-chip interconnection, this necessitates placing the chip upside down with its active face toward the substrate. Therefore control of the stand-off gap between the MMIC and the substrate is an essential prerequisite for successful operation at microwave frequencies. As a general guide, this gap needs to be a minimum of 35 ⁇ m and preferably much larger.
  • US 4466635 as shown with reference to Figures 2a-2c, discloses an interconnect bump 20 for flip-chip bonding which includes an integral stand-off.
  • the interconnect bump comprises a stand-off in the form of a cylindrical column 22 of copper which is bonded to a solder wettable metal pad 24 on a substrate 26.
  • the pad 24 has a diameter greater than that of the column such that a peripheral portion 24a extends laterally and externally of the cylindrical stand-off 26.
  • a solder cap 28 is formed on an upper surface of the stand-off 22 and has a peripheral portion 28a that extends laterally and externally of the stand-off. During flip-chip bonding the solder cap 28 melts over and coats the outer surface of the stand-off ( Figure 2b).
  • solder Due to surface tension the solder forms a generally hourglass shape over the outer surface of the stand-off as it bonds to the peripheral portion of the pad 24 and a corresponding solder wettable pad 30 on the device/circuit 32 being bonded.
  • an interconnect bump provides a predetermined stand-off it requires a relatively large volume of interconnect metal to achieve stand-off distances of any size which in itself causes problems during bonding.
  • a flip-chip bonding arrangement for bonding a first and second substrate comprises one or more metal under-bump portions attached to the first substrate and corresponding bump portions of an interconnecting metal attached to the surface of the under-bump portions remote to the first substrate, characterised in that sides of the under-bump portions are non-wettable by the interconnecting metal and wherein the height of the under-bump portion substantially determines the overall separation between the first and second substrates when the two are bonded.
  • the under-bump portions have a height of at least lO ⁇ m and preferably a height of at most 1 OO ⁇ m.
  • the height of the bump portions is less than or equal to a width of the under-bump portions.
  • the first substrate comprises a tile.
  • it can comprise an electronic device to be attached to a tile.
  • the under-bump portions comprise a seed layer and an overlying layer, the overlying layer being metallurgically compatible with the seed layer and the bump layer.
  • the bump portions are a composition selected from a group consisting of lead/tin, gold/tin and indium.
  • a flip-chip bonded circuit arrangement comprises a flip-chip bonding arrangement as described above and an electronic device mounted to said tile by way of said flip-chip bonding arrangement.
  • the electronic device is a GaAs monolithic microwave integrated circuit or an opto-electronic device.
  • a method for providing a flip-chip bonding arrangement on a substrate having one or more bond pads comprises the steps of: a) depositing a seed layer of conductive metal on the substrate; b) depositing a layer of photoresist on the substrate; c) providing in the photoresist layer respective openings above the pads; d) depositing into the openings an under-bump layer which will adhere to the seed layer and also be metallurgically compatible with a bump layer to be applied; e) depositing into the openings and onto the under-bump metal the bump layer, and f) removing the excess photoresist and seed layers.
  • step (d) and/or step (e) is achieved by way of an electroplating process.
  • the seed layer is composed of gold and the under-bump metal is selected from a group consisting of nickel, copper, gold and silver.
  • a width dimension of the under-bump layer is substantially equal to that of its corresponding bond pad.
  • the method further includes following step (f) and prior to mounting a second substrate on the bumps of the first substrate, a step (g): depositing a thin layer of gold onto the bump surfaces.
  • the thin layer of gold has a thickness less than that of the removed seed layer and advantageously has a thickness of between approximately 0.1 ⁇ m and 0.2 ⁇ m.
  • the bumps are solder-bumps for solder-interconnection to the further substrate and the interconnection operation is performed without flux in an atmosphere denuded of oxygen and water vapour.
  • the atmosphere in which the interconnection operation is performed contains dry nitrogen.
  • the bump layer is deposited as at least two separate layers to form a multi-layer structure and, between steps (f) and (g), a flux is applied to the multi-layer structure, the layers are melted to create an alloy and flux residues are cleaned away.
  • a method for the flip-chip bonding of a first substrate to a second substrate comprises the steps of:
  • solder-bumps depositing on the solder-bumps a thin layer of gold; (c) bringing the solder-bumps of the first substrate into substantial alignment and into contact with the contact means of the second substrate, and (d) without the application of a flux to either the solder-bumps or the contact means, raising the temperature of the solder-bumps so that a solder interconnection is made between the bumps and the contact means.
  • Figure 1 illustrates the mating of a conventional flip-chip electronic device to a substrate
  • Figure 2a-2c are schematic sectional representations of a known flip-chip bonding process which includes an integral stand-off;
  • Figure 3 a and 3b are schematic sectional representations of a flip-chip bonding process in accordance with the invention.
  • Figure 4 is a diagram showing part of an MMIC
  • FIGS 5a-5g depict the processing steps involved in manufacturing the under-bump portion and interconnect in accordance with the invention.
  • the under bump metal is not a single metal but a sequence of up to three metals.
  • the first metal is called the "adhesion metal" and its role is to provide an ohmic contact and strong physical bond to the surfaces to be joined.
  • the choice of adhesion metal varies with the nature of the components being joined and the method of deposition. Common examples are titanium and chromium, if applied by a vapour phase technique, and zinc if applied by wet plating.
  • the second metal is the "barrier metal” that is included to prevent metallurgical reaction between the adhesion metal and the interconnect metal.
  • barrier metal is extremely wide and includes both pure elements such as platinum, nickel and copper and mixtures of metals like titanium- tungsten. Finally, it is common practice to complete the under-bump metal with a "sacrificial metal" (often gold) which serves to improve shelf-life and wetting and/or aid visual inspection.
  • the under-bump metal is always thin, most usually less than l ⁇ m thick.
  • the interconnect metal applied on top of the under-bump metal that provides the stand-off height through being made sufficiently thick.
  • the present invention substantially increases the thickness (i.e. height above the surface of the substrate) of the under-bump portion to as much as lOO ⁇ m and applies only a small (relative to the conventional arrangement) thickness of interconnect metal on top.
  • the stand-off gap is mostly provided by the thick under-bump metal, while the interconnect diameter and pitch can be independently optimised by the geometry of the interconnect metal.
  • the bonding arrangement comprises a cylindrical metal under-bump 44 which comprises in order from the surface of the substrate 40, an adhesion metal layer 46, a metal barrier layer 48 and a sacrificial metal layer 50.
  • the barrier layer 48 is much thicker than the other two layers 46, 50 and is made of a material which is not wettable by the interconnect metal.
  • an interconnect metal bump 52 which is typically generally hemispherical in shape.
  • the barrier layer 48 which will hereinafter be referred to as spacing metal, substantially determines the stand-off gap between the substrate 40 and MMIC 42 when the two are bonded.
  • the volume of the interconnect metal bump 52 is selected such that when the substrate 40 and MMIC 42 are bonded together ( Figure 3b) there is sufficient to provide a good bond between the sacrificial layer 50 a corresponding wettable pad 54 though as will be seen from the Figure the stand-off is primarily determined by the height of the layer 48.
  • the spacing member is made of a material which is non wettable there is no flow of the interconnect metal down the sides of the under-bump 44.
  • a typical implementation of the process is the attachment of a GaAs MMIC to an alumina tile.
  • the GaAs MMIC (see Figure 4) will have two types of track, namely RF tracks (ground-signal-ground) 60 and DC tracks (power-line and bias) 62. (Only two of the latter type are shown.) These tracks terminate in respective exposed gold bond pads 64 which are suitable for wire bonding.
  • the bumps on the tile are positioned so as to mate with the pads 64 on the MMIC.
  • the RF pads are typically lOO ⁇ m square on a 150 ⁇ m pitch for the ground-signal-ground microwave connections.
  • the alumina tile (not shown in Figure 4) will have a polished surface onto which have been deposited gold tracks to route microwave signals, power and control lines to the MMIC.
  • These are all industry-standard presentations.
  • the interconnect process to be described can in fact be applied to any substrate, including silicon wafers with standard aluminium bond pads, provided that the bond pads are converted to expose a gold finish. This is dealt with later. Suffice it to say that many methods are available for achieving this and are known to those skilled in the art.
  • the under-bump and interconnect metals are applied to the alumina (Al 2 O 3 ) tile rather than to the MMIC, for reasons that will be elaborated upon later.
  • a thin layer of conductive metal 70 is first deposited over the entire tile 72.
  • Gold (Au) is the preferred choice for the seed metal as it will form a homogeneous bond with the existing gold tracks 74 and pads 76.
  • This gold layer 70 needs to be of just sufficient thickness to ensure uniform current distribution during the following electroplating processes. Methods for calculating a suitable thickness are well established and will not be elaborated here.
  • the gold layer 70 will likely be in the region of 0.5 ⁇ m thick and is preferably deposited by a vapour phase method.
  • a thick layer of photoresist 78 (see Figure 5b) is then applied to the tile 72 and is exposed and developed in accordance with the manufacturers' directions.
  • the objective of this process step is to coat the surface of the tile with an inert material that has near- vertical openings 80 through to the gold layer at desired locations, e.g. over the pad 76 connected to the track 74.
  • the location of the openings 80 (only one is shown in Figures 5b-5e) will mirror the openings of the bond pads on the MMIC (not shown).
  • the depth of the openings i.e. the thickness of the photoresist
  • the diameter of the openings will fix the diameter of the under-bump metal and will also have an influence on the diameter of the final interconnects, as will be explained shortly.
  • Nickel, copper or other metallurgically compatible metal 82 is then deposited by electroplating down the openings 80 using commercially available chemical solutions (Figure 5c).
  • This "spacing" metal 80 is ideally selected to provide the dual functions of the adhesion metal and the barrier metal but, if necessary, layers of different metals can be used to perform the required functions.
  • Nickel is a good first choice as it is compatible with the lead/tin and gold/tin solders commonly used as well as with indium interconnects.
  • the thickness of the spacing metal 80 should be such as to provide a significant proportion of the overall desired stand-off height, and preferably the majority of it, the remainder being provided by the thickness of the interconnect metal that will be deposited next.
  • the interconnect metal which in Figures 5d and 5e comprises a layer 84 of gold followed by a layer 86 of tin (Sn).
  • the interconnect metal is preferably deposited by electroplating, though other methods may be employed, such as thermal evaporation.
  • Lead/tin solder and indium can be deposited from a single plating solution as a single layer, whereas other solders must be deposited as a bi- or tri-layer of the constituent elements.
  • the relative thicknesses of gold 84 and tin 86 are selected so that, on melting, the composition of the melt conforms to the required 80 wt% gold 20 wt% tin eutectic composition. Because the gold/tin solder is metallurgically compatible with the gold bond pads on MMICs, this solder is the preferred choice for flip-chip solder interconnection of microwave components. Indium is the preferred choice for flip-chip compression interconnection for the same reason.
  • the photoresist 78 and gold seed 70 layers are then removed (Figure 5f) using standard chemical treatments.
  • the alumina tile 72 is then heat treated such that the one or more interconnect metal layers 84, 86 melt to form an interconnect metal bump 52 on the upper surface of the spacing metal 82 ( Figure 5g).
  • the overall thickness of the interconnect metal layer/s 46, 48 determines the volume and so height of the interconnect solder or compression bump 52.
  • the interconnect bump will have a height and diameter which exceeds the spacing member.
  • the diameter of the spacing metal should ideally match the diameter of the bond pad on the MMIC and the thickness of the interconnect metal layer/s should not exceed this dimension. For solder interconnects, this is the optimum thickness, as it maximises the surface-area-to- volume ratio.
  • the spacing metal 82 can be arranged to be of larger or even smaller diameter than the bump, if desired, although if it is too small, the mechanical stability of the structure is compromised.
  • the interconnect metal should be as thin as possible, compatible with process requirements, in order to minimise lateral spread of the interconnect beyond the profile of the spacing metal when bonding occurs.
  • interconnects 44 i.e. interconnect bumps 84, 86 plus spacing metal 82
  • interconnect bumps 84, 86 plus spacing metal 82 are provided which are taller and narrower than usual and consequently exhibit a superior microwave performance.
  • Flip-chip interconnection of the MMIC to the alumina tile can then be made in the conventional manner.
  • a particular advantage of the interconnect arrangement of the present invention is that the stand-off is substantially determined by the spacing metal portion of the under-bump and is largely independent of the volume of the solder bump.
  • the MMIC bond pads are surrounded by an anti scratch coating which acts to constrain the solder interconnect on the substrate to the MMIC bond pad. If the interconnect metal were applied to the MMIC, then a solder stop would have to be applied to the alumina tile and this would require an additional process step for that component, which would increase cost. Hence the alumina tile is the preferred component for the application of the spacing and interconnect metals. An advantageous spin-off of this is that completely standard MMICs can be used, rather than ones which have to be specially processed.
  • the novel technique herein proposed is to take the alumina tile and, immediately after removal of the photoresist and gold seed layer, coat all metallic surfaces with a thin layer of gold. This is simply achieved using a standard immersion plating process.
  • the gold deposit is essentially self-limiting in thickness (typically not exceeding O.l ⁇ m thick).
  • This additional gold forms a homogeneous bond with all the exposed gold tracks.
  • On the solder-bump this newly applied gold due to the noble character of this element, restricts contact between the solder and air and thereby greatly diminishes the oxidation that can occur.
  • the reduction in the propensity for oxidation is such that flip-chip interconnects can be formed without flux for up to three months after fabrication of the alumina tile.
  • the solder is melted to form the interconnect, the gold completely and rapidly dissolves in the solder. This means that the joint is best made in an atmosphere denuded of oxygen and water vapour.
  • a suitable atmosphere is dry nitrogen of industrial quality.
  • the substrate on which the spacing metal and interconnect metal are to be applied does not already have gold bond pads, e.g. it may have aluminium pads, it will be necessary to make a conversion to gold.
  • This may be done using a conventional under- bump metal process as described earlier and would involve, firstly, applying a photolithographic mask to the substrate with a pattern corresponding to that of the bond- pad layout; secondly, depositing a layer of titanium, followed by a layer of platinum, finally followed by a layer of gold, all of which are preferably carried out using the vapour-phase technique. Finally, the mask is removed, leaving a substrate which can be processed as described above to produce the required spacing- and interconnect-metal thicknesses.
  • the invention is not restricted to the bonding of MMICs to substrates.
  • Other electronic devices may be bonded as well, including optical devices. It is, however, necessary that the devices have bond pads finished in a metal for which a compatible seed is available.

Abstract

L"invention concerne un dispositif de connexion par bossage servant à connecter un composant électronique, par exemple un circuit intégré monolithique hyperfréquence à l"arséniure de gallium, à un substrat. Le substrat comprend, de préférence, une série de bossages de soudure et des bases de bossages, ces dernières étant plus épaisses et les bossages de soudure étant plus minces et plus étroits que dans les dispositifs de connexion classiques, permettant ainsi d"obtenir une plus grande efficacité hyperfréquence. Les bases de bossage plus épaisses sont obtenues par un procédé consistant à appliquer une couche de germe cristallin au-dessus d"une couche d"or existante sur les plots de connexion du substrat, à appliquer une photorésine sur la couche de germe cristallin avec des fenêtres définissant les sites d"interconnexion de bossage, et à déposer dans les fenêtres une épaisse couche de nickel par exemple (allant, par exemple, jusqu"à 100 microns), puis le métal de bossage, celui-ci pouvant être du plomb/étain, de l"indium ou de l"or/étain. Le procédé consiste enfin à enlever la réserve et la couche de germe cristallin. L"invention concerne également un procédé de soudage par bossage sans fondant selon lequel, suivant le procédé de fabrication mentionné ci-dessus, toutes les surfaces métalliques sont recouvertes d"une mince couche d"or. Le soudage postérieur d"un composant au substrat provoque ensuite la dissolution de la mince couche d"or dans la soudure.
PCT/GB2001/000335 2000-01-27 2001-01-26 Dispositif de connexion par bossage WO2001056081A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0001918.2 2000-01-27
GBGB0001918.2A GB0001918D0 (en) 2000-01-27 2000-01-27 Flip-chip bonding arrangement

Publications (1)

Publication Number Publication Date
WO2001056081A1 true WO2001056081A1 (fr) 2001-08-02

Family

ID=9884479

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2001/000335 WO2001056081A1 (fr) 2000-01-27 2001-01-26 Dispositif de connexion par bossage

Country Status (2)

Country Link
GB (2) GB0001918D0 (fr)
WO (1) WO2001056081A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387402A2 (fr) * 2002-07-15 2004-02-04 Texas Instruments Incorporated Procédé de fabrication au niveau de la plaquette d' une interconnexion de puces à pas fin et à haut facteur d'aspect
WO2004042819A1 (fr) * 2002-11-06 2004-05-21 Koninklijke Philips Electronics N.V. Dispositif comprenant des elements de circuit relies par une structure de liaison en forme de bosse
EP1536469A1 (fr) * 2003-11-28 2005-06-01 EM Microelectronic-Marin SA Dispositif à semi-conducteur avec plots de connexion
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
WO2005093816A1 (fr) * 2004-03-05 2005-10-06 Infineon Technologies Ag Semi-conducteur pour applications rf et son procede de fabrication
WO2006043235A1 (fr) * 2004-10-20 2006-04-27 Koninklijke Philips Electronics N.V. Substrat comprenant des contacts electriques et procede de fabrication de celui-ci
CN102881607A (zh) * 2012-09-27 2013-01-16 中国科学院长春光学精密机械与物理研究所 一种新型焦平面阵列电互连工艺
US9806043B2 (en) 2016-03-03 2017-10-31 Infineon Technologies Ag Method of manufacturing molded semiconductor packages having an optical inspection feature

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388933A2 (fr) * 1989-03-23 1990-09-26 Hughes Aircraft Company Plots de contact en indium reliés par alliage et leurs procédés de fabrication
EP0602328A2 (fr) * 1992-11-17 1994-06-22 Fujitsu Limited Structure d'interconnexion pour relier un circuit intégré à un substrat
EP0708481A2 (fr) * 1994-10-20 1996-04-24 Hughes Aircraft Company Bosses thermiques améliorées pour circuits intégrés monolithiques de haute puissance du type flip chip et procédé de fabrication
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993515A (en) * 1975-03-31 1976-11-23 Rca Corporation Method of forming raised electrical contacts on a semiconductor device
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
US5192835A (en) * 1990-10-09 1993-03-09 Eastman Kodak Company Bonding of solid state device to terminal board
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
US5790377A (en) * 1996-09-12 1998-08-04 Packard Hughes Interconnect Company Integral copper column with solder bump flip chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388933A2 (fr) * 1989-03-23 1990-09-26 Hughes Aircraft Company Plots de contact en indium reliés par alliage et leurs procédés de fabrication
EP0602328A2 (fr) * 1992-11-17 1994-06-22 Fujitsu Limited Structure d'interconnexion pour relier un circuit intégré à un substrat
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
EP0708481A2 (fr) * 1994-10-20 1996-04-24 Hughes Aircraft Company Bosses thermiques améliorées pour circuits intégrés monolithiques de haute puissance du type flip chip et procédé de fabrication
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
EP1387402A2 (fr) * 2002-07-15 2004-02-04 Texas Instruments Incorporated Procédé de fabrication au niveau de la plaquette d' une interconnexion de puces à pas fin et à haut facteur d'aspect
EP1387402A3 (fr) * 2002-07-15 2013-09-04 Texas Instruments Incorporated Procédé de fabrication au niveau de la plaquette d' une interconnexion de puces à pas fin et à haut facteur d'aspect
WO2004042819A1 (fr) * 2002-11-06 2004-05-21 Koninklijke Philips Electronics N.V. Dispositif comprenant des elements de circuit relies par une structure de liaison en forme de bosse
EP1536469A1 (fr) * 2003-11-28 2005-06-01 EM Microelectronic-Marin SA Dispositif à semi-conducteur avec plots de connexion
WO2005093816A1 (fr) * 2004-03-05 2005-10-06 Infineon Technologies Ag Semi-conducteur pour applications rf et son procede de fabrication
US8610266B2 (en) 2004-03-05 2013-12-17 Infineon Technologies Ag Semiconductor device for radio frequency applications and method for making the same
WO2006043235A1 (fr) * 2004-10-20 2006-04-27 Koninklijke Philips Electronics N.V. Substrat comprenant des contacts electriques et procede de fabrication de celui-ci
CN102881607A (zh) * 2012-09-27 2013-01-16 中国科学院长春光学精密机械与物理研究所 一种新型焦平面阵列电互连工艺
US9806043B2 (en) 2016-03-03 2017-10-31 Infineon Technologies Ag Method of manufacturing molded semiconductor packages having an optical inspection feature
US10431560B2 (en) 2016-03-03 2019-10-01 Infineon Technologies Ag Molded semiconductor package having an optical inspection feature

Also Published As

Publication number Publication date
GB0001918D0 (en) 2000-03-22
GB0102085D0 (en) 2001-03-14
GB2364172A (en) 2002-01-16

Similar Documents

Publication Publication Date Title
EP0398485B1 (fr) Procédé de formation d'une structure de soudure flip-chip pour dispositifs avec métallisation d'or
KR100514230B1 (ko) 범프의 형성방법 및 반도체장치의 제조방법
JP3300839B2 (ja) 半導体素子ならびにその製造および使用方法
US4922322A (en) Bump structure for reflow bonding of IC devices
TW586159B (en) Method of providing metallurgy or bonding structures for input/output pads of an electronic device, and electronic device
US6013572A (en) Methods of fabricating and testing silver-tin alloy solder bumps
US5698465A (en) Process for manufacturing an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5208186A (en) Process for reflow bonding of bumps in IC devices
US4463059A (en) Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
US7098126B2 (en) Formation of electroplate solder on an organic circuit board for flip chip joints and board to board solder joints
JP3201957B2 (ja) 金属バンプ、金属バンプの製造方法、接続構造体
US6251501B1 (en) Surface mount circuit device and solder bumping method therefor
KR100482721B1 (ko) 배선 기판 및 그 제조 방법, 반도체 장치 및 그 제조방법, 및 전자 기기
US7906425B2 (en) Fluxless bumping process
US20040007779A1 (en) Wafer-level method for fine-pitch, high aspect ratio chip interconnect
JP5064632B2 (ja) 相互接続構造を形成するための方法及び装置
US5985692A (en) Process for flip-chip bonding a semiconductor die having gold bump electrodes
WO2001056081A1 (fr) Dispositif de connexion par bossage
JPH04133330A (ja) 半導体装置およびその接続方法
JPH09205096A (ja) 半導体素子およびその製造方法および半導体装置およびその製造方法
JP3407839B2 (ja) 半導体装置のはんだバンプ形成方法
JPH038556A (ja) 集積回路のコンタクト及びはんだ接着方法
JPH03218644A (ja) 回路基板の接続構造
JPH07321114A (ja) 半導体装置のハンダバンプ形成の方法および構造
JPH03200343A (ja) 半田バンプの形成方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP