Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
  • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
  • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2

Definitions

• This invention relates generally to semiconductor fabrication, and more particularly to a tungsten gate electrode and methods of fabricating the same
• Aluminum and doped polycrystaUine silicon have been widely used for decades as gate electrode materials in MOS circuit designs Indeed some of the earliest MOS integrated circuits were implemented as p channel enhancement mode devices using aluminum as the gate electrode material Aluminum became an early material of choice due to its relatively low resistivity and material cost Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing
• polysilicon has the disadvantage of a much higher resistivity as compared to aluminum Higher resistivity translates into higher values of interconnect line resistance that can lead to undesirably long RC time constants and DC voltage variations within VLSI or ULSI circuits
• the development of polycide films on top of polysilicon layers has alleviated some of the resistivity shortcomings of polysilicon gate electrodes
• the resistivity of polysilicon gate electrodes in conventional MOS integrated circuit processing still presents a potential impediment to successful process scaling through reductions in the operating voltages of VLSI and ULSI devices
• Another disadvantage of polysilicon as a gate electrode material is polysilicon depletion In p channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron The implant also deposits boron into the polysilicon of the gate electrode Subsequent thermal processing steps to fab ⁇ cate a conventional p-channel field effect transistor frequently cause boron
• tungsten for gate electrode design
• the larger work function of tungsten produces low and nearly symmetrical threshold voltages for both PMOS and NMOS devices on moderately doped substrates Accordingly, tungsten is attractive as a gate electrode material in CMOS circuit design
• tungsten gate electrodes have the potential to exhibit reduced subthreshold leakage currents and a decreased sensitivities to body bias as compared to conventional doped polysilicon gate electrodes
• the resistivities of tungsten gate electrodes may be as much as 100 times or more lower than comparably sized doped polysilicon gates
• tungsten as a gate electrode material
• a gate oxide layer is formed on a doped silicon substrate by thermal oxidation or chemical vapor deposition ("CVD") Thereafter, an adhesion or so-called "glue” layer is blanket deposited on the gate oxide layer
• a tungsten film is next deposited on the glue layer
• the tungsten film is deposited by the CVD reduction of WF 6 in a silane ambient
• the deposition of a glue layer is a necessary predicate to CVD tungsten deposition due to the relatively poor adhesion of CVD tungsten to oxide
• a glue layer composed of a material which exhibits acceptable adhesion to the underlying oxide and the later-deposited tungsten film is applied as a precursor to the tungsten CVD step
• Titanium nitride is a common material used for a glue layer, although other titanium based films, such as Ti W have been used as well
• the deposition of a titanium based adhesion film normally cannot be carried out in the same CVD chamber used to deposit the CVD tungsten film Accordingly, the CVD glue layer and the CVD tungsten films involve separate deposition steps in separate chambers and the attendant movement of wafers between the two
• a method of fabricating a circuit device includes forming an insulating film on a substrate and forming a film of amorphous silicon and amorphous tungsten on the insulating film A film of polycrystaUine tungsten is formed on the film of amorphous silicon and amorphous tungsten and the substrate is annealed to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystaUine tungsten film.
• a method of fabricating a gate electrode stack on a substrate includes forming an insulating film on the substrate and forming a conductor film on the insulating film by initially depositing a film of amorphous silicon and amorphous tungsten, and thereafter depositing a film of polycrystaUine tungsten on the film
• a circuit device in accordance with another aspect of the present invention, includes a substrate, an insulating film on the substrate and a tungsten silicide film on the insulating film that has a sufficient amount of unbonded silicon to bond the tungsten silicide film to the insulating film A tungsten film is positioned on the tungsten silicide film BRIEF DESCRIPTION OF THE DRAWINGS
• FIG 1 is a cross-sectional view of an exemplary conventional tungsten gate electrode stack fabricated on a semiconductor substrate
• FIG 2 is a cross-sectional view depicting the initial fabrication steps for the conventional gate electrode stack depicted in FIG 1 ,
• FIG 3 is a cross-sectional view of an exemplary embodiment of a tungsten gate electrode stack fabricated on a semiconductor substrate in accordance with the present invention
• FIG 4 is a cross-sectional view of the substrate depicted in FIG 3 depicting the formation of a gate insulating layer thereon in accordance with the present invention
• FIG 5 is a cross-sectional view like FIG 4 depicting the deposition of an adhesion layer in accordance with the present invention
• FIG 6 is a cross-sectional view like FIG 5 depicting the deposition of a tungsten film on the adhesion layer in accordance with the present invention
• FIG 7 is a cross-sectional view like FIG 6 depicting the formation of a lithographic mask on the tungsten in accordance with the present invention
• FIG 1 therein is shown a cross- sectional view of an exemplary conventional tungsten gate electrode stack 10 fabricated on a semiconductor substrate 12
• the gate electrode stack 10 is commonly used as a switching device for a field effect transistor the other components of which are not shown for simplicity of illustration
• the stack 10 consists of a gate dielectric layer 14 positioned on the substrate 12, an adhesion or glue layer 16 formed on the gate dielectric layer 14 and a tungsten gate electrode 18 formed on the adhesion layer 16
• the substrate 12 is composed of silicon while the gate dielectric layer 14 is composed of an oxide of silicon
• the adhesion layer 16 is composed of a titanium based material, such as TiN
• the gate dielectric layer 14 is initially established on the silicon substrate 12 by thermal oxidation or chemical vapor deposition Oxide has been and continues to be a principal material of choice for gate dielectric layers in transistor fabrication due to its acceptable electrically insulating properties and relative ease of fabrication
• the relatively poor adhesion characteristics of CVD tungsten to oxide necessitates the fabrication of the adhesion layer 16 on the gate dielectric layer 14 prior to the deposition of the tungsten layer 18
• titanium or titanium nitride is deposited on the gate dielectric layer 14 by physical vapor deposition or CVD as the case may be
• the titanium-based adhesion layer 16 will readily adhere to the underlying oxide layer 14, and the later deposited tungsten layer 18 will readily adhere to the titanium-based adhesion layer 16
• the adhesion layer 16 is a laminate of an underlying titanium layer and an overlying titanium nitride layer
• the tungsten electrode layer 18 is next deposited on the adhesion layer 16 in a CVD process involving the reduction of WF 6 gas in the presence of S ⁇ H 4 and H, gas
• the reducing ambient is initially primarily silane
• the percentage of silane is reduced and the percentage of hydrogen is correspondingly increased to complete the reduction and deposition process
• the result is the formation of a polycrystaUine tungsten film 18 on the adhesion layer 16
• the difficulty with this conventional approach for fabricating a tungsten gate electrode stack is the propensity for the adhesion layer 16 to delaminate from the underlying gate dielectric layer 14 as a result of the formation of T ⁇ F x compounds in the adhesion layer 16
• the formation of T ⁇ F x compounds is an unwanted byproduct of the diffusion of fluorine atoms from the WF 6 reduction process into the adhesion layer 16
• the diffused fluorine atoms may readily react with the highly reactive titanium,
• the tungsten film 18 is subsequently masked and anisotropically etched to yield the completed gate electrode stack 10 depicted in FIG 1
• the aforementioned delamination may result in unacceptably high resistivity for the gate electrode stack 10 or in catastrophic failure of the device associated with the gate electrode stack 10
• FIG 3 is a cross-sectional view of the gate electrode stack 20 fabricated on a semiconductor substrate 22
• the gate electrode stack 20 consists of a gate insulating layer 24 fabricated on the semiconductor substrate 22, a tungsten silicide adhesion layer 26 positioned on the gate insulating layer 24 and a tungsten gate electrode 28 positioned on the adhesion layer 26
• the tungsten silicide adhesion layer 26 contains a sufficient amount of unbonded silicon atoms which adhere to the underlying gate insulating layer 24, and a majority concentration of tungsten silicide to which the overlying tungsten gate electrode 28 readily adheres
• An exemplary process flow for fabricating the gate electrode stack 20 in accordance with the present invention may be understood by referring now to FIGS 4, 5, 6 and 7, and initially to FIG 4 Initially, the gate insulating layer or film 24 is fabricated on the semiconductor substrate 22
• the substrate 22 may be composed of p- doped
• FIGS 5 and 6 depict two stages of a CVD reduction of WF 6 in silane Initially, and as depicted in FIG 5, a mixture of WF 6 and S ⁇ H 4 is flowed over the gate insulating layer 24 for a relatively short period of time at a chamber temperature of about 300 to 400°C and pressure of about 100 to 300 mtorr
• the S ⁇ H 4 -to-WF 6 ratio is kept high enough to produce a deposition of a combination of amorphous silicon ( ⁇ -Si) and amorphous tungsten ( ⁇ -W)
• the purpose of the high S ⁇ H 4 -to-WF 6 ratio is to ensure that the deposition produces ⁇ Si and ⁇ -W along with a sufficient amount of unbonded silicon atoms It is desirable for silicon to be present in the film 26 in non-stoichiomet ⁇ c quantities relative to the tungsten so that a subsequently performed anneal to convert the
• the flow of S ⁇ H 4 is greatly reduced while the flow of WF 6 is continued to produce the film 28 of polycrystaUine tungsten as shown FIG 6
• the polycrystaUine structure will yield more favorable resistivity than a more amorphous grain structure
• the film 28 will be deposited to a greater thickness than the ⁇ -Si and ⁇ -W film 26, although the thicknesses of both films 26 and 28 are largely matters of design discretion
• the tungsten film 28 will have a thickness that is approximately twenty times the thickness of the underlying adhesion layer 26
• the 2 1 S ⁇ H 4 -to-WF 6 ratio flow may be carried out for about 20 seconds and the 1 2 S ⁇ H 4 -to-WF 6 ratio flow for about 400 seconds
• a suitable lithographic mask 38 composed of well known resist or other masking materials is patterned, that is, exposed and developed to yield the desired shape of the later formed gate electrode stack 20 depicted in FIG 3
• the tungsten film 28, the underlying adhesion layer 26 and the gate insulating layer 24 are next anisotropically etched to yield the gate electrode stack 20 depicted in FIG 3
• the etch is advantageously a fluo ⁇ nated plasma etch using, for example, CF 4 /0 2 with argon as a diluent gas
• the substrate 22 is next annealed at about 500 to 1100°C
• the anneal produces a chemical reaction between the ⁇ -Si and the ⁇ -W in the film 26 which produces tungsten silicide with the generic chemical formula W x S ⁇ ⁇ , specific examples of which may be W 5 S ⁇ , and WSi-.
• the process of depositing the film 26 resulted in non-stoichiomet ⁇ c quantities of silicon and tungsten in the film 26, there will be excess and unbonded silicon atoms in the film 26 following the anneal which readily adhere the film 26 to the underlying oxide film 24
• the anneal also increases the average grain size of the overlying polycrystaUine tungsten electrode 28 which results in an improvement in the electrical resistivity thereof
• the anneal may be performed for about 30 to 90 minutes in a furnace process or for about 5 to 75 seconds in a rapid thermal anneal process
• the anneal may be performed prior to the patterning of the gate electrode stack 20
• the anneal may be performed on the blanket films 24, 26 and 28 depicted in FIG 7 and the aforementioned anisotropic etch performed thereafter
• the process of the present invention eliminates titanium as an adhesion layer material, thus eliminating the potential for delamination due to titanium-fluorine reactions
• the process of the present invention provides for the seamless production of a tungsten gate electrode and underlying adhesion layer by merely changing the ratio of WF 6 and silane flows into the CVD chamber In this way, a separate process for establishing a titanium based adhesion layer, which ordinarily requires the use of a separate tool and workpiece movements tor depositing both tungsten and titanium is eliminated
• specific embodiments have been shown by way ol example in the drawings and have been described in detail herein However, it should be understood that the invention is not intended to be limited to the particular forms disclosed Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims

Landscapes

• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=23942694

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (9)

Citations (3)

Family Cites Families (19)

• 2000
  • 2000-01-21 US US09/489,169 patent/US6284636B1/en not_active Expired - Lifetime
  • 2000-08-16 KR KR1020027009377A patent/KR100682643B1/ko not_active Expired - Fee Related
  • 2000-08-16 JP JP2001553570A patent/JP2003520445A/ja active Pending
  • 2000-08-16 DE DE60037337T patent/DE60037337T2/de not_active Expired - Lifetime
  • 2000-08-16 EP EP00955608A patent/EP1258033B1/en not_active Expired - Lifetime
  • 2000-08-16 WO PCT/US2000/022505 patent/WO2001054177A1/en not_active Ceased

Patent Citations (3)

Non-Patent Citations (5)

Also Published As

Similar Documents

Legal Events