WO2001048828A1 - L- and u-gate devices for soi/sos applications - Google Patents

L- and u-gate devices for soi/sos applications Download PDF

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Publication number
WO2001048828A1
WO2001048828A1 PCT/US2000/034249 US0034249W WO0148828A1 WO 2001048828 A1 WO2001048828 A1 WO 2001048828A1 US 0034249 W US0034249 W US 0034249W WO 0148828 A1 WO0148828 A1 WO 0148828A1
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WO
WIPO (PCT)
Prior art keywords
leg
shaped gate
region
semiconductor device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/034249
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English (en)
French (fr)
Inventor
David Owen Erstad
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Honeywell Inc
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Honeywell Inc
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Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Priority to EP00988112A priority Critical patent/EP1243028B1/en
Priority to JP2001548446A priority patent/JP2003518775A/ja
Priority to DE60034483T priority patent/DE60034483T2/de
Publication of WO2001048828A1 publication Critical patent/WO2001048828A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

  • the present invention relates to semiconductor devices, and more particularly to
  • semiconductor devices that are formed in a thin film of semiconductor material that sits
  • SOI Silicon-on-Insulator
  • SiN Silicon-on-Sapphire
  • SOS silicon-on-sapphire
  • CMOS technology typically include a semiconductor
  • the air or oxide dielectric layer helps provide lateral isolation between adjacent pixels.
  • This semiconductor structure typically includes a body/channel region disposed
  • a thin dielectric layer e.g., gate oxide.
  • side wall perimeter of the device typically extends under the polysilicon gate layer
  • a suicide layer is often provided
  • hysteresis effects can prevent proper circuit operation. These effects include the so-
  • kink effect and the parasitic lateral bipolar action.
  • the “kink” effect originates from impact ionization. For example, when an N-channel SOI/SOS MOSFET operates
  • the generated holes build up in the channel/body region of the device, thereby raising the body potential.
  • the body bias may be raised sufficiently so that the source to body p-n junction is forward biased.
  • resulting emission of minority carriers into the channel/body region may cause a
  • parasitic NPN bipolar transistor between the source, body and drain to turn on, leading
  • Both the "kink” effect and the parasitic bipolar effect can be avoided if charge is not allowed to accumulate in the channel/body region.
  • a body contact is often used to
  • channel/body region will move to lower potential regions, the body contact and the
  • source terminals can be tied together to eliminate the "floating body” effects.
  • a leakage path or 'parasitic” channel may be induced along the side walls of the body/channel region, and in particular, between the source and drain. This can result in
  • Figure 1 shows a typical prior art N-channel SOI MOSFET with body control.
  • the MOSFET is generally shown at 8, and is commonly called a T-gate MOSFET
  • the T-gate MOSFET 8 has an active region 10
  • the active region 10 is divided into three regions by T-gate 14, including the source region 20, the
  • the T-gate 14 includes a first leg
  • the N-type source/drain regions 20 and 22 are located on either side of the first leg 16 and along the lower side of the second leg 18.
  • region 24 is located above the second leg 18. Located under the first and second legs 16 and 18 is a p-type body/channel region.
  • the active region 10 and isolation region 12 are provided using known means
  • a thin gate oxide layer is provided over the active region 10, followed by a doped polysilicon gate layer.
  • the doped polysilicon gate layer and the gate oxide layer are provided.
  • the source and drain regions 20 and 22 are then selectively doped with an N-type dopant (for an N-channel device).
  • mask such as mask 30, is used to define the area that is to be exposed to the N-type
  • the body tie region 24 is selectively doped with a P-type dopant.
  • the T-gate configuration has a number of advantageous.
  • the T-gate configuration provides a body tie connection to the body/channel region under gate 14.
  • holes that are generated in the body/channel region under the first leg 16 of gate 14 pass through the P-type region under the second leg 18, and arrive at the P-type body
  • T-gate configuration Another advantage of the T-gate configuration is that the second leg 18
  • the second leg 18 also functions to prevent the suicide layer from
  • T-gate configuration A limitation of the T-gate configuration is that the channel/dielectric interface
  • leakage path or "parasitic" channel may be induced along the lower side wall 34 when
  • T-gate configuration Another limitation of the T-gate configuration is that a separate body tie region
  • These metal routes may further reduce the packing density that can be achieved by increasing congestion on the metal layer.
  • T-gate configuration Another limitation of the T-gate configuration is that the lateral pitch for two
  • each transistor must be provided in a separate active region. This alone reduces the packing density that can be achieved for the
  • minimum spacing requirements can also significantly increase the minimum lateral
  • the additional gate area also increases the thin
  • Figure 2 shows another prior art N-channel SOI MOSFET with body control.
  • the MOSFET is generally shown at 50, and is often referred to as an H-gate MOSFET because of the H-shape of gate 51.
  • the H-gate MOSFET 50 is similar to the T-gate
  • MOSFET of Figure 1 but further includes a third leg 52 along the bottom of the source
  • leg 52 helps eliminate the channel/dielectric interface along the lower side wall 70 of the body/channel region under the first leg 60. As such, the chance that a parasitic channel
  • third leg 52 also functions to prevent the suicide layer from connecting the body tie region 66 to the source region 54 and the drain region 56.
  • Holes generated in the body/channel region under first leg 60 may pass through
  • the holes may also pass through
  • H-gate configuration A limitation of the H-gate configuration is that body contacts must be provided
  • one or more metal routes must typically be
  • the third leg 52 increases the capacitance of the gate 51, which as described above, can
  • the packing density of the device may be improved relative to the T-gate and H-gate
  • the present invention may also reduce the overall gate
  • an L-Gate device in one illustrative embodiment of the present invention, includes an active region formed on an insulating layer and surrounded by an isolation region.
  • the active region has a top edge, a bottom edge, a
  • first lateral edge and a second lateral edge.
  • a first leg of the L-shaped gate is spaced
  • a second leg of the L-shaped gate is spaced inward of the top edge and extends into the active region over the first lateral edge before
  • the second leg helps eliminate the channel/dielectric interface
  • a drain region is defined by the first lateral edge of the active region, the first leg, the top edge of the active region and the second leg.
  • a source region is defined by the second lateral edge of the active region and the L-shaped gate. The source region
  • the drain region have a first conductivity type, while the active region under the first
  • an implant region having the second conductivity type extends from a portion of
  • a silicide layer preferably
  • the source contact may be used to bias both the source and
  • the second leg may be spaced inward from the bottom edge of the active region,
  • the second leg may overlap at least a portion of the bottom edge, which
  • one of these embodiments may provide an increased packing density over the other.
  • the second leg may extend past
  • the second leg that extends past the first leg may form a nub.
  • the nub increases the channel
  • shaped gates may be provided in the same active region, so long as they share a common source. This may help increase the packing density of the device.
  • a common source such as a transistor, a transistor, or a transistor.
  • second L-shaped gate having a first leg and a second leg may be provided in the same
  • shaped gate is preferably spaced inward of the second lateral edge and inward of the first L-shaped gate. As with the first L-shaped gate, the first leg of the second L-shaped gate
  • the second leg of the second L-shaped gate preferably is spaced inward from the
  • the second leg preferably does
  • a second drain region is then defined by the
  • a common source region is defined by the space between the first and second L-shaped gates.
  • a second implant region which may be an enlarged first implant region
  • a silicide layer or the like may extend over at least a
  • the U-gate device is formed on an active region that is
  • the active region has a top edge, a bottom edge, a
  • the U-gate has a first leg, a second leg and a third leg.
  • the first leg is preferably spaced inward of the first lateral edge and inward
  • the second leg preferably extends into
  • the third leg is preferably spaced from the second leg, and extends into the active region over the first lateral edge before intersecting the
  • the third leg preferably does not extend to the second lateral edge. Because
  • the second and third legs do not extend to the second lateral edge, there is a space between the first, second and third legs of the U-shaped gate and the second lateral edge.
  • a drain region is defined by the first lateral edge of the active region, the first
  • a source region is defined between the second
  • the source region and the drain region preferably are identical to each other.
  • an implant region having the second conductivity type preferably extends from a
  • a silicide layer or the like is then provided over at least a portion of the implant region and the source
  • the second leg may be spaced inward of the top edge of the active region, and
  • the third leg may be spaced inward of the bottom edge. This leaves a space between the
  • the second leg may overlap at least a portion
  • the third leg may overlap at least a portion of the bottom edge. This may not leave a space between the second leg and the top edge, and/or between the
  • one of these embodiments may provide an increased packing density over the other.
  • the second leg and third leg may extend past the first leg
  • the first nub may help increase the channel width along the side wall that borders the second leg, and the second nub may
  • first nub and the second nub may thus help control the "effective" channel width of the
  • the U-shaped gate may allow multiple transistors to be placed in the same active region, so long as they share a common
  • a second U-shaped gate having a first leg, a second leg and a third leg may be
  • leg of the second U-shaped gate is preferably spaced inward of the second lateral edge
  • the second leg of the second U-shaped gate is preferably spaced inward from the
  • leg of the second U-shaped gate preferably intersects the first leg of the second U- shaped gate, but does not extend to the first U-shaped gate.
  • the third leg of the second U-shaped gate is preferably spaced inward from the bottom edge, and extends into the active region over the second lateral edge. The third leg of the second
  • U-shaped gate preferably intersects the first leg of the second U-shaped gate, but does
  • a second drain region is then defined by the second lateral edge of the active
  • a common source region is defined by the space between the second U-shaped gate and the first U-shaped gate.
  • a second implant region which may be part of an enlarged first
  • implant region may extend from a portion of the second U-shaped gate and into the
  • a silicide layer or the like may then extend over at least a
  • Figure 1 is an enlarged top view of a prior art T-gate MOSFET with body
  • Figure 2 is an enlarged top view of a prior art H-gate MOSFET with body
  • FIG. 3 is an enlarged top view of an illustrative L-gate MOSFET in accordance
  • Figure 4 is an enlarged top view of another illustrative L-gate MOSFET in
  • Figure 5 is an enlarged top view of two illustrative L-gate MOSFETs in a
  • Figure 6 is an enlarged top view of an illustrative U-gate MOSFET in
  • Figure 7 is an enlarged top view of another illustrative U-gate MOSFET in
  • Figure 8 is an enlarged cross-sectional view of the illustrative U-gate MOSFET
  • FIG. 9 is an enlarged top view of another illustrative U-gate MOSFET in accordance with the present invention.
  • Figure 10 is an enlarged top view of two illustrative U-gate MOSFETs in a
  • FIG. 3 is an enlarged top view of an illustrative L-gate MOSFET in accordance
  • the L-Gate device is generally shown at 100.
  • the L-gate device 100 includes an active region 102 formed on an insulating layer and is
  • the active region 102 has a top edge 106, a
  • a first leg 116 of the L-shaped gate 117 is spaced inward of the first lateral edge 110 and inward of the
  • second leg 118 of the L-shaped gate 117 is spaced inward of the top edge 106 and
  • the second leg 118 helps eliminate the channel/dielectric interface along side wall 152 of the body/channel region.
  • the other channel/dielectric interface 120 remains. It is contemplated that the first leg 116 may extend over the bottom edge 108,
  • a drain region 122 is defined by the first lateral edge 110 of the active region
  • a source region 124 is defined by the second lateral edge 112 of the active region 102 and the L-shaped gate 117.
  • the source region 124 and the drain region 122 have a first
  • second leg 118 has a second conductivity type (e.g., P).
  • P second conductivity type
  • an implant region 130 having the second conductivity type (e.g., P)
  • implant region 130 may be defined by mask 132.
  • a silicide layer preferably formed using a conventional silicide process, is
  • a portion of the implant region 130 and the source region 124 to electrically connect the implant region 130 to the source region 124. Accordingly, a
  • source contact 136 may be used to bias both the source 124 and the channel/body region
  • this may increase the packing density of the transistor.
  • the second leg 118 of the gate 117 may be spaced inward from the bottom edge
  • the second leg 118 may overlap at least a portion of the bottom edge 108
  • embodiments may provide an increased packing density relative to the other.
  • the second leg 118 may extend past the first leg 116 toward the second lateral edge 112 of the active region 102.
  • the portion of the second leg 118 that extends past the first leg 116 may form a nub 150.
  • the nub 150 increases
  • the overall gate area may be reduced relative to the T-gate and H-gate
  • the spacing between two adjacent L-gate devices may be reduced relative to
  • FIG. 5 shows an enlarged top view of two L-gate MOSFETs in a common active region 200.
  • the first L-shaped gate 117 is similar to that described
  • the second L-shaped gate 202 has a first leg 204
  • the first leg 204 of the second L-shaped gate 202 is spaced inward of the second lateral edge 112 and inward from the first L-shaped gate 117.
  • first leg 204 of the second L-shaped gate 202 preferably extends into the active region
  • the first leg 204 may extend over
  • the bottom edge 108 as shown at 220, or may stop at the second leg 206.
  • leg 206 of the second L-shaped gate 202 is spaced inward from the top edge 106, and extends into the active region 200 over the second lateral edge 112 before intersecting
  • the second leg 206 preferably does not extend to the first L-shaped
  • a second drain region 210 is defined by the second lateral edge 112 of the active
  • common source region 214 is defined by the space between the first L-shaped gate 117 and the second L-shaped gate 202.
  • a second implant region which in the embodiment shown is part of an enlarged
  • first implant region 130 extends from a portion of the second L-shaped gate 202 into
  • a silicide layer (see Figure 8) or the like then extends
  • the second L-shaped gate 202 may be inverted relative to
  • the second leg 206 of the second L-shaped gate 202 may be positioned between the second drain region 210 and the upper edge 106 of the
  • Figure 6 is an enlarged top view of an illustrative U-gate MOSFET in
  • the illustrative U-gate MOSFET is generally
  • the U-gate device 300 includes an active region 302 formed on an insulating layer and is surrounded by an isolation region 304.
  • the active region has a
  • a first leg 314 of the U-shaped gate 316 is preferably spaced inward of the first lateral
  • first leg 314 may extend over the top edge 306 and/or over the bottom edge 308 as
  • a second leg 318 preferably extends into the active region 302 over the first
  • a third leg 320 spaced from the second leg 318, extends into the active
  • a drain region 326 is defined by the first lateral edge 310 of the active region
  • a source region 330 is defined by the second lateral edge 312 of the active region 302 and the U-shaped gate
  • the source region 330 and the drain region 326 preferably have a first conductivity
  • leg 320 have a second conductivity type (e.g., P).
  • a mask extends from a portion of the U-shaped gate 316 into the source region 330.
  • a silicide layer is preferably used to define the implant region 332.
  • the second leg 318 may be spaced inward of the top edge 206 of the active
  • the second leg 318 may overlap at least a
  • portion of the top edge 306, and/or the third leg 320 may overlap at least a portion of the bottom edge 308 of the active region 302. This latter configuration does not leave any
  • one of these embodiments may provide an increased packing density over the other.
  • leg 320 may extend past the first leg 314 toward the second lateral edge 312 of the active region 302. The portion of the second leg 318 that extends past the first leg forms
  • the first nub 350 may help increase the channel width along
  • the side wall 354 that borders the second leg 318, and the second nub 352 may help
  • both the first nub 350 and the second nub 352 may help control the
  • the overall gate area may be reduced relative to
  • Figure 8 is an enlarged cross-sectional view of the U-gate MOSFET of Figure 7
  • a bottom insulating layer 383 supports the active region 302.
  • active region 302 includes the source region 330, the implant region 332 and the
  • implant region 332 is the same conductivity type as the body/channel region 382, the implant region 332 is electrically connected to the body/channel region 382.
  • a silicide layer 384 is provided over the implant region 332
  • implant region 332 Since the implant region 332 is electrically connected to the body/channel
  • a gate oxide layer 380 which supports the
  • the second leg 320 is preferably a doped polysilicon material.
  • Another silicide layer 386 is preferably provided above the second leg 320 to lower the
  • Figure 10 is an enlarged top view of two illustrative U-gate MOSFETs in a
  • the U-shaped gate may allow
  • the first U-shaped gate 316 may be similar to that described above with respect
  • the second U-shaped gate 400 may
  • the first leg 402 is a first leg 402, a second leg, 404, and a third leg 406.
  • the first leg 402 is
  • the second leg 404 is preferably spaced inward from the top edge
  • the third leg 406 is preferably spaced
  • the third leg 406 intersects the first leg 402 of the second U-shaped gate 400, but does not extend to the first U-shaped gate 316.
  • the second leg 404 and the third leg 406 may overlap at least a portion of the top and bottom edges
  • a second drain region 420 is defined by the second lateral edge 312 of the active
  • a common source region 422 extends between the second U-shaped gate 400 and the first U-shaped gate 316.
  • embodiment shown is part of an enlarged first implant region, may extend from a
  • silicide layer or the like may then extend over at least a portion of the second implant region 332 and over the common source region 422 for electrically connecting the

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  • Thin Film Transistor (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Steering-Linkage Mechanisms And Four-Wheel Steering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/US2000/034249 1999-12-28 2000-12-18 L- and u-gate devices for soi/sos applications Ceased WO2001048828A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00988112A EP1243028B1 (en) 1999-12-28 2000-12-18 L- and u-gate devices for soi/sos applications
JP2001548446A JP2003518775A (ja) 1999-12-28 2000-12-18 Ｓｏｉ／ｓｏｓの応用のためのｌ及びｕゲートデバイス
DE60034483T DE60034483T2 (de) 1999-12-28 2000-12-18 L- und U-Gate-Bauelemente für SOI/SOS-Anwendungen

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/473,158 US6307237B1 (en) 1999-12-28 1999-12-28 L-and U-gate devices for SOI/SOS applications
US09/473,158 1999-12-28

Publications (1)

Publication Number Publication Date
WO2001048828A1 true WO2001048828A1 (en) 2001-07-05

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PCT/US2000/034249 Ceased WO2001048828A1 (en) 1999-12-28 2000-12-18 L- and u-gate devices for soi/sos applications

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US (1) US6307237B1 (enExample)
EP (2) EP1243028B1 (enExample)
JP (1) JP2003518775A (enExample)
AT (1) ATE360261T1 (enExample)
DE (1) DE60034483T2 (enExample)
WO (1) WO2001048828A1 (enExample)

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US9842858B2 (en) 2015-11-18 2017-12-12 Peregrine Semiconductor Corporation Butted body contact for SOI transistor
US9847349B1 (en) 2016-09-19 2017-12-19 Stmicroelectronics Sa Biasing the substrate region of an MOS transistor
US9960737B1 (en) 2017-03-06 2018-05-01 Psemi Corporation Stacked PA power control
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US6483156B1 (en) * 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
US20030036236A1 (en) * 2001-08-15 2003-02-20 Joseph Benedetto Method for radiation hardening N-channel MOS transistors
US6642579B2 (en) * 2001-08-28 2003-11-04 International Business Machines Corporation Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET
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US20030222308A1 (en) * 2002-05-30 2003-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. SOI MOSFET with compact body-tied-source structure
US6960810B2 (en) * 2002-05-30 2005-11-01 Honeywell International Inc. Self-aligned body tie for a partially depleted SOI device structure
US6861716B1 (en) * 2003-10-31 2005-03-01 International Business Machines Corporation Ladder-type gate structure for four-terminal SOI semiconductor device
US7084462B1 (en) * 2005-04-15 2006-08-01 International Business Machines Corporation Parallel field effect transistor structure having a body contact
US20070090431A1 (en) * 2005-10-24 2007-04-26 Honeywell International Inc. Device layout for reducing device upset due to single event effects
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US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
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US8217456B1 (en) 2011-03-11 2012-07-10 International Business Machines Corporation Low capacitance hi-K dual work function metal gate body-contacted field effect transistor
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US20140103440A1 (en) * 2012-10-15 2014-04-17 Texas Instruments Incorporated I-shaped gate electrode for improved sub-threshold mosfet performance
US20170141134A1 (en) * 2015-11-18 2017-05-18 Peregrine Semiconductor Corporation Butted Body Contact for SOI Transistor
US10424664B2 (en) 2016-12-14 2019-09-24 Globalfoundries Inc. Poly gate extension source to body contact
FR3076398B1 (fr) * 2017-12-29 2019-12-27 X-Fab France Transistor et son procede de fabrication
CN113314610B (zh) 2020-02-27 2024-04-30 台湾积体电路制造股份有限公司 晶体管器件及其制造方法
US11476279B2 (en) 2020-08-06 2022-10-18 Globalfoundries U.S. Inc. Devices with staggered body contacts
CN114188408A (zh) * 2020-09-14 2022-03-15 联华电子股份有限公司 半导体元件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993008603A1 (en) * 1991-10-21 1993-04-29 Harris Corporation Soi cmos device having body extension for providing sidewall channel stop and body tie
US5298773A (en) * 1992-08-17 1994-03-29 United Technologies Corporation Silicon-on-insulator H-transistor layout for gate arrays
US5317181A (en) * 1992-09-10 1994-05-31 United Technologies Corporation Alternative body contact for fully-depleted silicon-on-insulator transistors
DE19623846A1 (de) * 1995-10-11 1997-04-17 Mitsubishi Electric Corp Halbleitereinrichtung
US5811855A (en) * 1997-12-29 1998-09-22 United Technologies Corporation SOI combination body tie
US5920093A (en) * 1997-04-07 1999-07-06 Motorola, Inc. SOI FET having gate sub-regions conforming to t-shape

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021542A (ja) * 1983-07-15 1985-02-02 Toshiba Corp 半導体集積回路装置
JPH0379035A (ja) * 1989-08-22 1991-04-04 Nippondenso Co Ltd Ｍｏｓトランジスタ及びその製造方法
US5217915A (en) * 1991-04-08 1993-06-08 Texas Instruments Incorporated Method of making gate array base cell
US5334545A (en) 1993-02-01 1994-08-02 Allied Signal Inc. Process for forming self-aligning cobalt silicide T-gates of silicon MOS devices
US5821575A (en) 1996-05-20 1998-10-13 Digital Equipment Corporation Compact self-aligned body contact silicon-on-insulator transistor
KR100252913B1 (ko) * 1997-04-21 2000-04-15 김영환 반도체 소자 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993008603A1 (en) * 1991-10-21 1993-04-29 Harris Corporation Soi cmos device having body extension for providing sidewall channel stop and body tie
US5298773A (en) * 1992-08-17 1994-03-29 United Technologies Corporation Silicon-on-insulator H-transistor layout for gate arrays
US5317181A (en) * 1992-09-10 1994-05-31 United Technologies Corporation Alternative body contact for fully-depleted silicon-on-insulator transistors
DE19623846A1 (de) * 1995-10-11 1997-04-17 Mitsubishi Electric Corp Halbleitereinrichtung
US5920093A (en) * 1997-04-07 1999-07-06 Motorola, Inc. SOI FET having gate sub-regions conforming to t-shape
US5811855A (en) * 1997-12-29 1998-09-22 United Technologies Corporation SOI combination body tie

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2459666A (en) * 2008-04-29 2009-11-04 Sharp Kk Thin film transistor with low leakage current
GB2460395A (en) * 2008-04-29 2009-12-02 Sharp Kk Thin film transistor and active matrix display
US10629621B2 (en) 2015-11-18 2020-04-21 Psemi Corporation Butted body contact for SOI transistor
US11791340B2 (en) 2015-11-18 2023-10-17 Psemi Corporation Butted body contact for SOI transistor, amplifier circuit and method of providing the same
US9842858B2 (en) 2015-11-18 2017-12-12 Peregrine Semiconductor Corporation Butted body contact for SOI transistor
US12205954B2 (en) 2015-11-18 2025-01-21 Psemi Corporation Butted body contact for SOI transistor and amplifier circuit
US10985183B2 (en) 2015-11-18 2021-04-20 Psemi Corporation Butted body contact for SOI transistor
WO2017164904A1 (en) * 2016-03-23 2017-09-28 Peregrine Semiconductor Corporation Butted body contact for soi transistor
US12323105B2 (en) 2016-09-16 2025-06-03 Psemi Corporation Standby voltage condition for fast RF amplifier bias recovery
US9837965B1 (en) 2016-09-16 2017-12-05 Peregrine Semiconductor Corporation Standby voltage condition for fast RF amplifier bias recovery
US10819288B2 (en) 2016-09-16 2020-10-27 Psemi Corporation Standby voltage condition for fast RF amplifier bias recovery
US11456705B2 (en) 2016-09-16 2022-09-27 Psemi Corporation Standby voltage condition for fast RF amplifier bias recovery
FR3056331A1 (fr) * 2016-09-19 2018-03-23 Stmicroelectronics Sa Polarisation de la region de substrat d'un transistor mos
US9847349B1 (en) 2016-09-19 2017-12-19 Stmicroelectronics Sa Biasing the substrate region of an MOS transistor
US9960737B1 (en) 2017-03-06 2018-05-01 Psemi Corporation Stacked PA power control
TWI803786B (zh) 2020-02-27 2023-06-01 台灣積體電路製造股份有限公司 具有凹入閘極結構的電晶體元件及其製造方法

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US6307237B1 (en) 2001-10-23
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EP1783836A3 (en) 2008-02-27
EP1783836A2 (en) 2007-05-09

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