GB2460395A

GB2460395A - Thin film transistor and active matrix display

Info

Publication number: GB2460395A
Application number: GB0807765A
Authority: GB
Inventors: Gareth Nicholas; Benjamin James Hadwen
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2008-04-29
Filing date: 2008-04-29
Publication date: 2009-12-02
Also published as: GB0807765D0

Abstract

A thin film transistor is formed in a semi-conductor island 1501 on an insulating substrate. The transistor comprises heavily doped source 1502 and drain 1504 regions of first conductivity type and a channel of a second conductivity type, more lightly doped than the source and drain regions. The channel is overlapped by one or more insulated gate electrodes 1506 and is provided with isolation diodes formed from pn-junctions between regions 1510 of the second conductivity type of the salve doping concentration as the channel, and the source or drain. The lightly doped regions 1510 of the diodes extend away from the channel by less than the length of the adjacent source or drain and are bounded by the channel, the source or drain, and an edge of the island 1501. The diodes isolate the channel from the edge of the island, eliminating early turn-on owing to sub-threshold leakage current caused by fixed charge in the surrounding insulator causing the channel to invert at reduced gate voltage.

Description

THIN FILM TRANSISTOR AND ACTIVE MATRIX DISPLAY

This invention relates to thin film transistors (TFT5), for example of a type that are fabricated in the manufacture of the display substrate of an active matrix liquid crystal display (AM LCD). The present invention also relates to active matrix displays including such transistors.

Figure 1 of the accompany drawings shows an AM LCD substrate. In the display pixel matrix 102, TFTs are located next to each pixel, or sub-pixel in the case of a colour display, to control the level of light emitted. TFTs are also widely used in the display gate and source drivers 104 and 106 respectively, and may also be employed in sensor driver circuits 108. Many products utilise such AMLCDs (e.g. mobile phones and personal digital assistants (PDA5)). An improvement in the electrical characteristics of the TFTs enables the power consumption of an AM LCD to be minimised, or alternatively enables higher performance. TFTs also find application in circuits for system on panel applications such as ambient light sensors and temperature sensors. Certain preferred circuit topologies that enable these applications, such as low power amplifiers, are feasible only if the TFT electrical characteristics are sufficiently uniform.

The TFT is a variant of the metal-oxide-semiconductor field effect transistor (MOSFET), which consists of two semiconductor diodes placed back to back and a capacitor formed between the semiconductor and a gate electrode that controls the current flow between the diodes. The structure of semiconductor diodes and transistors is well known [Y. Taur and T. K. Ning, "Fundamentals of Modern VLSI Devices," Cambridge University Press, 1998] and will not be described here. The difference between a TFT and a conventional MOSFET is that in a TFT the semiconductor takes the form of a thin film placed on an insulating substrate, rather than the entire substrate being comprised of the semiconductor material.

Figure 2 of the accompanying drawings shows a typical TFT, with the top-gate configuration (gate electrode 202 positioned above the semiconductor). The structure would typically be covered with a dielectric (e.g. 5i02) that has been omitted from the diagram for clarity. The fabrication processes for various types of TFT are well known but are outlined here. A base coat (typically 5i02) is deposited on the substrate (typically glass, but other materials including quartz and plastics may be used). If the final device is to incorporate a gate electrode below the channel, the gate material (usually a metal such as TiN, TaN, W or Mo, or sometimes poly Si) is deposited and patterned, followed by the deposition of a thin insulator layer (typically a few tens of nm of 5i02). The semiconductor (most likely Si) is deposited and patterned. It is usual for each TFT to be created in an individual semiconductor island on the insulating basecoat. Because each TFT is thus isolated, problems such as cross-talk between adjacent devices are removed.

The most common technique for patterning the semiconductor and other layers in the fabrication of a TFT is lithography. A light-sensitive chemical known as a photoresist is spun onto a deposited layer and then exposed to ultraviolet light whilst covered with a mask, so that only certain defined regions of the photoresist may react with the light.

The resist is then developed so that either the regions that were exposed or those that weren't are removed (depending on whether the resist used is "positive" or "negative").

The deposited layer may then be etched; the regions still covered by photoresist are protected from this process. The remaining resist is then removed. Since the fabrication of TFTs requires several such masking steps, all subsequent masks must be precisely aligned to the first. There will however always be unavoidable small errors in alignment, the magnitude of which depends on the accuracy of the mask aligner used. These errors must be accounted for in the design of the TFT.

At this point, a treatment such as laser annealing may be used to crystallise the semiconductor if it was deposited in the amorphous state, and the semiconductor may be doped by ion implantation or diffusion. If the TFT is to incorporate a gate electrode above the channel, a thin insulator layer and gate material are then deposited and patterned. The source and drain regions are formed (typically by ion implantation) so that they are heavily doped with an opposite polarity to the semiconductor material between them. For top-gate TFTs, the presence of the gate electrode serves to block implanted ions, so that they are only introduced to the semiconductor adjacent to it.

This is known as a self-aligned implant. For non self-aligned implants, a developed photoresist is relied upon to block the dopant ions where they are not required.

Diodes are formed at the junctions between semiconducting material of opposite doping polarities, so that a TFT contains two diodes, one at the junction between the source implant and the channel underneath the gate, and one at the junction between the drain implant and the channel. In an n-type semiconductor there is an excess of negative charge carriers (electrons), whilst in a p-type semiconductor there is an excess of positive charge carriers (holes). When the two types are brought together, excess electrons and holes diffuse across the junction and recombine with carriers of the opposite type. The removal of these free carriers leaves positively charged ions in the n-type region and negatively charged ions in the p-type region near the junction.

This is known as a depletion region, and the presence of the charged ions sets up an electric field that causes charge carriers to drift in the opposite direction to those that are diffusing across the junction. Equilibrium is reached when the current due to carrier drift equals that due to carrier diffusion. The width of the depletion region depends on the doping concentration in the two types of semiconductor. The depletion region is widest in semiconductors with a low concentration of dopants. The electric field strength will also be reduced in such a case. There is a small but non-zero capacitance associated with the depletion region of a diode, since the p and n-type regions may be thought of as the two electrodes of a capacitor, with the depletion region acting as the dielectric.

When a diode is forward biased, the n-type material is negatively biased with respect to the p-type material. This reduces the electric field strength across the depletion region and disturbs the equilibrium so that the diffusion current becomes larger than the drift current. Because the current flow is dominated by diffusion, there is an exponential dependence of current on applied voltage. Large currents can therefore flow through the diode for even relatively small applied forward biases.

In a diode under reverse bias, the n-type material is positively biased with respect to the p-type material. This increases the strength of the electric field across the depletion region and favours drift current over diffusion. Because electrons and holes are in short supply in the p-type and n-type material respectively, the current through the diode remains extremely small, however. The width of the depletion region increases as the reverse bias is increased, as more carriers recombine to accommodate the potential drop across the junction. Because of the increased depletion region size and electric field, diodes in reverse bias are sensitive to processes that create electron-hole pairs, such as illumination. Carriers generated by such a process will immediately be swept out of the depletion region by the electric field and a leakage current is observed through the diode.

In a complementary process, both n-channel TFTs (nTFT5) and p-channel (pTFT5) are created, so that at least two doping steps are required. For example, the nTFT source and drain regions may be formed by a phosphor (n-type) implant whilst the pTFTs are masked by photoresist. The pTFT source and drain regions may then be formed by a boron (p-type) implant with the nTFTs masked. To simplify fabrication, and reduce cost, integrated circuits may also be made with only a single variety of TFT, in a "single channel" process.

The TFT fabrication is completed by opening holes in a deposited dielectric (typically Si02 or SiN) and depositing and patterning metal contacts for the source, drain and gate electrodes. The formation of these contacts necessarily requires a certain minimum area of semiconductor in the contact region.

Because the substrate used for the TFT backplane is usually glass, there is a requirement to keep temperatures relatively low (below approximately 600 °C) throughout the fabrication process in order to minimise shrinkage and melting.

Alternative substrate materials such as plastic have even more stringent maximum temperature limitations.

The most common type of TFT employs a top-gate, for which gate electrodes are deposited subsequent to the formation of semiconductor islands and run across the entire width of each island, being contacted elsewhere. Consequently, there may be regions where the gate electrode wraps around the edge of the island, due to the difference in height of the island and the surrounding basecoat region. TFTs may also be fabricated with a gate electrode below the semiconductor, or with gate electrodes both above and below the semiconductor. Figure 3 of the accompanying drawings shows a cross-section through such an nTFT with two gate electrodes in the channel length direction (equivalent to the y direction in Figure 2). Either of these gate electrodes may be left floating, rather than being connected to a power supply.

The width of the TFT channel (x direction, parallel to the gate electrode in Figure 2) depends on the application of the device. To minimise the area required for integrated circuitry, it is generally desirable to make the TFT as small as possible. The current that flows through the TFT is proportional to the channel width however, so that for some applications the TFT width must remain relatively large. For logic applications the channel width can generally be narrower, and the limiting factor becomes the area required for the region where the metal source and drain electrodes contact the semiconductor. In such a case, the semiconductor island may be patterned as shown in Figure 4 of the accompanying drawings.

Figure 5 of the accompanying drawings shows a cross-section through a top-gate nTFT in the channel length direction. In typical operation, the source 502 is grounded, and the drain 504 is biased at a high voltage. The junction between the channel 508 and drain is therefore reverse biased. The potential of the gate electrode 506 determines whether or not current flows between the source and drain, thus giving rise to the switching operation of a TFT. With the gate electrode at a low potential (off state), the weakly p-type doped channel region acts a barrier to conduction between the heavily n-type doped source and drain regions. With the gate electrode at a high potential (on state), the surface of the channel region is inverted so that a thin layer of free electrons is created that enables current flow between source and drain. The gate voltage at which the surface of the channel first inverts is known as the threshold voltage. pTFT5 operate in the same fashion, except that the polarity of all dopants and applied potentials is reversed, and conduction takes place by means of holes rather than electrons. Typical transfer characteristics for an nTFT and pTFT are shown in Figure 6 of the accompanying drawings, illustrating how the current at the drain varies according to the potential on the gate.

Because the drain of a TFT is reverse biased, the electric field may be large enough to cause undesirable impact ionisation in the region of the channel near the junction.

When conduction carriers encounter a large electric field they may gain much more energy than normal, becoming hot carriers. Hot carriers may have sufficient energy to create damage within the semiconductor or surrounding insulator (or at the interface between them), which degrades the performance of the TFT over time. To reduce the electric field at the drain and hence reduce the number of hot carriers, lightly doped drain (LDD) or gate overlapped drain (GOLD) structures may be employed. The creation of LDD or GOLD structures requires an additional ion implantation step, and in the case of LDD structures this implant may be global (i.e. not masked with resist).

Figure 7 of the accompanying drawings shows nTFTs with LDD and GOLD structures.

The structures take the form of additional regions of n-type doping inserted between the heavily doped n-type source/drain regions and the p-type channel. The additional regions have a doping concentration that is lower than in the source and drain regions.

Because the potential varies more gradually across such a junction, the electric field strength is reduced. For LDD structures 702, the additional n-type regions are placed adjacent to the gate electrode, whereas for GOLD structures 704, the additional regions are positioned underneath the gate electrode.

The TFT semiconductor island is surrounded on all sides by an insulator such as Si02, which may contain fixed charge (either positive or negative) because of requirements for low temperature fabrication. The presence of fixed positive charge will cause p-type semiconductor material to invert at a smaller gate voltage than otherwise, whilst negative oxide charge will likewise cause n-type material to invert at a smaller gate voltage. It is thought that, because the edges of the semiconductor island are exposed to more of the insulator, the threshold voltage may be particularly small in these regions. In addition, if the TFT is of the top-gate configuration with the gate electrode wrapped around the side of the semiconductor island, the electric field strength between the gate and the semiconductor will be greater at the island edges than the centre upon application of a potential difference between the gate and source electrodes. This also has the effect of reducing the threshold voltage of the island edges.

The early turn-on of the edge regions of the island is seen as a leakage current in the transistor subthreshold region, as shown for the nTFT in Figure 8 of the accompanying drawings. A TFT with such leakage at the island edges may be modelled as two transistors in parallel, one representing the island edge parasitic transistors 902, and one representing the main body of the TFT 904, as shown in Figure 9 of the accompanying drawings. In order to ensure that the island edges are off when the gate electrode is at the source potential, the threshold voltage of the TFT must be increased, usually by increasing the concentration of the channel doping. This increases the magnitude of the supply voltage required to realise acceptable on and off currents, and consequently increases the power consumption of any circuit utilising TFTs. The presence of the subthreshold leakage current also has the effect of increasing the variance between TFTs in this regime of operation. Certain circuit topologies, such as low power amplifiers, rely on TFTs having well matched subthreshold currents. The variance introduced by the parasitic conducting channels at the island edge means that the performance of such circuits is reduced.

It is known that increasing the concentration of the channel doping only in the vicinity of the channel edges can help to reduce the leakage current associated with parasitic conduction in these regions. For example, US 5,488,001 discloses a technique for manufacturing TFTs with high-doped stripes created at the island edges by means of an ion implantation mask with bevelled edges. Such a technique necessarily requires modification of established TFT fabrication process flows, which will increase cost and may adversely impact yield. Furthermore, since the regions with increased doping concentration directly contact the highly doped source and drain regions, which have opposite doping polarity to the channel, it is likely that strong lateral electric fields will result, increasing junction leakage at the drain and degrading reliability.

An alternative approach is to create diodes at the edges of the semiconductor island that prevent the parasitic conduction paths underneath the gate electrode from communicating with the source and drain regions. Figure 10 of the accompanying drawings shows a plan view of a TFT with isolation diodes created using doping regions of opposite polarity to the source 1002 and drain 1004, as disclosed in US 4,791,464. In the case of an nTFT, the diodes are created using two p-type doped semiconductor regions. The weakly p-type doped region (known as p-doping) 1006 acts to reduce the strength of the electric field within the diode, while the heavily p-type doped region (known as p+ doping) 1008 acts to restrict the size of the depletion region that forms within the p-type side of the diode. The presence of diodes 1102 causes the parasitic transistors 1104 to be isolated from the source 1106 and drain 1108, as shown in the equivalent circuit in Figure 11 of the accompanying drawings.

The problem with this approach is that, when manufacturing such a transistor, it is necessary to use at least two implant steps that employ masks which are not self-aligned with respect to one another to create the n+ and p+ doped regions of the isolation diodes. Consequently, the TFT fabrication is made more challenging by the requirement that the implant masks should be precisely aligned in both the x and the y directions, as shown in Figure 12 of the accompanying drawings. Failure to achieve sufficiently accurate alignment can result in the separation between the n+ and p+ regions becoming too small, which will result in increased electric field strength in the diode due to the abruptly changing potential across the junction and greatly increased junction leakage. This approach is also unsuitable for use in a single channel process, in which only a single high dose implant is available (n+ for nTFT only process, p+ for pTFT only process). The TFT disclosed in US 4,791,464 can only be realised by using an additional implant step, complicating manufacture and obviating the key advantage of a single channel process.

Another approach is to fabricate the TFT in such a way that the gate electrode does not overlap the edges of the semiconductor island. US 4,918,498 describes a device in which the gate electrode terminates above regions with the opposite doping polarity to the source and drain regions. The drawback of this approach is that a metal contact must be made to the gate electrode directly above the semiconductor island, rather then elsewhere in the circuit. This requires that the gate electrode must have a region with a sufficiently large area that a contact to it can be reliably formed. The total area of the TFT will be unavoidably increased, which is highly undesirable when integrated circuits should consume as little area as possible. In addition, the greater area of gate electrode above the device may result in increased leakage current from the gate electrode.

Other relevant prior art includes disclosures concerning the addition of regions to transistors that may be used to ground the body of the device. Because the channel region of a conventional TFT is floating, it is possible for its potential to change as a result of a build-up of carriers generated by impact ionisation at the drain. This can lead to the kink effect, when the drain current of the TFT increases significantly as the drain voltage increases, rather than saturating, as expected for a well-behaved transistor [Y.

Taur and T. K. Ning, "Fundamentals of Modern VL5I Devices," Cambridge university Press, 1998]. This is detrimental to device reliability.

Figure 13 of the accompanying drawings shows prior art from us 6,940,138, in which regions of opposite doping polarity to the source and drain are added along the sides of the transistor in the channel length direction and contacted with metal lines. Although the purpose of such designs is to facilitate the removal of excess carriers and thus improve transistor reliability, it is likely that they would also prove beneficial in the reduction of the leakage current associated with the semiconductor island edges.

Once again, the problem with this approach is that is it unsuitable for use in a single channel fabrication process. Additionally, the area of the depletion regions that form between areas with opposite doping polarities will be rather large, due to the requirement for them to run along the entire length of the device, so that a body contact electrode can be accommodated. This will add to the parasitic capacitance associated with the source and drain junctions, degrading high frequency operation of the TFT. In addition, these depletion regions will be sensitive to carrier generation through exposure to light. This may make a device incorporating such structures unsuitable for use in a display, due to increased junction leakage in the reverse biased diode limiting the off state current that can be achieved. Furthermore, such a device may show increased sensitivity to temperature through elevated leakage in the isolation diodes at high temperatures. US 4,809,056 also describes a device in which the potential of the body can be controlled by means of an additional contact. Once again, the regions with opposite doping polarity to the source and drain regions run the entire length of the device, resulting in large depletion regions.

US statutory invention registration H 1435 describes a device that solves the problem of leakage at the island edges and enables control of the potential of the body of the device. As shown in Figure 14, the channel region 1402 is extended outside the gate electrode 1404 on both sides, and contacts are made to the p+ doped regions 1406.

The disadvantage of this approach is the area consumed by the need for the two additional contacts.

Although the prior art therefore describes techniques for reducing the leakage current associated with the edges of the semiconductor islands, there are significant disadvantages either in terms of manufacturing difficulty, yield, increased size, increased sensitivity to ambient conditions, degraded high frequency performance, or a combination of these.

According to a first aspect of the invention, there is provided a transistor as defined in the appended claim 1.

According to a second aspect of the invention, there is provided a display as defined in the appended claim 12.

Embodiments of the invention are defined in the other appended claims.

It is thus possible to provide diodes that isolate the regions of the channel at the edges of the semiconductor island from the source and drain to reduce or eliminate the leakage current associated with the early turn-on of the semiconductor island edges.

The isolation diodes are formed in such a way that they are compatible with a single channel fabrication process, in which either n+ or p+ implants are available, but not both.

An example of such a TFT comprises: * An island of semiconductor material positioned on an insulating substrate, the island having a top surface and side walls.

* At least one gate stack comprising of a gate electrode and a gate insulator layer that separates the electrode from the semiconductor island, positioned above or below, or above and below the semiconductor island.

* A channel region of a second conductivity type within the semiconductor island, positioned above/below the gate electrode and extending to the side walls.

* Source and drain regions of a first conductivity type within the semiconductor island on either side of the channel region.

* Additional regions of the first conductivity type and same doping concentration as the channel region, placed adjacent to the source/drain and channel region and extending to the sidewalls.

Rather than being formed of three distinct regions: n+ region, low doped region (either n-or p-) and p+ region, the isolation diodes are formed using only a high doped region and low doped region of opposite doping polarity. Because only a single high dose implant is required to create such isolation diodes, a TFT incorporating the diodes can be easily integrated into a single channel process, whilst maintaining the advantages of relatively simple fabrication and low cost.

Such a TFT with isolation diodes may also be employed in a complementary fabrication process. In this case, the advantage over prior art is that there is no longer a requirement to accurately align two implantation masks (for n+ and p+ doping), so that the manufacturing process is easier, allowing reduced cost and/or improved yield compared to the prior art. The absence of the second high doped region may result in a somewhat larger depletion region, however.

The potential problem of increased depletion region size may be addressed by patterning the semiconductor island. Rather than being formed within the existing semiconductor island, the isolation diodes may be formed in additional semiconductor regions that extend the transistor in the width direction (parallel to the gate electrode).

The additional regions do not run the entire length of the device, for example existing underneath the gate electrode and extending only a short distance beyond this in the transistor length direction (perpendicular to the gate electrode). Because the area of the depletion region associated with the isolation diodes is reduced or minimised, the leakage current of the diodes is also reduced or minimised, allowing a smaller TFT off state current to be achieved. In addition, the parasitic capacitance of the depletion regions is also reduced or minimised, ensuring that the impact of these regions on performance when the TFT is operated at high frequency is reduced. Sensitivity to illumination and temperature, in the form of elevated diode leakage currents, is also reduced or minimised.

The isolation scheme may be combined with a structure that acts to control the channel potential of the TFT. Whilst such structures can prevent leakage current at the Si island edges if they are added to both sides of the channel, this typically consumes a significant amount of area. As only one contact is needed to control the channel potential, the addition of an isolation diode of the type disclosed here to the other side of the TFT yields the advantages of channel potential control and leakage reduction or elimination in a more efficient manner than any of the prior art. Such a device may also be integrated in either a complementary or a single channel process.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a known AMLCD; Figure 2 shows a known typical TFT with the top-gate configuration; Figure 3 shows a cross-section through a known nTFT with top and bottom gate electrodes; Figure 4 shows a plan view of a known TFT with narrow width, suitable for logic applications; Figure 5 shows a cross-section through a known nTFT.

Figure 6 shows typical known TFT transfer characteristics; Figure 7 shows cross-sections through known nTFTs with LDD and GOLD structures; Figure 8 shows known TFT transfer characteristics where the nTFT suffers from subthreshold leakage; Figure 9 shows an equivalent circuit of a known TFT with parasitic conduction at the island edges; Figure 10 shows a plan view of a known TFT using the isolation scheme described by io US 4,791,464; Figure 11 shows an equivalent circuit of a known TFT with the diodes introduced in US 4,791,464 to prevent leakage at the island edges; Figure 12 illustrates a known requirement to precisely align two doping masks to form the structure described by US 4,791,464; Figure 13 shows known TFT with additional regions for hot carrier removal described by us 6,940,138; Figure 14 shows a plan view of a known TFT described in us statutory invention registration H 1435; Figure 15 shows a first embodiment of the invention; Figure 16 shows a second embodiment of the invention; Figure 17 shows the second embodiment of the invention for the case of a narrow width TFT; Figure 18 shows a third embodiment of the invention; Figure 19 shows a fourth embodiment of the invention; Figure 20 shows a fifth embodiment of the invention; Figure 21 shows a sixth embodiment of the invention Figure 22 shows the sixth embodiment of the invention, employing minimised area isolation diodes; and Figure 23 shows a seventh embodiment of the invention.

The first embodiment comprises a TFT with diodes that isolate the leakage current associated with the island edges using only two distinct regions of doping.

Figure 15 illustrates the embodiment in plan view for the case of an nTFT. The TFT comprises a rectangular thin film of semiconductor (most likely Si: either amorphous, polycrystalline or crystalline) and a gate electrode that may be positioned above or below the semiconductor so that it crosses the entire island, separated from it by a dielectric such as 5i02. There may be two gate electrodes positioned above and below the semiconductor island, either of which may be left floating rather than being connected to a supply voltage.

In the semiconductor island 1501, the source 1502 and drain 1504 regions are heavily n-type doped and are separated by the channel region, which lies directly above or below the gate electrode 1506 (or is sandwiched between two gate electrodes, depending on the type of TFT) and is doped weakly p-type. The semiconductor island is extended parallel to the gate electrode 1506 (x direction in Figure 15) in both directions so that additional weakly p-type doped regions 1510 can be accommodated adjacent to the source 1502 and gate electrode 1506. These regions are masked from the high dose n-type implant used to form the source 1502 and drain 1504 regions, thus having the same p-type doping concentration as the channel region underneath the gate electrode 1506, and do not extend all the way to the edge of the island perpendicular to the gate electrode (y direction in Figure 15). Beyond the extent of the p-type regions 1510, the source 1502 is extended parallel to the gate electrode so that the width of the silicon island (in the x direction) is constant. The additional regions 1510 are therefore bound on two sides by the source 1502, on one side by the gate electrode 1506, and on the remaining side by the island edge. Weakly p-type doped regions 1510 are likewise added on the drain 1504 side of the gate electrode 1506.

Isolation diodes are thus formed between the heavily n-type doped regions (1502, 1504) and the lightly doped p-type regions 1510.

An advantage of this embodiment over the prior art is that the device can be fabricated in a single channel process. The TFT can therefore be manufactured at lower cost than

devices disclosed in the prior art.

In a complementary process, an advantage of the embodiment over the prior art is that there is no requirement to precisely align two doping masks (for the high dose p-type and high dose n-type implants) with respect to one another, and there is thus no risk of high leakage diodes being fabricated.

The second embodiment combines this invention with that described in the first embodiment of invention disclosure 07026SLE. In the semiconductor island 1501 of the second embodiment shown in Figure 16, the source 1502 and drain 1504 regions are heavily n-type doped and are separated by the channel region, which lies directly above or below the gate electrode 1506 (or is sandwiched between two gate electrodes, depending on the type of TFT) and is doped weakly p-type. The channel region is extended in both directions parallel to that of the gate electrode 1506 (x direction in Figure 16), sO that it protrudes beyond the edges of the source 1502 and drain 1504. The protrusions are also extended in both directions perpendicular to the gate electrode 1506 (y direction in Figure 16). These extensions 1510 that do not lie directly above or below the gate electrode 1506 are lightly p-type doped, and are adjacent to the source 1502 or drain 1504 depending on which side of the channel they are positioned. They are thus bound on one side by the source 1502 or drain 1504, on one side by the gate electrode 1506, and on two sides by the island edge. The lightly doped regions 1510 have the same doping concentration as the channel region as they are masked from the high dose n-type implant during fabrication.

The depletion regions that form between the source/drain (1502 and 1504) and p-type regions 1510 are thus restricted in the channel length direction perpendicular to the gate electrode 1506 (y direction in Figure 16) by the amount that the semiconductor island extends beyond the gate electrode 1506.

The exact shape of the semiconductor island 1501 can change depending on the application that the TFT is intended for. If the TFT is of the type that has a channel region narrower than the area required for source and drain contact regions, then the source 1502 and drain 1504 must be extended in the x direction, leaving recesses 1702 so that the regions 1510 remain bound by the source 1502 or drain 1504 on only one side, as shown in Figure 17. This has no effect on the design of the active region of the TFT in the vicinity of the gate electrode.

This embodiment combines the advantage of the first embodiment, which is that the device can be fabricated in a low cost single channel process, with the advantages of reduced depletion region area. This reduces the reverse leakage current associated with the diodes, allowing small off-state currents to be achieved. The sensitivity of the TFT to changes in illumination and temperature, and the parasitic capacitance of the isolation diodes are also reduced.

In the third embodiment of the invention, the TFT is formed as described in either of the first two embodiments, but the isolation diodes are formed only on the drain side of the channel. Figure 18 illustrates the third embodiment for the case in which the semiconductor island has been patterned to minimise the depletion region area for a TFT that has a channel region that is narrower than the source 1502 and drain 1504 in the contact regions. The p-regions 1510 exist only on the drain 1504 side of the device. At the source 1502 end, the channel underneath the gate electrode 1506 has the same width as the heavily n-type doped source 1502, being extended in width (x direction in Figure 18) underneath the gate electrode 1506 to accommodate the p-regions 1510 on the drain 1504 side. In Figure 18, there is a recess 1702 between the weakly p-type doped regions 1510 and the drain 1504 width (x direction) extensions so that the regions 1510 are only bound by the drain 1504 on one side. The TFT could also be constructed without the recesses 1702, in which case the weakly doped p-type regions 1510 would be bound by the drain 1504 on two sides.

For many applications the current through the channel of the TFT is always in the same direction (i.e. the drain is always at a lower potential for the inversion carriers than the source). In this case, there is no need to include isolation diodes on the source side of the channel. The advantage of including isolation diodes only on the drain side of the channel is that the detrimental effects associated with the diode depletion regions are further reduced.

In the fourth embodiment of the invention, the TFT is formed as described in any of the previous three embodiments, with the addition of lightly doped drain (LDD) structures 1902 as shown in Figure 19. For an nTFT, LDD takes the form of additional n-type regions inserted between the heavily doped source 1502 and drain 1504 regions and the p-type channel region, adjacent and self-aligned to the gate electrode 1506. The LDD structures may extend beyond the p-type regions 1510 in the direction perpendicular to the gate electrode (y direction) or need not extend so far, as illustrated in Figure 20. LDD structures may be formed on both sides of the channel or only on the drain 1504 side, depending on the application of the TFT.

This embodiment combines the advantages of a TFT with isolation diodes that can be fabricated in a low cost single channel process and LDD structures. If the TFT is fabricated with a semiconductor island 1501 patterned as illustrated in Figure 19, the advantages of minimised isolation diode depletion regions can also be provided.

In the fifth embodiment, the TFT is formed as described in any of the first three embodiments, with the addition of gate overlapped drain (GOLD) structures 2002, as shown in Figure 20. In the case of an nTFT, GOLD takes the form of additional n-type regions 2002 inserted between the heavily doped source 1502 and drain 1504 regions and the p-type channel that is underneath the gate electrode 1506. In contrast to LDD, GOLD structures are formed underneath the gate electrode 1506. They may also be employed on both sides of the channel or only on the drain 1504 side, depending on the application of the TFT.

The fifth embodiment combines the advantages of isolation diodes that can be fabricated in a low cost single channel process and GOLD structures. If the TFT is fabricated with a semiconductor island 1501 patterned as illustrated in Figure 20, the advantages of minimised isolation diode depletion regions can also be provided.

In the sixth embodiment, the TFT is formed as described in any of the previous five embodiments but includes two or more gate electrodes 1506, as shown in Figure 21.

The region(s) 2102 between gate electrodes 1506 has doping of the same polarity and concentration as the source 1502 and drain 1504 regions, and may also include LDD regions as described in the fourth embodiment if required. Semiconductor island extensions with weak p-type doping 1510 may be employed on both sides (as illustrated in Figure 21) or only on the drain 1504 side of each gate electrode, as described in the third embodiment.

The TFT may be fabricated according to the second embodiment so that the semiconductor island is patterned to minimise the areas of the depletion regions that form between weakly p-type regions 1510 and source 1502 ordrain 1504 regions, as illustrated in Figure 22.

TFTs with multiple gate electrodes are useful when there is a requirement to minimise off-state leakage. The sixth embodiment combines the advantages of isolation diodes that can be fabricated in a low cost single channel process with the reduced off-state leakage due to the employment of multiple gates.

If the TFT is fabricated with a patterned semiconductor island 1501 as illustrated in Figure 22, the advantages of minimised isolation diode depletion regions can also be incorporated.

In the seventh embodiment, the TFT is formed with the isolation region on one side (in the x direction) only. The isolation region is as described in any of embodiments one to three inclusive. In Figure 23 the isolation region has been drawn as described in the second embodiment, so that it is only on the drain 1504 side of the gate electrode 1506. On the other side of the TFT (in the x direction), the channel region underneath the gate electrode 1506 is extended in the x direction. A body contact region 2302 is then placed adjacent to this extended region so that it extends beyond the gate electrode 1506 in they direction and is contacted by a metal electrode. In practice, region 2302 will likely extend as far as the limit of the source 1502 or drain 1504 (depending on which side of the gate electrode 1506 it is positioned), since the requirement for it to be contacted with an electrode will dictate that the same minimum amount of semiconductor material is present. The body contact region 2302 has the same doping concentration and type as the channel region underneath the gate electrode 1506. The body contact region 2302 is grounded in order to prevent the kink effect that may be observed when the channel region of the TFT is floating.

The seventh embodiment may be combined with LDD or GOLD structures, as disclosed in the fourth and fifth embodiments.

Because this embodiment incorporates a contact to the TFT body, the channel potential may be controlled to reduce undesirable operation such as the kink effect.

The seventh embodiment enjoys the advantages of a body contact, whilst reducing consumed area as far as possible by employing an isolation diode on the other side of the channel, which may be minimised according to the second embodiment. The TFT may be fabricated in a low cost single channel process.

The problem with leakage at the island edges can equally affect pTFTs and nTFTs.

The TFT may therefore be formed as described in any of the previous embodiments but the polarity of every doping region may be reversed with the relative doping concentrations remaining the same. This provides a pTFT, which is suitable for fabrication in a low cost single channel pTFT fabrication process.

Claims

CLAIMS: 1. A thin film transistor formed in an island of semiconductor material having at least one edge and being disposed on an insulating substrate, the transistor comprising: a source region of a first conductivity type and a first doping concentration; a drain region of the first conductivity type and a second doping concentration; a first channel of a second conductivity type opposite the first conductivity type and a third doping concentration less than each of the first and second concentrations, the first channel extending in a first direction, parallel to a main conduction path, between the source and drain regions; a first insulated gate extending in a second direction substantially perpendicular to the first direction and substantially overlapping the first channel; and a first isolation diode which comprises a region of the second conductivity type and the third concentration extending in the first direction from the first channel by less than the length of the drain region in the first direction and in the second direction from a first edge of the drain region, the region of the first diode being bounded by the first channel, the drain region and the at least one edge.
2. A transistor as claimed in claim 1, comprising a second isolation diode which comprises a region of the second conductivity type and the third concentration extending in the first direction from the first channel by less than the length of the drain region in the first direction, and in the second direction from a second edge of the drain region, the region of the second diode being bounded by the first channel, the drain region and the at least one edge.
3. A transistor as claimed in claim 1 or 2, comprising third and fourth isolation diodes which comprise regions of the second conductivity type and the third concentration extending in the first direction from the first channel by less than the length of the source region in the first direction and in the second direction from first and second edges, respectively, of the source region, the regions of the third and fourth diodes being bounded by the first channel, the source region and the at least one edge.
4. A transistor as claimed in any one of the preceding claims, comprising a second insulated gate overlapping the first insulated gate with the first channel disposed therebetween.
5. A transistor as claimed in any one of the preceding claims, comprising a second channel overlapped by at least one further insulated gate and provided with at least one further isolation diode.
6. A transistor as claimed in any one of the preceding claims, in which each of the source and drain regions is connected to the first channel by a respective region of reduced width in the second direction.
7. A transistor as claimed in claim 6, in which the or each diode is separated in the first direction from a portion of the source or drain of unreduced width by a recess in the semiconductor island.
8. A transistor as claimed in any one of the preceding claims, in which at least one of source and drain regions is connected to the first or second channel by a region of the first conductivity type and of a fourth doping concentration less than the first or second concentration.
9. A transistor claimed in claim 8, in which the region of the first conductivity type is overlapped by at least one of the gates.
10. A transistor as claimed in any one of the preceding claims, in which the first channel is connected to a body contact.
11. A transistor as claimed in any one of the preceding claims, in which the second concentration is substantially equal to the first concentration.
12. An active matrix display comprising a plurality of transistors, each as claimed in any one of the preceding claims.