WO2001046989A2 - Decoupling capacitors for thin gate oxides - Google Patents

Decoupling capacitors for thin gate oxides Download PDF

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Publication number
WO2001046989A2
WO2001046989A2 PCT/US2000/031352 US0031352W WO0146989A2 WO 2001046989 A2 WO2001046989 A2 WO 2001046989A2 US 0031352 W US0031352 W US 0031352W WO 0146989 A2 WO0146989 A2 WO 0146989A2
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WO
WIPO (PCT)
Prior art keywords
die
voltage
source
drain regions
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/031352
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English (en)
French (fr)
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WO2001046989A3 (en
Inventor
Ali Keshavarzi
Vivek K. De
Tanay Karnik
Rajendran Nair
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Priority to GB0215177A priority Critical patent/GB2374462B/en
Priority to HK02108392.5A priority patent/HK1046776B/zh
Priority to JP2001547425A priority patent/JP4954413B2/ja
Priority to DE10085347T priority patent/DE10085347B4/de
Priority to AU30726/01A priority patent/AU3072601A/en
Publication of WO2001046989A2 publication Critical patent/WO2001046989A2/en
Publication of WO2001046989A3 publication Critical patent/WO2001046989A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to integrated circuits and, more particularly, to decoupling capacitors in integrated circuits.
  • Decoupling capacitors are used in integrated circuit (IC) design for noise decoupling. Indeed, they are heavily used in virtually all IC's.
  • One type of semiconductor capacitor is called a MOS-C or metal oxide semiconductor capacitor.
  • the MOS-C has two terminals separated by a dielectric region (which includes at least an insulator, such as gate oxide). One of the terminals is the gate and the other is the body (and perhaps source and drain diffusions).
  • Another type of semiconductor capacitor is using a field effect transistor (FET) such as an n-channel metal oxide semiconductor FET (NMOSFET) or a p-channel metal oxide semiconductor FET (NMOSFET).
  • FET field effect transistor
  • NMOSFET n-channel metal oxide semiconductor FET
  • NMOSFET p-channel metal oxide semiconductor FET
  • the terminals are separated by a dielectric (which includes at least an insulator, such as gate oxide).
  • a dielectric which includes at least an insulator, such as gate oxide.
  • decoupling capacitors such as a capacitor sandwiched in between two metal lines with a high dielectric constant insulator are also possible.
  • the material challenge and integration in today's MOS technology will be very difficult.
  • C the capacitance C
  • A the area
  • d the distance.
  • the current decoupling capacitors structures have voltages applied to keep the MOS-C in inversion resulting in maximum per unit area capacitance value, with good high frequency response time, and low series resistance.
  • gate oxide thickness also scales in order to maintain transistors with good drive current capabilities and a good short channel behavior. As gate oxides continue to scale (e.g., below 30A), this capacitive configuration results in high leakage conduction through oxide (e.g., elevated tunneling leakage).
  • the invention includes a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage.
  • a semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage.
  • n+ gate poly and n+ source/drain regions in an n-body including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body.
  • the power supply voltage may have a larger absolute value than does a flatband voltage.
  • FIG. 1 is a schematic cross-sectional representation of a prior art capacitor.
  • FIG. 2 is a graphical representation of a capacitance v. gate-to-body voltage for capacitors with n-bodies with z zero work function.
  • FIG. 3 is a graphical representation of a capacitance v. gate-to-body voltage for capacitors with n-bodies with a non-zero work function.
  • FIG. 4 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 5 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 6 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 7 is a graphical representation of a capacitance v. gate-to-body voltage for capacitors with p-bodies with a zero work function.
  • FIG. 8 is a graphical representation of a capacitance v. gate-to-body voltage for capacitors with p-bodies with a non-zero work function.
  • FIG. 9 is a schematic cross-sectional representation of a prior art capacitor.
  • FIG. 10 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 1 1 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 12 is a schematic cross-sectional representation of a capacitor according to some embodiments of the invention.
  • FIG. 13 is a block diagram representation of a die with a capacitor according to some embodiments of the invention.
  • FIG. 14 is a block diagram representation of a die with a capacitor and voltage circuitry according to some embodiments of the invention.
  • the invention involves operating semiconductor capacitors (transistor or MOS- C) in a depletion mode to reduce leakage through the insulator (e.g., gate oxide).
  • a depletion mode reduces the capacitance per area.
  • the area may be made bigger, which is undesirable.
  • the inventors noticed that by operating in the depletion mode, the number of carriers is smaller, so there will be a smaller amount of tunneling in the gate oxide and hence less leakage.
  • the idea is to move away from using a MOS-C capacitor derived from a MOS transistor structure operating in inversion mode.
  • the alternative suggestion is to use a capacitor structure using the gate oxide as an insulator operating in depletion mode. Effective capacitance reduces by about 25% (approximated) while leakage reduces by approximately a factor of 100 for approximately a IV power supply technology. Capacitance reduction is observable in the C-V curve as the capacitor is biased in a depletion mode (close to accumulation region). The leakage reduction is due to the fact that we have less carriers in depleted channel under the gate oxide to tunnel through the thin gate oxide.
  • the Q-factor of such capacitor will be similar to a MOS transistor cap in inversion specially if we do not rely on minority carrier generation and recombination to provide the carriers need to respond to the AC signal superimposed on the decap.
  • a prior art PMOS transistor capacitor 10 includes a p- substrate, n-well, a p+ source S, a p+ drain D, p+ polysilicon gate electrode (poly) G, and an n+ body tap BT for a body B.
  • transistor capacitor 10 is called a ⁇ +/p+ cap on n-body (n-well), where the first p+ signifies the poly type and the second ⁇ + signifies the type of the S/D regions. Note that in the case of a capacitive structure is not particularly meaningful to call one diffusion region a source and the other a drain, but it is done for convenience in nomenclature.
  • Transistor capacitor 10 has voltage applied as follows: the body voltage Vb is at the power supply voltage Vcc (sometimes called Vdd), the source and drain voltages Vs and Vd are both Vcc, and the gate voltage V G and the p-substrate are both at ground (called Vss or 0).
  • Vg is tied to Vss. In some embodiments, however, G might not be tied to Vss and might be a nonzero and non-Vcc value.
  • FIG. 2 illustrates a capacitance vs. gate-to-body voltage V GB curve for n-body (e.g., n-well) capacitive structures with a zero work function because the poly and body have the same type.
  • n-body e.g., n-well
  • a drain and source voltage may be the same as the body voltage.
  • the curve is intended to only show general relationships, not precise values or shapes. The actual curve could look somewhat different. Further, the shape of the curve may change at different frequencies. As can be seen, the capacitance is higher in accumulation and inversion and is lower in depletion.
  • Vt is a threshold voltage.
  • accumulation mode occurs when 0 ⁇ V GB
  • depletion mode occurs when -Vt ⁇ V GB ⁇
  • inversion mode occurs when V GB ⁇ -Vt.
  • FIG. 3 illustrates a capacitance vs. gate-to-body voltage V GB curve for n-body capacitive structures with a non-zero work function (non-zero flat band voltage V FB .) because the poly and body have a different type.
  • the curve is intended to only show general relationships, not precise values or shapes. The actual curve could look somewhat different. Further, the shape of the curve may change at different frequencies. As can be seen, the capacitance is higher in accumulation and inversion and is lower in depletion.
  • V FB for a heavily doped poly is approximately 1.0 volts.
  • accumulation mode occurs when V FB ⁇ V GB
  • depletion mode occurs when -Vt ⁇ V GB ⁇ V FB
  • inversion mode occurs when V GB ⁇ -Vt. Note that the relative distance between -Vt and 0 and between 0 and V FB between 0 and Vt is not intended to be restrictive on actual values of V FB or Vt, which may vary from embodiment to embodiment.
  • transistor capacitor 10 of FIG. 1 The curve of FIG. 3 would apply because there is an n-body and the poly and body have different types, so there is a non-zero work function.
  • the flatband voltage (V FB ) of this structure is approximately IV.
  • V GB -Vcc, which is more negative than is - Vt. Therefore, transistor capacitor 10 is in the inversion mode (more specifically, the channel is in inversion because it includes holes which are an opposite type of the body). Accordingly, it has a very high (perhaps a maximum) capacitance per unit area, very good frequency response and low series resistance. However, it also has leakage through gate oxide, especially for thin gate oxides is also high (perhaps a maximum).
  • Vcc should be greater than Vt for this decap configuration.
  • the capacitance as a function of frequency and resistance in series with the cap (for displacement current) are representative of the Q-factor of the decap.
  • the flatband voltage (V FB ) is about IV (not zero) for the PMOS cap in inversion because p+ poly gate and n-body.
  • FIG. 4 illustrates a MOS-C 40 according to some embodiments of the invention.
  • MOS metal oxide semiconductor
  • MOS-C 40 is designated n+/n+ on n-body, according to the above described nomenclature (i.e., poly is n+, S/D is n+).
  • Vg is Vcc and S/D/B are at 0 (Vss). The curve of FIG. 2 will apply because an n-well is used and the poly and body have the same type.
  • V FB of MOS-C 40 is 0V.
  • V GB Vcc, so MOS-C 40 is in the accumulation mode (the channel is accumulated by electrons, which are the same type as the body). With the configuration of FIG. 4, it may be desirable to allow such a layout (drawing n-poly on n-well) in design tools.
  • MOS-C 40 works with all Vcc values. It has high (good) capacitance per unit area at slightly lower leakage. It has £;ood frequency response and low series resistance.
  • FIG. 5 illustrates MOS-C 50 according to some embodiments of the invention.
  • MOS-C 40 is designated p+/n+ on n-body, according to the above described nomenclature.
  • Vg is Vcc and S/D/B are at 0 (Vss). The curve of FIG. 3 will apply because an n-well is used and the poly and body have a different type.
  • V FB of MOS-C 50 is approximately IV.
  • V GB Vcc. If Vcc > V FB , then MOS-C 50 is in the accumulation mode (channel accumulates) and if MOS-C ⁇ V FB , then MOS-C 40 is in the depletion mode (channel depletes).
  • Vcc V FB
  • Vcc V FB
  • MOS-C 50 has lower capacitance per unit area but with much lower leakage because of the depletion mode (there are fewer carriers to leak). It has good frequency response, but may have high series resistance. Note that the structure resembles the buried channel MOS transistor structure.
  • FIG. 6 illustrates a PMOS transistor capacitor 60 MOS-C 60 according to some embodiments of the invention.
  • Transistor capacitor 60 is designated p+/p+ on n-body, according to the above described nomenclature.
  • Vg is Vcc and S/D/B are at 0 (Vss) (opposite of FIG. 1). The curve of FIG. 3 will apply because an n-well is used and the poly and body have a different type.
  • V FB of MOS-C 50 is approximately IV.
  • V GB Vcc. If Vcc > V FB , then MOS-C 60 is in the accumulation mode (channel accumulates) and if MOS-C ⁇ V FB , then MOS-C 60 is in the depletion mode (channel depletes).
  • Vcc is less than V FB so that MOS-C 60 will be in the depletion mode and leakage will be reduced.
  • MOS-C 60 has lower capacitance per unit area but with much lower leakage because of the depletion mode (there are fewer carriers to leak). However, frequency response and series resistance may be an issue.
  • Decoupling capacitors with p-body The following describe examples of transistors and MOS-C capacitive structures with p-bodies (p-well or p-substrate). Note that although p-wells are shown the body could be just the p-substrate. Further, the substrate could be an n-type with a p-well.
  • FIG. 7 illustrates a capacitance vs. gate-to-body voltage V GB curve for p-body capacitive structures with a zero work function because the poly and body have the same type.
  • the curve is intended to only show general relationships, not precise values or shapes. The actual curve could look somewhat different. Further, the shape of the curve may change at different frequencies.
  • the capacitance is higher in accumulation and inversion and is lower in depletion. Generally, although the boundaries between accumulation, depletion, and inversion modes may be inexact, accumulation mode occurs when V GB ⁇ 0, depletion mode occurs when 0 ⁇ V GB ⁇ Vt, and inversion mode occurs when V GB > Vt.
  • FIG. 8 illustrates a capacitance vs. gate-to-body voltage V GB curve for p-body capacitive structures with a non-zero work function (non-zero flat band voltage V FB .) because the poly and body have a different type.
  • the curve is intended to only show general relationships, not precise values or shapes. The actual curve could look somewhat different. Further, the shape of the curve may change at different frequencies. As can be seen, the capacitance is higher in accumulation and inversion and is lower in depletion.
  • V FB for a heavily doped poly is approximately 1.0 volts (although it is in the negative region of the curve).
  • accumulation mode occurs when V GB ⁇ - V FB (e.g., -lv)
  • depletion mode occurs when -V FB ⁇ V GB ⁇ Vt
  • inversion mode occurs when Vt ⁇ V GB .
  • the relative distance between -V FB and 0 and between 0 and Vt is not intended to be restrictive on actual values of V FB or Vt, which may vary from embodiment to embodiment.
  • FIG. 9 illustrates a prior art NMOS transistor capacitor 90 designated is designated n+/n+ on p-body, according to the above described nomenclature.
  • it is a p-body is a p-substrate, but it could be a p-well on an n-substrate or a p-well in a p-substrate.
  • Vg Vcc and S/D B are 0 (Vss). Since the poly and body have a different type, the curve of FIG. 8 is used.
  • V GB Vcc. On curve 8, Vcc is greater than Vt, so transistor capacitor 90 is operating in inversion mode (the channel is in inversion).
  • Decap 90 does not require a triple well process and uses no special layout requirements. It has very high (perhaps a maximum) capacitance per unit area, very good frequency response and low series resistance. The main issue is that leakage through gate oxide specially for thin gate oxides is also high (perhaps a maximum). Vcc should be greater than Vt for this decap configuration.
  • capacitor 100 includes an n-body or other insulator between the p-well and p-substrate. The purpose is to prevent the Vcc voltage from influencing the voltage of the substrate or other bodies.
  • Decap 100 works with all Vcc values. It has high (good) capacitance per unit area at slightly lower leakage. It has good frequency response and low series resistance.
  • FIG. 11 illustrates a MOS-C capacitor 110 with a n+/p+ on p-body configuration, according to the above-described nomenclature. Although a p-well is illustrated it is not necessary.
  • V GB -Vcc. If Vcc > V FB (-Vcc ⁇ -V FB ), then capacitor 110 would be in accumulation mode (channel would be accumulated). If Vcc ⁇ V FB (-Vcc > -V FB ), then capacitor 110 would be in depletion mode (channel would be depleted).
  • capacitor 1 10 includes an n-body or other insulator between the p-well and p-substrate. Capacitor 110 has lower capacitance per unit area at much lower leakage. It has good frequency response, but high series resistance.
  • capacitor 120 If Vcc > V FB (-Vcc ⁇ -V FB ), then capacitor 120 would be in accumulation mode (channel would be accumulated). If Vcc ⁇ V FB (-Vcc > -V FB ), then capacitor 120 would be in depletion mode (channel would be depleted). To help with leakage, in some embodiments, the depletion mode is used. In some embodiments, capacitor 120 includes an n-body or other insulator between the p-well and p-substrate. Leakage is good (lower) in this configuration. However, frequency response and series resistance may be an issue. This configuration may require a triple well process.
  • FIG. 13 illustrates a die 130 in which capacitors (e.g., capacitor 134) including one or more of the configurations described herein may be included.
  • Die 130 may be any of a various types of electrical devices including a microprocessor, DSP (digital signal processor), embedded controller, ASIC (application specific integrated circuit), and communication chip.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • a die 140 includes capacitor 134 (which is representative of one or more of the various capacitors described therein).
  • Die 140 includes voltage circuitry 142, which can provide the voltage(s) for one or more of the body, gate, and source/dr in to provide a desired capacitance level. Changing the body voltage may make a capa ;itor have a forward or reverse body bias. Note that Vt changes as the body bias changes. There may also be a feedback mechanism to obtain a desired capacitance level.
  • capacitance may be reduced by approximately 25%, while leakage reduces by approximately a factor of 100 for approximately a IV power supply technology.
  • Capacitance reduction is observable in the C-V curve as the capacitor is biased in a depletion mode (close to accumulation region).
  • the leakage reduction is due to there being fewer carriers in depleted channel under the gate oxide to tunnel through the thin gate oxide.
  • the Q-factor of such capacitor will be similar to a MOS transistor cap in inversion specially if we do not rely on minority carrier generation and recombination to provide the carriers need to respond to the AC signal superimposed on the decap.
  • the invention accordingly supports additional supply voltage scaling and development of process technologies for low voltage, high performance and low power CMOS circuits.
  • Our proposed solution is compatible with current processing technology.
  • the invention may be used in connection with SOI (silicon on insulator) configurations.
  • FETs other than MOSFETs could be used. Although the illustrated embodiments include enhancement mode transistors, depletion mode transistors could be used with modifications to the circuit which would be apparent to those skilled in the art having the benefit of this disclosure.
  • p+/p+ on N-Well means a capacitor with p+ poly and p+ S/D regions on N-Well
  • V FB - 1 V used for Vcc column
  • TW May use triple well to insulate body of capacitor

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PCT/US2000/031352 1999-12-22 2000-11-13 Decoupling capacitors for thin gate oxides Ceased WO2001046989A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB0215177A GB2374462B (en) 1999-12-22 2000-11-13 Decoupling capacitors for thin gate oxides
HK02108392.5A HK1046776B (zh) 1999-12-22 2000-11-13 供用於簿栅氧化物的退耦电容器
JP2001547425A JP4954413B2 (ja) 1999-12-22 2000-11-13 薄いゲート酸化膜用デカップリング・キャパシタ
DE10085347T DE10085347B4 (de) 1999-12-22 2000-11-13 Verwendung einer MOS-Struktur als Entstörkondensator bei dünnen Gate-Oxiden
AU30726/01A AU3072601A (en) 1999-12-22 2000-11-13 Decoupling capacitors for thin gate oxides

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/469,406 US6828638B2 (en) 1999-12-22 1999-12-22 Decoupling capacitors for thin gate oxides
US09/469,406 1999-12-22

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WO2001046989A2 true WO2001046989A2 (en) 2001-06-28
WO2001046989A3 WO2001046989A3 (en) 2002-05-10

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US (1) US6828638B2 (enExample)
JP (1) JP4954413B2 (enExample)
KR (1) KR100532208B1 (enExample)
AU (1) AU3072601A (enExample)
DE (1) DE10085347B4 (enExample)
GB (1) GB2374462B (enExample)
HK (1) HK1046776B (enExample)
WO (1) WO2001046989A2 (enExample)

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US6828638B2 (en) 2004-12-07
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DE10085347T1 (de) 2003-01-30
GB2374462B (en) 2004-05-26
JP4954413B2 (ja) 2012-06-13
GB0215177D0 (en) 2002-08-07
DE10085347B4 (de) 2009-04-09
HK1046776B (zh) 2004-12-03
HK1046776A1 (en) 2003-01-24
KR20020089311A (ko) 2002-11-29
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GB2374462A (en) 2002-10-16
JP2004501501A (ja) 2004-01-15

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