WO2001020465A2 - Circuit de synchronisation - Google Patents

Circuit de synchronisation Download PDF

Info

Publication number
WO2001020465A2
WO2001020465A2 PCT/TR2000/000050 TR0000050W WO0120465A2 WO 2001020465 A2 WO2001020465 A2 WO 2001020465A2 TR 0000050 W TR0000050 W TR 0000050W WO 0120465 A2 WO0120465 A2 WO 0120465A2
Authority
WO
WIPO (PCT)
Prior art keywords
boards
microprocessors
board
synchroniser
circuit
Prior art date
Application number
PCT/TR2000/000050
Other languages
English (en)
Other versions
WO2001020465A3 (fr
Inventor
Omer Aydin
Atilla Tanyeli
Ismail Hakki Topcu
Ozgur Kayalar
Original Assignee
Netas Northern Electric Telecommunication A.S.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Netas Northern Electric Telecommunication A.S. filed Critical Netas Northern Electric Telecommunication A.S.
Priority to GB0208703A priority Critical patent/GB2371390B/en
Priority to AU76989/00A priority patent/AU7698900A/en
Publication of WO2001020465A2 publication Critical patent/WO2001020465A2/fr
Publication of WO2001020465A3 publication Critical patent/WO2001020465A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level

Definitions

  • This invention relates to an Integrated Circuit wherein it provides synchronised operation of two identical digital boards which contain microprocessors, and thereby renders the system continuous by putting the other board into operation when probable errors occur, and one of the boards stops operation
  • the synchroniser circuit of this invention has been designed to be utilised in a system with a standby microprocessor board with the aim of enhancing the system security and making the users as less influenced as possible by the errors probable to occur
  • a system has been designed with this purpose wherein a standby is present of the microprocessor board to be taken as standby
  • the circuit performed according to the invention allows each board to access to each other's memories It produces the necessary signals to start the synchronised operation of the boards It allows the microprocessors on both boards to have a synchronised operation on a command interpretation basis to provide synchronised operation It determines the probable incompatibilities by comparing the address and data buses of both microprocessors during the synchronised operation It reports the incompatibility to both microprocessors by a break signal It allows the microprocessors to read the address and data bus values of an incompatibility by writing the said values on an internal log
  • the structure of the standby boards and the synchroniser circuit in the system will be better understood from the following figures
  • Figure 1 A block diagram showing the standby structure of synchronised operating digital boards with microprocessors
  • FIG. 2 A block diagram of the synchroniser circuit
  • Figure 3 A block diagram showing the flow diagram of the synchronised circuit
  • FIG. 1 A block diagram of a standby operating system is given in Figure 1 With this respect, two boards characterised as a main board (A) and a standby board (B) are embodied in Figure 1
  • the main board (A) and the standby board (B) are exactly identical
  • the main board (A) receives all of the input signals coming from the system and produces the output signals that are required for the system Identical to the main board (A), the board (B) as a standby receives simultaneously the same signals and produces simultaneously the same output signals
  • the output signals that the main board (A) and the standby board (B) produce are passed through buffer circuits (2) before they are sent to the system These circuits allow the signals to be transmitted or to be interrupted Outputs of buffer circuits on the main board (A) and on the standby board (B) are in the form of short circuit to each other At the same time, since only one board is allowed to drive the signals, the output signals shall be driven only by the main board (A) or by the standby board (B)
  • the buffer circuits (2) of the main board (A) stop to transmit the output signals and the standby board (B) starts operating, so the output signals are started to be driven by the standby board (B)
  • the process where buffer circuits (2) transmit or interrupt the output signals is controlled by the synchroniser circuit (3)
  • a path (bus) which is characterised as a standby bus (C) is present between the main board (A) and the standby board (
  • the synchroniser circuit (1 ) is designed so that both microprocessor boards are capable to access to and read and write on each other's memories (5) when an error is determined With this characteristic, the main board (A) and the standby boards (B) are able to send and receive messages to and from each other This characteristic provides great facility to the system in determining the errors and the following operation mode
  • the main board (A) and the standby board (B) stop the synchronised operation to determine the error
  • the main board (A) and the standby board (B) operate independently to determine the cause of the error, i e they are not synchronised during that process If both boards are in a position to continue the synchronised operation after the error determination they report this to the synchroniser circuit (3) present both on its own-board and on the other board by the standby bus (C) It goes to a determined address to pass to the synchronised operation and waits the necessary signals to pass where these signals come from the synchroniser circuit (3) Afterwards the process of which board is to drive the output signals is determined by the synchroniser circuits (3) present on the main board (A) and on the standby board (B) and it sends the necessary signals to microprocessors (1 ) to start the synchronised operation The microprocessors (3) receiving the signals from the synchroniser circuit (1 ) to pass to the synchronised operation start the synchronised operation once again
  • a terminal may be connected externally to the microprocessor boards in the system or some software may be transferred from an external system as well
  • a standard serial communication interface RS232 is present preferably on both boards in the system
  • data which come from the RS232 units of any boards have to be carried to both boards while synchronised operation is effective
  • Another feature of the synchroniser board (3) is that it is capable to transmit the data -received by the RS232 units of the main board (A) or of the standby board (B)- to both boards In case the RS232 units of both boards are tried to be operated during the synchronised operation, the data received by the main board (A) are transmitted to both boards by the synchroniser circuit (3), but those received by the standby board (B) are not transmitted to the boards
  • the user may take one of the main (A) and standby (B) boards in the system out of operation and if the main board (A) is required to be taken out, this request is reported to the synchroniser circuit (3) by activating a key in front of the board
  • the synchroniser board (3) puts the standby board (B) into operation if the standby operating board is operating well, and the main board (A) starts operating in place of the standby board (B) and the standby board (B) starts operating in place of the main board (A)
  • the user may put the main board (A) in the standby mode out of operation as a result of this process
  • FIG. 2 A block diagram of the synchroniser circuit is given in Figure 2
  • the microprocessor (1 ) sees its synchroniser circuit (3) as a peripheral unit and reports its own-requests to the synchroniser circuit (3) by the microprocessor interface (3a) present in the synchroniser circuit (3)
  • the encoder (3aa) in the interface (3a) selects the logs (3ab) the microprocessor (1) shall condition and/or the content of those logs (3ab, 3ca, 3cc) it shall read By conditioning the selected logs (3ab) it operates the synchroniser circuit (3) according to its own-requests
  • the microprocessor gains access to the logs showing the source of the break signals and to the logs (3ab, 3ca, 3cc) present in the comparison circuit (3c) where the address and data values of the incompatibility are saved by reading the content of said logs (3ab, 3ca, 3cc) through the interface (3a)
  • the main and standby assigning block (3d) in the synchroniser circuit (3) determines one of the boards in the system to operate in the main mode and the other to operate in the standby mode In other words, this block performs the controlling process of the buffer circuit in the boards
  • the controlling process is provided by the control the status mach ⁇ ne_2 (3da) in the block and the buffer circuit control logic (3db) perform on the buffer circuits in the board by the signals they receive
  • assigning software control may be performed Since a board fails in the tests if this board is defective it is assigned as a standby in the system Depending on the error of the board, the software allows the system to pass to synchronised operation or not
  • the logs content and the entire memory areas of both boards in the system have to be identical before synchronised operation is started Therefore the synchroniser circuit (3) allows both boards to access to each other's memories (5) This is to say that one of the identical boards is capable to perform reading and writing on other's memory (5)
  • RS232 (3b) block on the synchroniser circuit (3) controls the RS232 ports on the boards It transmits the data received by the main board RS232 to both boards simultaneously during the synchronised operation By transmitting the same data to the main and the standby boards through the RS232 port during the synchronised operation, the boards are kept in a synchronised mode And when the boards operate in an independent mode, the RS232 ports also operate independently

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un circuit intégré destiné au fonctionnement synchrone de deux cartes numériques identiques comprenant des microprocesseurs. Ce circuit permet à chaque carte d'accéder aux mémoires (5) de l'autre carte, produit les signaux nécessaires à la mise en oeuvre du fonctionnement synchronisé des cartes, permet un fonctionnement synchronisé des microprocesseurs (1) pour chaque traduction de commande. Ce circuit détermine en outre les incompatibilités probables en comparant l'adresse et les bus (7, 8) de données des deux microprocesseurs (1) pendant le fonctionnement synchronisé, rapporte cette incompatibilité aux deux microprocesseurs (1) par un signal d'interruption, et permet aux microprocesseurs (1) de lire les valeurs d'adresse et des bus (7, 8) de données associées à une incompatibilité par l'inscription de ces valeurs dans un journal interne.
PCT/TR2000/000050 1999-09-17 2000-09-18 Circuit de synchronisation WO2001020465A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0208703A GB2371390B (en) 1999-09-17 2000-09-18 Synchroniser circuit
AU76989/00A AU7698900A (en) 1999-09-17 2000-09-18 Synchronizer circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TR1999/02280A TR199902280A2 (xx) 1999-09-17 1999-09-17 Eş zamanlama devresi.
TR99/02280 1999-09-17

Publications (2)

Publication Number Publication Date
WO2001020465A2 true WO2001020465A2 (fr) 2001-03-22
WO2001020465A3 WO2001020465A3 (fr) 2001-12-27

Family

ID=21622162

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/TR2000/000050 WO2001020465A2 (fr) 1999-09-17 2000-09-18 Circuit de synchronisation

Country Status (4)

Country Link
AU (1) AU7698900A (fr)
GB (1) GB2371390B (fr)
TR (1) TR199902280A2 (fr)
WO (1) WO2001020465A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1262872A3 (fr) * 2001-05-10 2007-11-07 Siemens Aktiengesellschaft Interface de synchronisation d'un Maitre-CPU et d'une Réserve-CPU

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
FR2561410A1 (fr) * 1984-03-13 1985-09-20 Merlin Gerin Commande de process associe a deux automates programmables redondants
WO1986002475A1 (fr) * 1984-10-17 1986-04-24 American Telephone & Telegraph Company Procede et agencement d'ordonnancement des operations d'un multiprocesseur dans un systeme multiprocesseur
EP0315303A2 (fr) * 1987-09-04 1989-05-10 Digital Equipment Corporation Système à calculateur tolérant les fautes, doublé, à vérification d'erreur
US5862502A (en) * 1993-12-02 1999-01-19 Itt Automotive Europe Gmbh Circuit arrangement for safety-critical control systems

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
FR2561410A1 (fr) * 1984-03-13 1985-09-20 Merlin Gerin Commande de process associe a deux automates programmables redondants
WO1986002475A1 (fr) * 1984-10-17 1986-04-24 American Telephone & Telegraph Company Procede et agencement d'ordonnancement des operations d'un multiprocesseur dans un systeme multiprocesseur
EP0315303A2 (fr) * 1987-09-04 1989-05-10 Digital Equipment Corporation Système à calculateur tolérant les fautes, doublé, à vérification d'erreur
US5862502A (en) * 1993-12-02 1999-01-19 Itt Automotive Europe Gmbh Circuit arrangement for safety-critical control systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1262872A3 (fr) * 2001-05-10 2007-11-07 Siemens Aktiengesellschaft Interface de synchronisation d'un Maitre-CPU et d'une Réserve-CPU

Also Published As

Publication number Publication date
AU7698900A (en) 2001-04-17
TR199902280A2 (xx) 2001-02-21
GB2371390A (en) 2002-07-24
WO2001020465A3 (fr) 2001-12-27
GB2371390B (en) 2004-07-14
GB0208703D0 (en) 2002-05-29

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