WO2001017014A1 - Dispositif de cellules memoires et procede de realisation - Google Patents

Dispositif de cellules memoires et procede de realisation Download PDF

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Publication number
WO2001017014A1
WO2001017014A1 PCT/DE2000/002218 DE0002218W WO0117014A1 WO 2001017014 A1 WO2001017014 A1 WO 2001017014A1 DE 0002218 W DE0002218 W DE 0002218W WO 0117014 A1 WO0117014 A1 WO 0117014A1
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WO
WIPO (PCT)
Prior art keywords
trench
capacitor electrode
layer
electrode
memory cell
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PCT/DE2000/002218
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German (de)
English (en)
Inventor
Bernhard Sell
Josef Willer
Dirk Schumann
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Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Publication of WO2001017014A1 publication Critical patent/WO2001017014A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

Definitions

  • a one-transistor memory cell comprises a read-out transistor and a storage capacitor.
  • the information is stored in the storage capacitor in the form of an electrical charge, which represents a logical variable, 0 or 1.
  • the storage capacitor must have a minimum capacitance for safe storage of the charge and simultaneous differentiability of the information read out. The lower limit for the capacitance of the storage capacitor is currently seen at 25 fF.
  • the required area of the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor must be maintained.
  • both the read-out transistor and the storage capacitor were implemented as planar components. From the 4 MBit memory generation onwards, a further reduction in the area of the memory cell was achieved by a three-dimensional arrangement of the read transistor and memory capacitor.
  • One possibility is to implement the storage capacitor in a trench (see, for example, BK Ya ada etal, Proc. Intern. Electronic Devices and Materials IEDM 85, p. 702 ff).
  • the electrodes of the storage capacitor act as a diffusion region adjoining the wall of the trench and a doped polysilicon filling which is located in the trench.
  • the electrodes of the storage capacitor are thus along the surface of the Trench arranged.
  • the effective area of the storage capacitor, on which the capacitance depends is increased compared to the space requirement for the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench.
  • Trench can further increase the packing density.
  • the enlargement of the depth of the trench is, however, limited for technological reasons.
  • the invention is based on the problem of specifying a memory cell arrangement with memory cells, each of which has a storage capacitor and a selection transistor, in which the storage capacitor is arranged on a trench and, with a constant cross-sectional area and depth of the trench, has an increased capacitance in comparison with the prior art , Furthermore, a method for producing such a memory cell arrangement is to be specified.
  • the memory cells each have a storage capacitor and a selection transistor.
  • the storage capacitor comprises a lower capacitor electrode, a capacitor dielectric and an upper capacitor electrode, which are at least partially arranged in a trench.
  • the lower capacitor electrode is adjacent to a wall of the trench.
  • At least one of the capacitor electrodes is designed as a metallic electrode. This prevents the formation of a depletion zone in the capacitor electrode designed as a metallic electrode, which leads to an increase in the specific capacitance. This measure also has the advantage that the electrode resistance of the capacitor electrode designed as a metallic electrode is reduced.
  • the metallic electrode is preferably formed from tungsten silicide, tungsten, tungsten nitride, ruthenium or ruthenium oxide, since these metals can be introduced into the trench by CVD deposition. Furthermore, the metallic electrode can also be formed from iridium or iridu oxide.
  • Both the lower capacitor electrode and the upper capacitor electrode or both capacitor electrodes can be designed as a metallic electrode.
  • the upper capacitor electrode contains doped polysilicon.
  • the lower capacitor electrode is designed as a diffusion region adjacent to the trench.
  • a further increase in area can be achieved in that the trench extends from a main area of a semiconductor substrate into the semiconductor substrate and the trench has a smaller cross section in the area of the main area parallel to the main area than in an area of the trench facing away from the main area.
  • cavities are also avoided when filling the trench.
  • the memory cell arrangement has the advantage that it requires only minor modifications to a conventional process circuit for its manufacture.
  • the invention is explained in more detail below on the basis of exemplary embodiments which are illustrated in the figures.
  • Figure 1 to Figure 7 shows steps for producing a
  • FIG. 8 and FIG. 9 show manufacturing steps for a variant of the memory cell arrangement in which the upper capacitor electrode is designed as a metallic electrode.
  • FIGS. 10 to 13 show manufacturing steps for forming a selection transistor.
  • FIG. 14 shows a layout in an 8F 2 cell architecture.
  • FIG. 15 to FIG. 21 show steps for producing a storage capacitor in which the lower capacitor electrode is designed as a metallic electrode.
  • FIGS. 22 and 23 show steps for producing a storage capacitor in which the lower and the upper capacitor electrodes are designed as metal electrodes.
  • FIGS. 24 to 27 show manufacturing steps for a selection transistor.
  • An 8 n thick SiO 2 (oxide) layer 3 and a 220 nm thick Si 3 N 4 layer 4 are applied to a main surface 1 of a semiconductor substrate 2.
  • a 620 nm thick BPSG layer (not shown) is applied thereon.
  • the BPSG layer, the Si 3 N 4 - Layer 4 and the Si0 2 layer 3 structured in a plasma etching process with CF4 / CHF3, so that a hard mask is formed.
  • this hard mask as an etching mask, trenches 5 are etched into the main surface 1 in a further plasma etching process using HBr / NF 3 .
  • the BPSG layer is subsequently removed by wet etching with H2SO4 / HF.
  • the trenches 5 have a depth of 7 ⁇ m, a width of 100 ⁇ 250 nm and a mutual spacing of 100 nm.
  • a 10 nm thick SiO 2 layer 6 is subsequently produced by thermal oxidation and covers at least the walls of the trenches 5.
  • a polysilicon filling 7 is produced in the trenches 5, the surface of which is 1100 nm below the main surface 1 is arranged. The chemical mechanical polishing can be omitted if necessary.
  • a 10 nm thick SiO 2 layer 8 is formed on the surface of the polysilicon filling 7 by thermal oxidation.
  • Si 3 N 4 layer is deposited in a CVD process and selectively etched to SiO 2 with CHF 3 in an anisotropic plasma etching process. This creates 5 Si 3 N 4 spacers 9 above the polysilicon filling 7 on the flanks of the trenches.
  • the Si0 2 layer 8 is removed in a wet chemical etching step using NH 4 F / HF, which attacks SiO 2 selectively to form Si 3 N 4 and silicon.
  • the etching time is such that approximately 25 nm of SiO 2 are removed.
  • undercuts occur in the surface of the polysilicon filling 7, in which the side walls of the trenches 5 adjacent to the semiconductor substrate 2 are exposed (see FIG. 2).
  • the etching time for this anisotopic etching step is dimensioned such that 5 nm Si 3 N 4 are etched away.
  • SF 6 is then used to selectively etch polysilicon to Si 3 N 4 and Si0 2 .
  • the polysilicon filling 7 is removed from the trench 5 in each case.
  • the exposed part of the Si0 2 layer 6 is removed by etching with NH 4 F / HF.
  • the etching time is dimensioned so that 10 nm Si0 2 are etched.
  • An isotropic etching step with ammonia is then carried out, in which silicon is selectively etched to nitride.
  • the etching time is dimensioned so that 20 nm silicon are etched.
  • the cross section of the trenches 5 in the lower region of the trenches 5, ie in the region facing away from the main surface 1, is widened by 40 nm (see FIG. 3).
  • an arsenic-doped silicate glass layer By depositing an arsenic-doped silicate glass layer in a layer thickness of 50 nm and a TEOS-Si0 2 layer in a thickness of 20 nm and a subsequent tempering step at 1000 degrees Celsius, 120 seconds is achieved by diffusion out of the arsenic-doped silicate glass layer in the semiconductor substrate 2, an n + -doped region 11, which acts as the lower capacitor electrode of a single capacitor in the finished memory cell arrangement, is formed.
  • the lower capacitor electrodes of adjacent capacitors are connected to one another via the n + -doped region 11.
  • gas phase doping can also be carried out, for example with the following parameters: 900 ° C., 3 Torr tributylarsine (TBA) [33 percent], 12 min.
  • the Si 3 N 4 filling 10 and the Si 3 N 4 spacer 9 act as a diffusion barrier, so that the n + -doped region 11 is delimited approximately 1000 nm below the main surface 1.
  • the arsenic-doped silicate glass layer and the TEOS-Si0 2 layer are removed.
  • the Si 3 N 4 is attacked selectively to Si 2 silicon and the etching time is such that 15 nm Si 3 N 4 are etched, the Si 3 N 4 filling 10 and the Si 3 N 4 spacer 9 removed (see Figure 4).
  • a 5 nm thick dielectric layer 12 is subsequently deposited, which contains Si 2 and Si 3 N 4 .
  • the dielectric layer 12 contains Al2O3 (aluminum oxide), T1O2
  • Ta2 ⁇ 5 tantalum oxide
  • a 30 nm thick tungsten silicide layer 13 is deposited by CVD deposition
  • tungsten silicide is then selectively etched to Si 3 N 4 and the dielectric layer 12. This creates an upper capacitor electrode 15 made of tungsten silicide (see FIG. 5).
  • the remaining free space m is provided in the trench 5 by depositing a 70 nm thick polysilicon layer and chemical-mechanical polishing down to the surface of the S 3 N 4 layer 4 with a polysilicon filling 16 (see Figure 6).
  • etching step with SF 6 the polysilicon filling 16 is etched back under the main surface 1 by 100 nm.
  • a S 3 N 4 attacking etching step with HF / ethylene glycol follows, in which nitride is etched. With the help of NH 4 F / HF, exposed parts of the dielectric layer 12 and the SiO 2 layer 6 are removed (see FIG. 7). After a thermal oxidation (Sac ⁇ ficial oxidation) is followed by an implantation with phosphorus with a dose of 2 x 10 13 cm ⁇ 2 and an energy of 10 keV to form a ⁇ -doped region 17 which in the upper region of the trench 5 to the main surface 1 borders.
  • the depth of the n + -doped region 17 is such that between the basic doping of the semiconductor substrate 2 adjoins the surface of the trench 5 in the n + -doped region 17 and the n + -doped region 11 (see FIG. 7).
  • the Si0 2 generated before the implantation is subsequently removed again.
  • the trench 5 is essentially filled with a polysilicon filling 18 by deposition of polysilicon and anisotropic etching with SF 6 .
  • the polysilicon fillings 16, 18 are in situ doped with arsenic during the deposition. As a result, the polysilicon fillings 16, 18 act as a connection structure between the upper capacitor electrode 15 and the n ⁇ -doped region 17.
  • the n "-doped region 17 is connected to a source / drain region of a selection transistor in the further production process.
  • a 20 nm thick tungsten silicide layer 15 'and then a 50 nm thick polysilicon layer 16' can first be applied to the structure, as shown in FIG. 6 is shown, can be deposited (see FIG. 8).
  • the tungsten silicide layer 15 ', the polysilicon layer 16', the Si0 2 layer 6 and the dielectric layer 12 are etched back 100 nm below the main surface 1. This creates an upper capacitor electrode 15 '', the doped over the height of the n + region 11 protrudes, and a polysilicon fill 16 '', the remaining free space of the trench 5 within the upper capacitor electrode 15 'fills (see Figure 9)'.
  • the polysilicon filling 18 is formed by depositing 80 nm polysilicon and chemical-mechanical polishing down to the surface of the Si 3 N layer 4.
  • the polysilicon filling 18 is etched up to the main surface 1 by etching with SF 6 .
  • isolation structures 20 are subsequently created which laterally delimit active areas (see FIG. 10).
  • a photolithographically generated mask (not shown) is formed which covers the active areas.
  • a non-selective etching step with CHF 3 / N / NF 3 follows, in which silicon, tungsten silicide, Si0 2 and polysilicon is etched. The etching time is set so that 200 nm polysilicon are etched. After removal of the photoresist mask with 0 2 / N 2 and wet chemical etching of the dielectric layer 12 at a depth of 3 nm, an oxidation is carried out and 5 nm SiN 4 is deposited.
  • source / drain regions 28 are generated for selection transistors.
  • the implantation is carried out with phosphorus with an energy of 25 keV and a dose of 3 x 10 13 cm -2 .
  • Si 3 N 4 spacers 29 are produced on the flanks of the gate electrodes 26 and the Si 3 N 4 layer 25.
  • An oxynitride layer 30 is subsequently deposited over the entire surface in a layer thickness of 23 nm. This is followed by the deposition of a BPSG layer 31 with a thickness of 550 nm. In a tempering step at 850 ° C., the BPSG layer 31 is blown over. A planar surface is produced by chemical mechanical polishing, in which the oxynitride layer 30 acts as an etching stop (see FIG. 12).
  • An SiO 2 layer 32 with a layer thickness of 450 nm is formed over the whole area by TEOS deposition (see FIG. 13).
  • contact holes 33 to source / drain regions 28 are opened.
  • the contact holes 33 are each opened to the source / drain region of a selection transistor which is not in contact with the n + -doped region 17.
  • a photolithographically produced mask (not shown) is used to open the contact holes 33.
  • the etching is carried out with 0 2 / C 4 F 8 / CO.
  • the oxynitride layer 30 acts as an etch stop. To complete the contact holes 33, the oxynitride layer 30 is removed with 0 2 / CHF 3 .
  • the contact holes 33 are provided with polysilicon fillings 34 by in situ-doped deposition of polysilicon and etching back of the polysilicon with CF 4 / SF 6 (see FIG. 13).
  • the SiO 2 layer 32 is formed in the region of the periphery removed by etching with CF 4 / CHF 3 and an HDD implantation is carried out for transistors in the periphery.
  • bit lines BL After the formation of a photolithographically generated mask, the course of strip-shaped bit lines BL, which run parallel to one another and which run perpendicular to the word lines WL, etching takes place in the SiO 2 layer 32 with CF 4 / CHF 3 . After removing the mask with 0 2 / N 2 , the bit lines are generated by depositing titanium and tungsten and then chemical-mechanical polishing.
  • wiring levels are formed in a known manner.
  • the memory cell arrangement has a memory capacitor arranged in one of the trenches 5 and a planar selection transistor for each memory cell.
  • a space requirement of 8F 2 is required per memory cell, where F is the smallest structure size that can be produced in the respective technology.
  • the layout of the memory cell arrangement is shown in FIG.
  • the bit lines BL run in the form of strips and parallel to one another, the width of the bit lines BL in each case F and their mutual spacing likewise being F.
  • the word lines WL which likewise have a width of F and a mutual spacing of F, run perpendicular to this.
  • Active areas A are arranged below the bit lines BL, two word lines WL crossing above each active area.
  • the active areas A are arranged offset from each other below adjacent bit lines BL.
  • a bit line contact BLK is arranged in the middle of the active areas A, which enables an electrical connection between the respective bit line BL and the active area A.
  • the trenches 5 are arranged below the word lines WL. The widening of the trenches 5 in the lower area is entered as a dotted contour and provided with the reference symbol 5 '.
  • At the crossing point between one of the Bit lines BL and one of the word lines WL each have the gate electrode 26 of the associated selection transistor arranged (see FIG. 14).
  • the active regions A each extend between two trenches 5. They comprise two selection transistors which are connected to the associated bit line BL via a common bit line contact BLK. Depending on which of the word lines WL is driven, the information is read out of the storage capacitor which is arranged in one of the trenches 5 or the other of the trenches 5.
  • an SiO 2 layer 43 with a thickness of 8 nm and an SiN 4 layer 44 with a thickness of 220 nm are applied to a main surface 41 of a semiconductor substrate 42 made of monocrystalline silicon.
  • a BPSG layer with a thickness of 620 nm is deposited thereon (not shown).
  • the BPSG layer, the Si 3 N 4 layer 44 and the SiO 2 layer 43 are structured by plasma etching with CF 4 / CHF 3 .
  • a trench 45 is formed using the BPSG layer as a hard mask by plasma etching with HBr / NF per memory cell.
  • the trench 45 has a depth of 7 ⁇ m and a width of 100 nm ⁇ 250 nm (see FIG. 15).
  • the BPSG layer is removed by wet chemical etching with H 2 S0 4 / HF.
  • a SiO 2 layer 46 with a layer thickness of 10 nm is formed by thermal oxidation and covers at least the walls of the trenches 45.
  • a 70 nm thick polysilicon layer from which a polysilicon filling 47 is formed by chemical mechanical polishing down to the surface of the Si 3 N 4 layer 44 and etching with SF 6 , which is arranged 1100 nm below the main surface 41 is.
  • a 10 nm thick SiO 2 layer 48 is formed by oxidation.
  • Si 3 N 4 By CVD deposition of a 10 nm thick Si 3 N 4 layer and anisotropic plasma etching with CHF 3 , Si 3 N 4 being selectively etched to Si0 2 , 47 Si 3 N 4 spacers 49 are produced above the polysilicon filling (see FIG. 15 ).
  • the Si0 2 layer 48 and thereby exposed parts of the SiO 2 layer 46 are removed by wet chemical etching of SiO 2 selectively to Si 3 N 4 and silicon with NH 4 F / HF.
  • the etching time is set so that 25 nm Si0 2 are etched.
  • CVD deposition of a 5 nm Si 3 N layer and anisotropic etching with CHF 3 the etching time being set in such a way that 5 nm Si 3 N 4 are etched, undercuts resulting from the wet chemical oxide etching with an Si 3 N 4 - Filling 50 filled (see Figure 16).
  • the polysilicon filling 47 is subsequently removed selectively to Si 3 N 4 and Si0 2 .
  • the exposed part of the SiO 2 layer 46 is removed by wet chemical etching with NH 4 F / HF.
  • the cross section of the trenches 45 below the Si 3 N 4 spacer 49 and the Si 3 N 4 filling 50 is widened by isotropic etching with ammonia, silicon being attacked selectively to Si 3 N 4 .
  • the etching time is set so that 20 nm
  • Silicon are etched. This means that the cross section of the respective trench 45 is widened by 40 nm (see FIG. 17).
  • the etching time is set so that 15 nm Si 3 N 4 are etched.
  • a 30 nm thick, arsenic-doped tungsten silicide layer 51 is produced by in situ-doped deposition of tungsten silicide (see FIG. 18).
  • the trenches 45 are provided with a lacquer filling 52 in the lower region, in that the cross section of the trenches 45 has been widened by the isotropic silicon etching.
  • the height of the resist filling 52 is adjusted by etching with N 2/0.
  • lower capacitor electrodes 53 are formed in the trenches 45 by structuring the tungsten silicide layer 51.
  • the lower capacitor electrodes 53 are each arranged along the surface of the respective trench 45 in the region of the widening. Parts of the arsenic-doped tungsten silicide layer 51 which are arranged above the widened cross section of the respective trench 55 or which are arranged on the surface of the silicon nitride layer 44 are removed in the process (see FIG. 19). Subsequently, the paint filling 52 is removed with 0 2 / N 2 .
  • the dielectric layer 54 contains SiO 2 and Si 3 N 4 or the alternative dielectrics listed in connection with the first exemplary embodiment and serves as a capacitor dielectric in the finished memory cell arrangement.
  • a tempering step at 1100 degrees Celsius, 60 seconds and chemical-mechanical polishing of the polysilicon layer down to the surface of the Si 3 N 4 layer 44, an n + is formed by diffusion out of the lower capacitor electrode 53 doped region 55, which connects the adjacent lower capacitor electrodes 53 to one another, and a polysilicon filling 56 is formed by structuring the polysilicon layer (see FIG. 20).
  • the polysilicon filling 56 is etched back by 100 nm below the main surface 41 by etching with SF 6 .
  • etching with SF 6 There follows an Si 3 N 4 etching with HF / ethylene glycol, in which 10 nm Si 3 N 4 are etched and an etching with NH 4 F / HF, with which Si0 2 and dielectric material are etched.
  • an implantation is carried out in which a Area 57 is formed in the side wall of each trench 45 in the area of the main surface 41 (see Figure 21).
  • Free space remaining in the respective trench 45 above the polysilicon filling 56 is filled with a polysilicon filling 58 by depositing msitu-doped polysilicon and scratching the polysilicon with SF b .
  • the polysilicon filling 56 acts as an upper capacitor electrode in the finished storage capacitor.
  • the polysilicon filling 58 acts as a connection structure between the n + -doped region 57 and the polysilicon filling 56, which acts as an upper capacitor electrode.
  • a 20 nm thick tungsten silicide layer 59 and then a 30 nm thick, msitu-doped polysilicon layer 60 can be deposited (see FIG. 22).
  • the polysilicon layer 60 is healed and the N + -doped region 55 is formed by diffusion out of the arsenic-doped tungsten-silicon layer 51, which interconnects the lower capacitor electrodes 53 connects (see Figure 22).
  • the tungsten silicide layer 59 and the polysilicon layer 60 are structured by chemical-mechanical polishing down to the surface of the Si 3 N 4 layer 44. Subsequently, HCI / CI2 / NF3 polysilicon, tungsten silicide and Si0 2 are selectively etched to Si 3 N 4 . The etching rates of S1O 2 and polysilicon are somewhat higher than that of tungsten silicide.
  • HF / ethylene glycol are 10 nm Si 3 N 4 etched.
  • the surface of the semiconductor substrate 42 is exposed in the upper region of the trench 45.
  • the n + -doped region 57 is formed by angled phosphor implantation with an energy of 10 keV and a dose of 2 ⁇ 10 13 cm -2 (see FIG. 23).
  • a masked implantation follows to form an n-doped well (not shown).
  • the polysilicon filling 63 is etched up to the main surface 41 by etching with SF 6 .
  • Isolation structures 64 are subsequently produced which surround and thus define active areas. For this purpose, a mask is created that defines the active areas (not shown).
  • a mask is created that defines the active areas (not shown).
  • the etching time being set so that polysilicon is etched by 200 nm by removing one used in the process Lacquer mask with 0 2 / N 2 , by wet chemical etching of 3 nm dielectric layer, by oxidation and deposition of a 5 nm thick Si 3 N 4 layer and by deposition in a TEOS process of a 250 nm thick Si0 2 layer and subsequent chemical - Mechanical polishing, the insulation structures 64 are completed.
  • the Si 3 N 4 layer 44 is subsequently removed by etching in hot H 3 PO 4 and the Si0 2 layer 43 is removed by etching in DHF (dilute hydrofluoric acid) (see FIG. 24).
  • a scattering oxide is subsequently formed by a sacrificial oxidation.
  • Masks and implantations generated by photolithography are used to form n-doped wells, p-doped wells and to carry out Threshold voltage implantations in the area of the periphery and the selection transistors of the cell array (not shown in detail).
  • a p-doped well 65 with a dopant concentration of 5 ⁇ 10 ⁇ cm -3 is produced in the region of the active areas, which is intended for receiving the selection transistors (see FIG. 25).
  • a gate oxide 66 is formed in a layer thickness of 6 nm by thermal oxidation.
  • a polysilicon layer 67 and a tungsten silicide layer 68 are formed by integrated deposition.
  • the polysilicon layer 67 is doped in situ and has a thickness of 80 nm.
  • the tungsten silicide layer 68 has a thickness of 60 nm (see FIG. 25).
  • An Si 3 N 4 layer 69 is then deposited in a layer thickness of 200 nm.
  • gate electrodes comprising word lines which are stMailför ig and parallel to each other, defining the SiN 4 layers 69 with CHF 3/0 2 / CF 4, the tungsten Silicide layer 68 etched with HC1 / C1 2 / NF 3 and the polysilicon layer with HC1 / C1 2 .
  • Gate electrodes 70 are each formed from the tungsten silicide layer 68 and the polysilicon layer 67 (see FIG. 26).
  • the side walls of the gate electrodes 70 are provided with an SiO 2 layer 71 by oxidation. A masked implantation follows to form source / drain regions 72.
  • a 23 nm thick oxynitride layer 74 is subsequently deposited.
  • a planar surface is achieved by depositing a BPSG layer 75 in a layer thickness of 550 nm, flowing the BPSG layer 75 and chemical-mechanical polishing, the oxynitride layer 74 acting as an etching stop (see FIG. 26).
  • An SiO 2 layer 76 with a layer thickness of 450 nm is applied to this planar surface in a TEOS process.
  • contact holes 77 are produced in the SiO 2 layer 76, which extend to the source / drain region 72 of the selection transistors and the transistors in the periphery that do not contain the n + -doped Area 57 is connected (see Figure 27).
  • anisotropic etching is used to open the contact hole 76 with 0 2 / C 4 F 8 / CO, the oxynitride layer 74 acts as an etching stop. In the area of the contact holes 77, the oxynitride layer 74 is removed with 0 2 / CHF 3 .
  • a polysilicon filling 78 is formed in the contact holes 77 by depositing an in-situ doped polysilicon layer and anisotropic etching with CF / SF 6 (see FIG. 27).
  • CF 4 / CHF 3 is etched into the SiO 2 layer 76. Doing so. etched to a depth of 270 nm.
  • the memory cell arrangement is completed in a known manner by the formation of further wiring levels.

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Abstract

La présente invention concerne un dispositif de cellules mémoires comportant des condensateurs présentant chacun une électrode inférieure (53), un diélectrique (54) et une électrode supérieure (61), étant situés au moins partiellement dans une tranchée (45). Dans ce dispositif de cellules mémoires, au moins l'une des électrodes de condensateur (53, 61) correspond à une électrode métallique constituée en particulier de siliciure de tungstène. Le dispositif de cellules mémoires peut être réalisé avec un encombrement par cellule mémoire de 8F2.
PCT/DE2000/002218 1999-08-30 2000-07-07 Dispositif de cellules memoires et procede de realisation WO2001017014A1 (fr)

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
WO2001039256A2 (fr) * 1999-11-22 2001-05-31 Infineon Technologies Ag Procede de fabrication d'un col isolant dans un condensateur a tranchee
WO2001089284A2 (fr) * 2000-05-24 2001-11-29 Infineon Technologies North America Corp. Dispositif de tranchee de circuit integre a empilement de collier dielectrique et procede de realisation
DE10109564A1 (de) * 2001-02-28 2002-09-12 Infineon Technologies Ag Grabenkondensator und Verfahren zu seiner Herstellung
WO2003003462A2 (fr) * 2001-06-27 2003-01-09 Infineon Technologies Ag Condensateur a tranchee et son procede de production
WO2003017336A2 (fr) * 2001-08-13 2003-02-27 Amberwave Systems Corporation Condensateurs a tranchee pour memoire dynamique a acces aleatoire
DE10138981A1 (de) * 2001-08-08 2003-03-06 Infineon Technologies Ag Verfahren zur elektrochemischen Oxidation eines Halbleiter-Substrats
DE10142580A1 (de) * 2001-08-31 2003-03-27 Infineon Technologies Ag Verfahren zur Herstellung einer Grabenstrukturkondensatoreinrichtung
WO2003060994A1 (fr) * 2002-01-21 2003-07-24 Infineon Technologies Ag Cellule de memoire comprenant des couches basses temperatures dans un condensateur a tranchee
DE10217261A1 (de) * 2002-01-21 2003-08-07 Infineon Technologies Ag Speicherbaustein mit einer Speicherzelle mit Niedertemperatur-Schichten im Speichertrench und Herstellungsverfahren
US6998307B2 (en) 2001-02-26 2006-02-14 Infineon Technologies Ag Method for fabricating a storage capacitor
US7170125B2 (en) 2002-11-29 2007-01-30 Infineon Technologies Ag Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium
DE102016115008A1 (de) * 2016-08-12 2018-02-15 Infineon Technologies Dresden Gmbh Verfahren zum herstellen einer halbleitervorrichtung

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WO2001039256A2 (fr) * 1999-11-22 2001-05-31 Infineon Technologies Ag Procede de fabrication d'un col isolant dans un condensateur a tranchee
WO2001039256A3 (fr) * 1999-11-22 2002-01-17 Infineon Technologies Ag Procede de fabrication d'un col isolant dans un condensateur a tranchee
WO2001089284A3 (fr) * 2000-05-24 2002-05-30 Infineon Technologies Corp Dispositif de tranchee de circuit integre a empilement de collier dielectrique et procede de realisation
WO2001089284A2 (fr) * 2000-05-24 2001-11-29 Infineon Technologies North America Corp. Dispositif de tranchee de circuit integre a empilement de collier dielectrique et procede de realisation
US6998307B2 (en) 2001-02-26 2006-02-14 Infineon Technologies Ag Method for fabricating a storage capacitor
DE10109564A1 (de) * 2001-02-28 2002-09-12 Infineon Technologies Ag Grabenkondensator und Verfahren zu seiner Herstellung
US6987295B2 (en) 2001-02-28 2006-01-17 Infineon Technologies Ag Trench capacitor and method for fabricating the trench capacitor
WO2003003462A2 (fr) * 2001-06-27 2003-01-09 Infineon Technologies Ag Condensateur a tranchee et son procede de production
WO2003003462A3 (fr) * 2001-06-27 2003-03-20 Infineon Technologies Ag Condensateur a tranchee et son procede de production
US7339224B2 (en) 2001-06-27 2008-03-04 Infineon Technologies Ag Trench capacitor and corresponding method of production
DE10138981A1 (de) * 2001-08-08 2003-03-06 Infineon Technologies Ag Verfahren zur elektrochemischen Oxidation eines Halbleiter-Substrats
US6559069B2 (en) 2001-08-08 2003-05-06 Infineon Technologies Ag Process for the electrochemical oxidation of a semiconductor substrate
DE10138981B4 (de) * 2001-08-08 2005-09-08 Infineon Technologies Ag Verfahren zur Bildung von Siliziumoxid durch elektrochemische Oxidation eines Halbleiter-Substrats mit Vertiefungen
WO2003017336A2 (fr) * 2001-08-13 2003-02-27 Amberwave Systems Corporation Condensateurs a tranchee pour memoire dynamique a acces aleatoire
US6891209B2 (en) 2001-08-13 2005-05-10 Amberwave Systems Corporation Dynamic random access memory trench capacitors
WO2003017336A3 (fr) * 2001-08-13 2003-09-04 Amberwave Systems Corp Condensateurs a tranchee pour memoire dynamique a acces aleatoire
US7408214B2 (en) 2001-08-13 2008-08-05 Amberwave Systems Corporation Dynamic random access memory trench capacitors
US7410861B2 (en) 2001-08-13 2008-08-12 Amberwave Systems Corporation Methods of forming dynamic random access memory trench capacitors
US8253181B2 (en) 2001-08-13 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel dynamic random access memory devices
US6693016B2 (en) 2001-08-31 2004-02-17 Infineon Technologies Ag Method of fabricating a trench-structure capacitor device
DE10142580B4 (de) * 2001-08-31 2006-07-13 Infineon Technologies Ag Verfahren zur Herstellung einer Grabenstrukturkondensatoreinrichtung
DE10142580A1 (de) * 2001-08-31 2003-03-27 Infineon Technologies Ag Verfahren zur Herstellung einer Grabenstrukturkondensatoreinrichtung
DE10217261A1 (de) * 2002-01-21 2003-08-07 Infineon Technologies Ag Speicherbaustein mit einer Speicherzelle mit Niedertemperatur-Schichten im Speichertrench und Herstellungsverfahren
WO2003060994A1 (fr) * 2002-01-21 2003-07-24 Infineon Technologies Ag Cellule de memoire comprenant des couches basses temperatures dans un condensateur a tranchee
US7170125B2 (en) 2002-11-29 2007-01-30 Infineon Technologies Ag Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium
DE102016115008A1 (de) * 2016-08-12 2018-02-15 Infineon Technologies Dresden Gmbh Verfahren zum herstellen einer halbleitervorrichtung

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