463369 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明ο ) 在動態隨機存取式記憶胞配置中幾乎只使用所謂單一 電晶體記憶胞。單一電晶體記憶胞包含一個讀出電晶體 及一個記憶電容器。資訊是以電荷之形式儲存在記憶電 容器中，這些資訊是表示邏輯値0或1。以字元線來控制 此種讀出電晶體，則可將資訊經由位元線讀出。爲了可 靠地儲存電荷且同時可區別所讀出之資訊，則此記憶電 容器必須具有一種最小容量。記憶電容器之容量下限目 前是25fF。 由於記憶體密度由一個時代至另一個時代而逐漸增 力α，則單一電晶體記憶胞所需之面積必須由·個時代至 另一個時代而逐漸減小。記憶電容器之最小容量同時必 須保持著。 直至Mb it時代爲止，讀出電晶體及記億電容器都是以 平面式組件製成。由4 Mbit記憶體時代開始，藉由讀出 電晶體及記憶電容器之三維配置已可使記憶胞之面積進 一步降低。一種可能性是以溝渠來製成記億電容器（see K Yam ad a e t a i, Proc，Intern. Elektronic Dev ices and Materia 丨 s IEDM 85，page 702 and so on)。在此種情況下， 一種鄰接於溝渠壁之擴散區以及一種摻雜之多晶矽塡料 (其位於溝渠中）是用作此記憶電容器之電極。此記憶 電容器之電極因此是沿著溝渠表面而配置。這樣即可針 對基板表面上之記憶電容器之面積需求（其對應於溝渠 之橫切面）而使此記憶電容器之有效面積（其與電容量 有關）增大。藉由溝渠之橫切面降低而使封裝密度進一 本紙張尺度遶用中S國家標準（CNS〉A4規格（210 X 297公釐） ----------- -- * I---I--訂- 1 ------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 633 6 9 A7 _____B7___ 五、發明說明（）） 步提高。但溝渠深度之增加由於技術上之原因會受到限 制。 本發明之目的是提供一種記憶胞配置，各記憶胞分別 具有一個記憶電容器及一個選擇電晶體，其中記憶電容 器配置在溝渠中目.在此種溝渠之仍然相同之橫切面和深 度中具有較先前技藝還大之電容。此外，本發明亦涉及 此種記憶胞配置之製造方法。 上述目的是以申請專利範圍第1項之記憶胞配置以及 第7項之製造方法來達成。本發明之其它形式描述在申 請專利範圍各附屬項中。 在本發明之記憶胞配置中|各記憶胞分別具有一個記 憶電容器和一個選擇電晶體。此記憶電容器包含一個下 部電極 ' 一種介電質和一個上部電極，這些電極至少一 部份是配置於溝渠中。電容器下部電極鄰接於溝渠之一 壁。電容器之至少一個電極因此是以金屬電極構成。這 樣可防止空乏區（depletion area)形成於此種以金屬電極 構成之電容器電極中，這樣可使比（specific)電容提高。 此外，這樣所具有之優點是：此種以金屬電極構成之電 容器電極之電極電阻可降低。 此種金屬電極較佳是由矽化鎢、鎢' 氮化鎢、釕（Ru) 或氧化釕所構成，這是因爲這些金屬可藉由CVD沈積而 引入溝渠中。此外，此種金屬電極亦可由銥或氧化銥所 構成。 電容器下部電極、上部電極或此二個電極亦可由金屬 -4- 本紙張尺度適用令國國家標準<CNS)A4規格（210 X 297公釐） -------------裝--------訂--------- ί請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6 33 6 9 A7 ____B7_ 五、發明說明（> ) 電極所構成。 若電容器只有下部電極電由金屬電極所構成 > 則本發 明之範圍包括：電容器上部電極含有摻雜之多晶矽。 若電容器只有上部電極電由金屬電極所構成，則本發 明之範圍包括：電容器下部電極可由一種鄰接於溝渠之 擴散區所構成。 進--步之面積擴大可以下述方式達成：溝渠是由半導 體基板之一個主面向內延伸至半導體基板中且此溝渠在 平行於此主面之主面區域中所具有之橫切面較在此溝渠 之遠離此主面之區域中者還小。在此種構成中，在對此 溝渠進行塡入時另外亦可防止中空區之肜成。 此種記億胞配置之優點是：其只須對傳統之製程作極 爲微小之修改即可製成此記憶胞。 本發明以下將依據顯示在圖式中之實施例作詳述° _ 式簡單說明： 第1至7圖--種記億胞配置之製造步驟，其中此電容 器之上部電極是以金屬電極構成。 第8、9圖此記憶胞配置之一種變型之製造步驟’其中 此電容器之上部電極是以金屬電極構成。 第1 0至1 3圖形成一種選擇電晶體所用之製逍步驟° 第1 4圖一種8F2晶胞結構中之佈局（layout)。 第15至21圖一種記憶電容器之製造步驟，其中此電 容器之下部電極是以金屬電極構成- 第22、23圖一種記憶電容器之製造步驟’其中此電容 本紙張尺度適用中國國家標準（CNS)A4規格（210* 297公釐） —-------------HE—---訂--------1 (諸先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 3 3 6 9 A/ _ B7 五、發明說明（4 ) 器之下部電極和上部電極是以金屬電極構成。 第24至27圖一種選擇電晶體之製造步驟。 在半導體基板2之主面1上施加8nm厚之Si 02 (氧化 物）層3和22〇η«ι厚之Si3N4層4。其上施加620nm厚之 B P S G層（未顯示）》 使用一種微影術所產生之遮罩（未顯示）以CF4/CHF3 在電漿蝕刻過程中對BPSG層、Si3N4層4和8丨02層3進 行結構化以便形成一種硬遮罩。使用此種硬遮罩作爲蝕 刻遮罩而在另一電漿蝕刻過程中以Η B r/N F 3來對面1中 之溝渠5進行蝕刻。然後藉由濕式蝕刻以H2 S04/HF使 BPSG層被去除。 溝渠5之深度是7pm，寬度是100x250nm，相互間之 距離是1OOnm 。 然後藉由熱氧化作用而產生一種10nm厚之Si02層6, 其至少覆蓋此溝渠5之壁。藉由沈積7 0 n m厚之多晶矽， 化學-機械式抛光直至Si3N4層4之表面且以SF6來對多 晶矽層進行回（back)蝕刻而在溝渠5中產生一種多晶矽 塡料7，其表面是配置在主面1下方1100 nm處。情況需 要時因此可省略化學-機械式拋光過程。藉由熱氧化作用 而在多晶砂塡料7之表面上形成一種厚度10nm之Si02 層8。 然後以CVD方法沈積一種lOnm厚之Si3N4層且以非等 向性之電漿蝕刻過程以CHF3選擇性地對Si02來對Si3N4 層作蝕刻。於是在溝渠5之側面上在多晶矽塡料7上方 -6- 本紙張尺度適用中圉國家標準（CNS)A4規輅（210 X 297公釐） -------------裝--------訂---------線 C請先間讀背面之注意事項再填寫本頁) 463369 A7 B7___ 五、發明說明（Γ ) 產生S i 3 N 4間隔層9。 f請先閱讀背面之注意事項再填寫本頁) 在濕式化學蝕刻步驟中以NH4F/HF選擇性地對Si3N4 和矽來對S i 0 2作蝕刻而使S i 0 2層8被去除。須測定此種 蝕刻時間，以便去除大約2 5 n m之S i 02。這樣就可在多晶 矽塡料7之表面上產牛··些欠（under)蝕刻區，其中可使 溝渠5之與半導體基板2相鄰之側壁裸露出來（第2圖> 藉藉CVD法使Si3N4沈積5nm之厚度且隨後以CHF3進 行非等向性之蝕刻而使這些欠蝕刻區中以S i 3 N 4層塡料 1 0塡入。須測定此種非等向性蝕刻步驟之時問，以便以 貪虫刻來去除5 n m之S i 3 N 4。 然後以SF6選擇性地對Si3N4和Si02來對多晶矽進行 蝕刻。於是此多晶矽塡料7分別由各溝渠5中去除。藉 由以N H4 F/H F來進行之蝕刻而使S i 0 2層6之裸露部份被 去除。須測定此種蝕刻時間以便去除1 〇 n m之S i 02。然後 以氣（A m m ο n i a)來進行一種等向性之軸刻步驟，其中須選 擇性地對氮化物來對矽進行飩刻。須測定此種蝕刻時間 以便去除20nm之矽。此溝渠5之橫切面於是在溝渠5之 下部區域（即，在遠離主面1之區域）中可擴大4 0 n m (第 3圖）。 經濟部智慧財產局員工消費合作社印製 藉由沈積一種50nm厚之砷-摻雜之矽酸鹽玻璃層以及 20nm厚之TE0S-Si02層以及隨後在lOOOt時退火120 秒，則由此種砷-摻雜之矽酸鹽玻璃層往外擴散至半導體 基板2中而形成一種η、摻雜區1 1此區Π ·在已製成之記 憶胞配置中用作各別電容器之下部電極。各相鄰電容器 本紙張尺度適用中國國家標準（CNS)A4現格（210 X 297公釐） 4633 6 9 as 3 6 6 5 B7 鎮精委員^"，4V ν\ί ."^是否變更原實質内^經濟部智慧財產局員工消費合作社印製 五、發明說明（k ) 之下部電極經由此》、接雜區1 I而互相連接。另一方式 是亦可進行一種氣相摻雜過程，其例如是以下述各參數 來進行：900 °(：，3托（丁〇]^)丁1^(7'1^1^¥131^11)[33%]，12 分鐘。 在砷-摻雜之矽酸鹽玻璃層往外擴散時，Si3N4塡料I 〇 和S i3 N4間隔層9用作一種擴散位障，使η + -接雜區1丨限 制於主面1下方大約]〇 〇 〇 n m處。 在以NHj/HF來選擇性地對Si;N4和矽進行齡刻步驟 中使砷-摻雜之矽酸鹽玻璃層和TEOS-Si〇2層被去除。 在以H F /乙二醇來進行之融刻步驟中，S i 3 N 4選擇性地 對Si02而被侵蝕且須測定其蝕刻期間使]5nm之 Si3N4被倉虫亥IJ 。於是可去除Si3N4塡料1 0以及S“n4間隔 層9(第4圖）。然後沈積厚度是5nm之介電質層12 (其 含有$丨02及Si3N4)»另一方式是此介電質層12含有AI2〇3 (氧化鋁）、Ti〇2、Ta205。藉由CVD沈積法而沈積30ηηι 厚之矽化鎢層Π (第4圖）。 溝渠5中所剩下之空間以光阻]4塡入且以N2/.02進行 回（back)蝕刻。然後在電漿促進式之蝕刻過程中以HCI/ C12/HF3來進行非等向性之蝕刻選擇性地對Si3N4和介電 質層1 2來對矽化鎢進行蝕刻。於是產生一種由矽化鎢所 構成之電容器上部電極15(第5圖）。 在以〇2/N 2來進行之蝕刻過程中去除上述之光阻塡料 1 4之後，溝渠5中剩餘之空間藉由沈積7 0 n m厚之多晶 矽層及化學-機械拋光至Si3N4層4之表面以設置一種多 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公髮） (請先閱讀背面之注ΐ孝項再填寫本頁) ^4--I----- 訂 --------· 4 6 33 6 9 經濟部智慧財產局員工消f合作社印製 A7 B7 五、發明說明（7 ) 晶矽塡料1 6 (第6圖）。 在以S F6來進行之鈾刻步驟中，對該多晶矽塡料1 6進 行回（b a c k )蝕刻至主面1下方丨〇 〇 n m處爲止。然後以η F / 乙二醇來進行一種S i3 N 4侵蝕性之蝕刻步驟，其中須對氮 化物進行蝕刻。藉助於NH4F/HF使介電質層12和Si02 層6之棵露的部份被去除（第7圖）。在熱氧化作用（西 牲性氧化作用）之後以劑量2 X 1 Ol3cnT2和能量1〇 kev之 磷來進行植入以形成n + -摻雜區17，此區17在溝渠5之 上部區域中鄰接於主面1。須測定此n + -摻雜區1 7之深 度’使得在η + -摻雜區1 7和η + -摻雜區1 1之間此半導體 基板2之基本摻雜區鄰接於溝渠5之表面（第7圖）。然 後又將此植入前所產生之S i 02去除。藉由多晶矽之沈積 以及以S F6來進行之非等向性蝕刻使溝渠5中以多晶矽 塡料1 8塡入。 多晶砂㈣料1 6、1 8在沈積時以碑來進行同次（i n s i t u ) 摻雜。多晶矽塡料1 6 ' 1 8在電容器上部電極1 5和η + -摻 雜區1 7之間作爲連接結構用。n + -摻雜區1 7在隨後之製 程中是與選擇電晶體之源極/汲極區相連接。 另一種不同於第7圖所示之製程之方式是，就電容器 上部電極15之低歐姆性之連接而言，首先在第6圖所示 之結構上沈積20nm厚之矽化鎢層1 5’且其上沈積50nm 厚之多晶矽層16’（第8圖）。 藉由多晶矽和矽化鎢層之化學-機械式抛光直至Si3N4 層4之表面且隨後以HCL/CI2/NF3來進行蝕刻（其中Si02 -9- ^紙張尺度巾關家標準（CNS)A4規格（210 X 297公釐） ----------丨丨-裝--------訂---------線 (請先闉讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 33 6 9 A7 B7 五、發明說明（方） 和多晶矽之蝕刻速率較矽化鎢者大）以便對矽化鎢層 1 5，'多晶矽層1 6 ·' S i 0 2層6以及主面1下方1 〇 〇 n m處 之介電質層1 2進行回蝕刻。於是產生電容器上部電極1 5 (其突出於η + -摻雜區1 1之高度上方）以及多晶矽塡料 1 6 "(其在電容器上部電極1 5 ”之內部中塡入溝渠5之剩 餘之空間中）（請參閱第9圖）。 然後類似於第7圖中所示者以FH/乙二醇進行一種 10nm之Si3N4蝕刻，一種5nm之對介電質材料之等向性 蝕刻，一種西牲性之氧化作用以及一種以磷來進行之斜 角式植入等等以便形成一種η+ -摻雜區17。在以DHF(稀 釋之氫氟酸）來去除此種植入前所形成之氧化物層之 後，藉由沈積8 Onm之多晶矽及進行化學-機慽式抛光直 至S i3N4層4之表面爲止而形成多晶矽塡料1 8。 藉助於微影術所產生之遮罩（未顯示）以及以1 . 3 M e v 之劑量1 0 u c m _2之磷來進行植入而形成一種n _摻雜之阱 1 9 (第9圓）。 藉由S F 6來進行蝕刻使多晶矽塡料1 8被蝕刻至主面1。 爲了界定一些主動區，隨後須產生一些隔離結構20， 其在側面是磷接於這些主動區（第1 〇圖）。於是形成一 種由微影術所產生之遮罩（未顯示），其覆蓋著主動區。 然後以CHF^NVNF;進行一種非選擇性之蝕刻步驟，其中 須對矽、矽化鎢、S i02和多晶矽進行蝕刻。須調整此種 貧虫刻期間’以便對200nm之多晶矽進行蝕刻。在以n2/02 去除光阻遮罩且對介電質層1 2進行濕式化學蝕刻至3 n m -1 0- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 丨丨丨111!!!裝-------訂---------線 (請先閱讀背面之注意事項再填寫本頁) A7 4633 6 9 B7__ 五、發明說明（9 ) (請先閱讀背面之注意事項再填寫本頁) 之深度之後進行一種氧化作用且沈積5 n m之S丨3 N 4。然後 以TEOS來沈積250nm厚之Si〇2°藉由化學-機械拋光直 至S i3N4層4表面，.種以熱Η3Ϊ>〇4來進行之蝕刻步驟（其 可侵蝕S i )以及一種以DHF來進行之触刻步驟（其可 侵蝕S i Ο 2 )來製成此種隔離結構2 〇且使S丨3 Ν 4層4、S i 0 2 層3被去除（第10圖）。 藉由熱氧化作用而在整面上形成一種10nm厚之雜散 氧化物（未顯示）。藉助於微影術所產生之遮罩（未顯示） 以及植入步驟而產生這些用於周邊和用於記憶胞配置之 選擇電晶體之η -摻雜阱、p -摻雜阱和導通電壓植入。特 別是形成一種Ρ-摻雜阱2 1，其配置在η-摻雜阱I 9上方 且其深度較η + -摻雜區1 7之深度還大但較η -摻雜阱i 9之 深度還小（第Π圖）。p-摻雜阱2 1所具有之摻雜物質濃 度是 5xl017cm_3。 經濟部智慧財產局員工消費合作社印f 在以D H F去除上述之雜散氧化物之後，藉由熱氧化作 用而形成60nm厚之閘極氧化物22。其上藉由積體式沈 積而形成一種多晶矽層23或矽化鎢層24。積體式沈積在 學術界中是指一種在一設備中之多層式沈積，其中矽晶 圓在各沈積步驟中不會接觸到大氣。形成80nm厚之多晶 矽層2 3和6 0 n m厚之矽化鎢層2 4 (第1 1圖）》 在沈積2〇〇nm厚之Si3N4層25之後以微影術產生' ·種 遮罩，其可界定這些條形之互相平行而延伸之字元線WL 之外形，字元線含有閘極電極。在使用此種遮罩（未顯 示）作爲蝕刻遮罩時，藉由以CHF3/02/CF4來進行之電漿 -1 1 - 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 4633 6 9 五、發明說明（、° ) 蝕刻且以HC l/C 12來對多晶矽層2 3進行蝕刻而形成閘極 電極26。然後進行-•種氧化作用，其中此閘極電極26之 側壁設有一種Si02層27(第12圖）。在使用一種由微影 術所產生之遮罩（未顯示）下以及在植入過程之各步驟 中產生各選擇電晶體之源極/汲極區2 8。植入過程是以 能量25 Kev及劑量3x1ο13 cm — 2之碟來進行》 藉由沈積35nm厚之Si02·以及以CHF3來進行之非等 向性蝕刻而在閘極電極2 6和S i 3N 4層2 5之各邊緣上產生 Si3N4間隔層29 - 然後在整面上沈積2 3 n m厚之氧化氮化物層3 0。其上 沈積550nm厚之BPSG層31。在85〇°C之退火步驟中使 B P S G層3 1融合。藉由化學-機械式拋光（其中此氧化氮 化物層3 0用作蝕刻停止層）而產生一種平坦之表面（第 1 2 圖）。 在整面上藉由TEOS沈積而形成45〇nm厚之3丨02層32 (第13圖）。在5丨02層32和BPSG層31中開啓一些至 源極/汲極區2 8之接觸孔3 3。這些接觸孔3 3分別開啓 至一種選擇電晶體之源極/汲極區，此源極/汲極區不 與η + -摻雜區1 7相接觸。爲了開啓這些接觸孔3 3 '須使 用· ·種由微影術所產生之遮罩（未顯示）。此種蝕刻是以 02/C4F8/CO來進行。該氧化氮化物層30因此用作蝕刻停 止層。爲了製成這哇接觸孔33，須以02/CHF3來去除該 氧化氮化物層3 0。 這些接觸孔33藉由同次（in situ)摻雜之多晶矽沈積以 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------- ------ 丨訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4633 6 9 \\ 月 日修正 Β7 五、發明說明（"） (請先間讀背面之注意事項再填寫本頁) 及以CF4/SF6來對多晶矽進行回蝕刻而設有多晶矽塡料 3 4 (第1 3圖）=藉助於一種由微影術所產生之遮罩（未 顯示，其覆蓋此記憶胞配置之晶胞陣列）而在周邊之區 域中藉由CF4/CHF3來進行蝕刻使Si02層32被去除且對 此周邊之各電晶體進行一種HDD植入。 在形成一種由微影術所產生之遮罩（其覆蓋條形之位 元線B L之外形，位元線互相平行而延伸且垂直於字元線 WL而延伸）之後，以〇?4/(：1^3在5丨02層32中進行一 種蝕刻。在以〇2/N2去除此遮罩之後藉由鈦和鎢之沈積以 及隨後之化學-機械式拋光而產生各條位元線。 爲了製成此種記憶胞配置，須以習知方式形成一些佈 線平面。 經濟部智慧財產局員工消費合作社印製 此種電容器及一個平面式選擇電晶體。每一記憶胞之 面積需求是8F2,其中F是以當時技術所可製成之最小之 結構大小。第1 4圖是此記憶胞配置之佈局（丨a y 〇 u t)。位 元線B L以條形方式互相平行而延伸，位元線b l之寬度 分別是F且其相互間之距離同樣是F。字元線W L.垂直於 位元線而延伸，字元線WL之寬度同樣是F且相互間之距 離也是F。主動區A配置於位元線B L下方，二條字元線 WL交叉於每一主動區上方。主動區a互相偏移地配置於 相鄰位元線BL之下方。在主動區A之中央配置一種位元 線接觸區BLK ，其可在各別位元線BL和主動區 A之間形成一種電性連接。溝渠5配置在字元線 WL下方。溝渠5在下部區中之擴張是以參考符號 -1 3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局貝工消費合作社印製 4 6 33 6 9 A7 B7 五、發明說明（<>) 51表示。在位元線BL中之一和字兀線WL中之一之間的 相交點處分別配置該所屬之選擇電晶體之閘極電極2 6 (第14圖）。 主動區A分別在二個溝渠5之間延伸°主動區A包括 二個選擇電晶體，其經由一個共用之位元線接觸區B LK 而與所屬之位元線B L相連接°依據哪一條字元線W L受 到控制而由記憶電容器（其配置在溝渠5之一中或配置 在溝渠5之另一個中）讀出資訊。 依據本發明之另一種構造，在一種單晶矽半導體基板4 之主面41上施加8nm厚之Si02層43及220nm厚之Si3N4 層4 4。其上沈積6 2 0 n m厚之B P S G層（未顯示）。藉助於 微影術所結構化之遮罩（未顯示，其界定了記憶電容器 之配置方式）以CF4/CHF3來進行之電槳蝕刻而使BPSG 層，3丨3&層44和Si02— 43被結構化。以02/N2去除此 遮罩之後使用BPSG層作爲硬遮罩以HBr/NF3來進行電漿 蝕刻而在每一個記億胞中形成一種溝渠45。此溝渠之深 度是7em且寬度是l〇〇nmx250nm (第15圖）。 藉由以H3S04/HF來進行之濕式化學蝕刻而使BPSG層 被去除。藉由熱氧化作用而形成厚度10nm之Si02層46’ 其至少覆蓋溝渠45之壁。 然後沈積7 0 // m厚之多晶矽層，由此多晶矽層藉由化 學-機械式拋光直至Si 3N4層44之表面爲止且以SF6來進 行蝕刻而形成多晶矽塡料4 7，其配置於主面4 1下方1 1 〇 〇 nm處。在多晶矽層47之表面上藉由氧化作用而形成lOnm -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------装.------訂---------線I j (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 33 6 9 A7 B7 五、發明說明（4) 厚之S i 0 2層4 8。 藉由CVD沈積10nm厚之Si3N4層以及以CHF.,來進行 之非等向性電漿蝕刻（其中須選擇性地對Si02來對Si;N4 進行蝕刻）而在多晶矽塡料4 7上方產生S i 3 N 4間隔層4 9 (第15圖）。 以NH4/HF選擇性地對Si3N4和矽來對Si02進行濕式化 學蝕刻而使S i Ο 2層4 8以及因此而裸露之此部份S i 0 2層 4 6被去除。須調整此種蝕刻期間以便蝕刻2 5 n m之S i 0 2。 藉由CVD沈積5nm之Si3N4層以及以CHF3來進行之非 等向性蝕刻（其中須調整此種蝕刻期間以便飩刻5 nm之 5 i 3N4 )而在濕式化學氧化物蝕刻中以S i 3N 4塡料5 0塡入 所產生之欠（u n d e r)蝕刻區中（第1 6圖）。 然後藉助於SF6選擇性地對Si3N4和Si02使多晶矽塡 料47被去除。藉由以NH4F/HF來進行之濕式化學蝕刻使 Si〇2層46之裸露部份被去除。以氨（ammonia)來進行等 向性蝕刻（其中選擇性地對S i 3N 4而對矽進行侵蝕）而使 溝渠45之橫切面在Si3N4間隔層49和Si3N4塡料50下 方擴展。須調整此種飽刻期間以便触刻2 0 n m之砂。即， 各別溝渠4 5之橫切面已擴展4 0 n m (第1 7圖）。 藉由以HF/乙二醇來進行之濕式化學蝕刻而選擇性地 對SiQ2和矽使Si3N4間隔層49和Si3N4塡料50被去除。 須調整此種蝕刻時間，以便蝕刻1 5 n m之S i 4。藉由矽 化鎢同次（in situ)摻雜之沈積而產生30nm厚之砷-摻雜之 矽化鎢層5 1 (第1 8圖）。 -1 5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝it-----訂---------線 {請先閱讀背面之注意事項再填寫本頁) A633 6 9 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（) 藉由光阻之沈積而使溝渠4 5在下部區（其中此溝渠4 5 之橫切面藉由等向性之矽蝕刻而擴大）中設有一種光阻 塡料52。此光阻塡料52之高度藉由以N2/02來進行之蝕 刻而被調整。藉由以H C 1 / C 12 / N F 3來進行之非等向性触刻 (其中須選擇性地對Si3N4和Si02來對矽化鎢進行蝕刻） 而在溝渠4 5中藉由矽化鎢層5 1之結構化而形成電容器 下部電極5 3。電容器下部電極5 3分別沿著各別溝渠4 5 之表面而配置在上述之擴大區中。以砷來摻雜之矽化鎢 層51之配置在各別溝渠45之已擴大之橫切面上方之此 部份或配置在氮化矽層4 4之表面上之此部份因此被去除 (第1 9圖）。然後以〇2/N2去除此光阻塡料5 2。 隨後沈積5nm厚之介電質層54，其含有Si02和Si3N4 或含有此種與第一實施例相關連而製成之另一介電質且 在已製成之記憶胞配置中用作電容器介電質》藉由沈積 70nm厚之同次摻雜之多晶矽層，在11〇〇 °C時進行退火步 驟60秒以及對此多晶矽層進行化學-機械式抛光直至 Si3N4層44之表面爲止以及藉由電容器下部電極53之往 外擴散而形成n + -摻雜區5 5(其使相鄰之電容器下部電極 5 3互相連接）且藉由多晶矽層之結構化而形成一種多晶 矽塡料5 6 (第2 0圖）。 以SF6來進行蝕刻而對此多晶矽塡料56進行回（back) 蝕刻至主面4 1下方1 0 〇 n m處。然後以H F/乙二醇來進行 Si3N4之鈾刻（其中蝕刻1 〇ηΐΏ之Si3N4 )且以MH4F/HF 來進行蝕刻（其中是對Si〇2及介電質材料進行蝕刻）。在 -1 6- 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） -------------裝-- - ---訂---------線 (請先閱讀背面之注意事項再填寫本頁} 4 6 33 6 9 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（π) 一種以西牲性氧化作用以形成雜散氧化物（未顯示）之 後進行一種植入過程，其中可在主面4 1之區域中在每--溝渠45之側壁中形成--種n + -摻雜區57 (第21圓）。各 別溝渠4 5中在多晶矽塡料5 6上方所剩下之空間藉由同 次摻雜之多晶矽之沈積以以S F 6來對此多晶矽進行回蝕 刻而以多晶矽塡料5 8塡入。多晶矽塡料5 6在已製成之 記億電容器中用作此電容器之上部電極。多晶矽塡料5 8 用作n + -摻雜區57和多晶矽塡料56 (其用作電容器之上 部電極）之間的連接結構。 爲了由矽化鎢製造電容器上部電極，則另一方式是在 沈積介電質層5 4之後沈積一種2 0 n m厚之矽化鎢層5 9且 其上又沈積3 〇 n m厚之同次摻雜之多晶矽層6 0 (第2 2 圖）。在I 1 0 0 °C時進行退火步驟60秒而使多晶矽層6 0恢 復且藉由砷摻雜之矽化鎢層5 1之往外擴散而形成n +-摻 雜區5 5，其使電容器下部電極5 3互相連接（第2 2圖）。 矽化鎢層5 9和多晶矽層6 0藉由化學-機械式拋光直至 SijNq層44之表面爲止而被結構化。然後以HCI/C12/NF3 選擇性地對Si3N4來對多晶矽、矽化鎢和Si〇2進行蝕刻。 S i Ο 2和多晶矽之蝕刻速率較矽化鎢者稍高。利用H F /乙二 醇來蝕刻lOnm之Si3N4。於是使半導體基板42之表面裸 露於溝渠45之上部區域中。然後以DHF對介電質層54 進行等向性之蝕刻。須調整此種蝕刻期間以便進行5 nm 之蝕刻。 在形成一種雜散氧化物之後，藉由一種能量是1 〇Kev I - - - - I I — I - - I I - — — — — I! — < I t I f I —1 I I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用十國國家標準（CNS)A4規格Ο10 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4633 6 9 A7 B7 五、發明說明（4) 而劑量是2xlOl3cm〃之磷之傾斜式植入而形成η、摻雜 區57 (第23圖）。 然後進行一種遮罩式植入以形成η-摻雜之阱（未顯 示）。藉由以S F ή來進行之蝕刻，使多晶矽塡料6 3被蝕刻 至主面4 1。 然後產生一些隔離結構64，其圍繞著主動區且因此而 界定了主動區。形成一種遮罩 > 其界定了各主動區（未 顯示）。藉助於CHF3/N2/NF3非選擇性地對矽，矽化鎢、 S i 02和多晶矽來進行電漿-蝕刻，其中須調整此種蝕刻時 間，以便蝕刻200nm之多晶矽，以02/N2去除所使用之 光阻遮罩，以濕式化學蝕刻3 n m之介電質層，氧化及沈 積5nm厚之Si3N4層，以TEOS方法沈横2 50nm厚之Si02 層以及隨後進行化學-機械式拋光而製成各隔離結構 64。然後以熱H3P〇4來進行蝕刻使Si3N4層44被去除且 以D H F (稀釋之氫氟酸）來進行蝕刻以去除S i Ο 2層4 3 (第24圖）。 然後藉由西牲性之氧化作用而形成一種雜散氧化物。 使用一些植入過程及微影術所產生之遮罩以形成η-摻雜 之阱，Ρ -摻雜之阱且在周邊區域中及晶胞陣列之選擇電晶 體區域（未各別地顯示）中進行各導通電壓之植入。特 別是在主動區中產生一種摻雜物質濃度5 X 1 〇17cm·3之ρ_ 摻雜阱65，其是固定用來容納各選擇電晶體（第25圖）。 在以DHF去除該雜散氧化物之後，藉由熱氧化作用而 形成6nm厚之閘極氧化物66。然後藉由積體式沈積而形 -1 8- <紙張尺度iS t關家鮮（CNS)A4規格（210 x 297公釐） ---ill---------------^ I-------- (請先閲讀背面之注意事項再填寫本頁) A7 B7 Λ6336 9 五、發明說明（7) 成多晶矽層6 7和矽化鎢層6 8。多晶矽層6 7是同次摻雜 的且具有80η πι之厚度。矽化鎢層68之厚度是68nm (第 2 5 圖）。 然後沈積200nm厚之Si3N4層69。 藉助於微影術所產生之遮罩（未顯示，其界姖了這些 含有閘極電極配置之字元線，各字兀線是條形的且互相 平行而延伸）而以CHF3/02/CF4來對Si3N4層69進行蝕 刻•因此由矽化鎢層6 8和多晶矽層6 7來分別形成閘極 電極70(第26圖）。 藉由氧化作用使閘極電極7 0之側壁設有S i 02層7 1。 然後進行一種遮罩式植入以形成源極/汲極區7 2。 在去除最後所使用之光阻遮罩之後，藉由沈積3 5 n m厚 之S i3N4層以及以c HF3來進行之非等向性蝕刻而在閘極 電極70，Si3N4層69之側面上形成Si3N4間隔層73。然 後沈積23 nm厚之氧化氮化物層74。 藉由沈積厚度550nm之BPSG層75,使BPSG層75熔 合且進行化學-機械式拋光（其中此氧化氮化物層.74用作 蝕刻停止層）而形成一種平坦之表面（第26圖）》 在此種平坦之表面上以TEO S方法而施加一種4 5 0 n m 厚之Si〇2層76 »藉助於微影術所產生之遮罩（未顯示） 而在3丨02層76中產生一些接觸孔77,這些接觸孔77到 達周邊中各選擇電晶體及各電晶體之未與n + -摻雜區57 相連接之此種源極/汲極區72(第27圖）。在以02/C4F8/ CO對此接觸孔76之開口進行非等向性蝕刻時，該氧化 -19- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） --------- ----震--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 4 633 6 9 A7 B7 五、發明說明（j) 氮化物層74用作蝕刻停止層。在接觸孔77之區域中以 〇2/CHF3來去除該氧化氮化物層74。 藉助於微影術所產生之遮罩（其覆蓋此記憶胞配置之 晶胞陣列）而在周邊區域中進行一種各電晶體所需之 H D D植入（未顯示）。 在接觸孔7 7中藉由沈積一種同次摻雜之多晶矽層以及 隨後以CH4/SF6來進行之非等向性蝕刻而形成一種多晶 矽塡料78 (第27圖）。 藉助於微影術所產生之另一遮罩（未顯示）而在 CF4/CHFj在SiCh層76中進行蝕刻，此遮罩界定了互相 平行而延伸之條形位元線之配置，位元線是垂直於字元 線而，延仲。因此可触刻至2 7 0 n m之深度。 在以〇 2 /N 2去除此種由微影術所產生之遮罩之後，沈積 鈦和鎢且藉由化學-機械式拋光法而進行結構化。於是產 生位元線79 = 此種記憶胞配置以習知之方式藉由其它佈線平面之形 成而製成。 ------------* --- 請先閱讀背面之;i意事項本頁) .. .線. 經濟部智慧財產局員工消費合作社印製 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 463369 A7 X B7 \年\\ 充 五、發明説明（) 主要元件符號說明·’ 經濟部智慧財產局員工消費合作杜印製 1 主面 2 半導體基板 3,6,8 Si02 層 4,25 Si3N4 層 5 溝渠 7,1 6,1 6 Μ 8 多晶矽塡料 9,29 Si3N4間隔層 10 Si3N4塡料 11,17 n + -摻雜區 12 介電質層 13,15s,24 矽化鎢層 14 光阻 15,15” 電容器上部電極 I6’，23 多晶矽層 19 η-摻雜阱 20 隔離結構 21 Ρ-摻雜阱 22 閘極氧化物 26 閘極電極 27,32 Si02 層 28 源極/汲極區 30 氧化氮化物層 31 BPSG 層 33 接觸孔 -21 - ----------^------1T------ C請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 463369 A7 B7 五、發明説明（π ) 經濟部智慧財產局員工消費合作社印製 34,47,5 6,5 8,6 3,7 8 多晶矽塡料 41 主面 42 半導體基板 43,46,48,7 1,76 Si02 層 44,69 Si3N4 層 45 溝渠 49,73 S i 3 N 4間隔層 50 Si3N4塡料 51,59,68 矽化鎢層 52 光阻塡料 53 電容器下部電極 54 介電質層 55,57 n + -摻雜區 60,67 多晶矽層 64 隔離結構 65 P-摻雜阱 66 閘極氧化物 70 閘極電極 Ί1 源極/汲極區 74 氧化氮化物層 77 接觸孔 79 位元線 A 主動區 BLK 位元線接觸區 WL 字元線 -22- I---------^-------1T------^ (請先閲讀背面之注意事項再蜞寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ2ίΠ公釐）463369 Consumption Cooperation by Employees of Intellectual Property Bureau, Ministry of Economic Affairs, printed by A7 B7 V. Description of the invention ο) In the dynamic random access memory cell configuration, almost only the so-called single transistor memory cell is used. A single transistor memory cell contains a readout transistor and a memory capacitor. Information is stored in a memory capacitor in the form of a charge, and this information represents a logical zero or one. The word transistor is used to control such a readout transistor, and information can be read through the bit line. In order to store the charge reliably and at the same time to distinguish the information read out, the memory capacitor must have a minimum capacity. The lower limit of the capacity of the memory capacitor is currently 25fF. As the memory density gradually increases from one era to another, the area required for a single transistor memory cell must gradually decrease from one era to another. The minimum capacity of the memory capacitor must be maintained at the same time. Until the Mb it era, readout transistors and capacitors were made of planar components. Since the era of 4 Mbit memory, the area of memory cells has been further reduced by the three-dimensional configuration of readout transistors and memory capacitors. One possibility is to use the trenches to make billion capacitors (see K Yam ad a e t a i, Proc, Intern. Elektronic Dev ices and Materia s IEDM 85, page 702 and so on). In this case, a diffusion region adjacent to the trench wall and a doped polycrystalline silicon material (located in the trench) are used as the electrodes of the memory capacitor. The electrodes of this memory capacitor are therefore arranged along the surface of the trench. In this way, the effective area of the memory capacitor (which is related to capacitance) can be increased according to the area requirement of the memory capacitor on the substrate surface (which corresponds to the cross-section of the trench). By reducing the cross-section of the trench, the packaging density is incorporated into a paper standard and used in the national S standard (CNS> A4 specification (210 X 297 mm)) ------------* I-- -I--Order- 1 ------- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 633 6 9 A7 _____B7___ V. Description of Invention ()) Step up. However, the increase in trench depth is limited due to technical reasons. The purpose of the present invention is to provide a memory cell configuration, each memory cell has a memory capacitor and a selection transistor, wherein the memory capacitor is arranged in the trench. In this trench, the cross section and depth are the same as before The skill is also big. In addition, the present invention also relates to a method for manufacturing such a memory cell configuration. The above purpose is achieved by the memory cell configuration of item 1 of the patent application scope and the manufacturing method of item 7. Other forms of the invention are described in the respective appended claims. In the memory cell configuration of the present invention, each memory cell has a memory capacitor and a selection transistor, respectively. This memory capacitor contains a lower electrode '' a dielectric and an upper electrode, and these electrodes are at least partially disposed in the trench. The lower electrode of the capacitor is adjacent to one wall of the trench. At least one electrode of the capacitor is thus constituted by a metal electrode. This prevents a depletion area from being formed in such a capacitor electrode composed of a metal electrode, which can increase specific capacitance. In addition, this has the advantage that the electrode resistance of such a capacitor electrode composed of a metal electrode can be reduced. Such metal electrodes are preferably composed of tungsten silicide, tungsten 'tungsten nitride, ruthenium (Ru) or ruthenium oxide, because these metals can be introduced into the trench by CVD deposition. In addition, such a metal electrode may be composed of iridium or iridium oxide. The capacitor's lower electrode, upper electrode or these two electrodes can also be made of metal. < CNS) A4 size (210 X 297 mm) ------------- install -------- order --------- ί Please read first Note on the back, please fill out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 33 6 9 A7 ____B7_ V. Description of Invention (>) Electrode. If only the lower electrode of the capacitor is composed of a metal electrode > the scope of the invention includes: the upper electrode of the capacitor contains doped polycrystalline silicon. If only the upper electrode of the capacitor is composed of a metal electrode, the scope of the present invention includes that the lower electrode of the capacitor may be composed of a diffusion region adjacent to the trench. The further enlargement of the area can be achieved in the following way: a trench extends inwardly from one major surface of the semiconductor substrate into the semiconductor substrate, and the cross-section of the trench in a region of the major surface parallel to the major surface is greater than here The area of the ditch far from this main face is still small. In this configuration, it is also possible to prevent the formation of a hollow area when the trench is penetrated. The advantage of this memory cell configuration is that it only needs to make very minor modifications to the traditional process to make this memory cell. The present invention will be described in detail based on the embodiments shown in the drawings below. Figures 1 to 7-Manufacturing steps of a kind of configuration with one million cells, in which the upper electrode of the capacitor is composed of a metal electrode. Figures 8 and 9 are steps of manufacturing a variation of this memory cell configuration, wherein the upper electrode of the capacitor is made of a metal electrode. Figures 10 to 13 form a kind of manufacturing steps for selecting a transistor. Figure 14 shows a layout in an 8F2 cell structure. Figures 15 to 21 of a manufacturing step of a memory capacitor, wherein the lower electrode of the capacitor is made of a metal electrode-Figures 22 and 23 of a manufacturing step of a memory capacitor 'where the paper size of this capacitor applies to Chinese National Standard (CNS) A4 Specification (210 * 297mm) —------------- HE —--- Order -------- 1 (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 3 3 6 9 A / _ B7 V. Description of the invention (4) The lower and upper electrodes of the device are made of metal electrodes. Figures 24 to 27 show a manufacturing process of a selective transistor. On the main surface 1 of the semiconductor substrate 2, a Si02 (oxide) layer 3 with a thickness of 8 nm and a Si3N4 layer 4 with a thickness of 22 nm are applied. A 620nm-thick BPSG layer (not shown) was applied on it.> A mask (not shown) created using a lithography method was used to etch the BPSG layer, Si3N4 layer 4 and 8 丨 02 layer 3 in the plasma etching process with CF4 / CHF3. Structured to form a hard mask. Using this hard mask as an etching mask, the trench 5 in the face 1 is etched with Η B r / N F 3 in another plasma etching process. The BPSG layer was then removed by wet etching with H2S04 / HF. The depth of trench 5 is 7pm, the width is 100x250nm, and the distance between them is 100nm. Then, by thermal oxidation, a 10 nm-thick SiO 2 layer 6 is generated, which covers at least the wall of the trench 5. By depositing polycrystalline silicon with a thickness of 70 nm, chemically and mechanically polishing it to the surface of the Si3N4 layer 4 and back etching the polycrystalline silicon layer with SF6, a polycrystalline silicon paste 7 is produced in the trench 5, the surface of which is configured 1100 nm below main surface 1. The chemical-mechanical polishing process can be omitted if necessary. A Si02 layer 8 having a thickness of 10 nm is formed on the surface of the polycrystalline sand aggregate 7 by thermal oxidation. Then, a SiNN layer with a thickness of 10 nm was deposited by CVD method, and the Si3N4 layer was etched selectively with CHF3 by an anisotropic plasma etching process. So on the side of the trench 5 above the polycrystalline silicon material 7-This paper size applies the Chinese National Standard (CNS) A4 Regulation (210 X 297 mm) ------------- Install -------- Order --------- Line C, please read the precautions on the back before filling this page) 463369 A7 B7___ V. Description of the invention (Γ) Generate S i 3 N 4 Spacer layer 9. f Please read the precautions on the back before filling this page.) In the wet chemical etching step, Si 3N 4 and Si are selectively etched with Si 3N 4 and silicon to etch Si 2 layer 8 to remove Si 8 layer. This etching time must be measured in order to remove Si02 of approximately 2 5 nm. In this way, an under-etched area can be produced on the surface of the polysilicon material 7, in which the side wall of the trench 5 adjacent to the semiconductor substrate 2 can be exposed (Fig. 2 > by CVD method) Si3N4 was deposited to a thickness of 5 nm and subsequently anisotropically etched with CHF3 to inject Si 3 N 4 layer material 10 into these under-etched areas. The timing of this anisotropic etching step must be determined In order to remove 5 nm of Si 3 N 4 by greedy engraving. Then Si3N4 and Si02 are selectively etched with SF6. Therefore, the polycrystalline silicon material 7 is removed from each trench 5 by using N H4 F / HF etching to remove the exposed part of the Si 0 2 layer 6. This etching time must be measured in order to remove 10 nm of Si 02. Then the gas (A mm ο nia) is used. An isotropic axial engraving step is performed in which silicon must be selectively etched with nitride. This etching time must be measured in order to remove 20 nm silicon. The cross section of this trench 5 is then in the lower region of trench 5 (That is, in an area away from the main surface 1) can be enlarged by 40 nm (Figure 3). The Intellectual Property Bureau employee consumer cooperative prints this arsenic-doped by depositing a 50nm-thick arsenic-doped silicate glass layer and a 20nm-thick TE0S-Si02 layer and then annealing at 1000t for 120 seconds. The silicate glass layer diffuses out into the semiconductor substrate 2 to form a η, doped region 1 1 This region Π is used as the lower electrode of each capacitor in the completed memory cell configuration. Each adjacent capacitor Paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 4633 6 9 as 3 6 6 5 B7 Zhenjing Committee member ^ ", 4V ν \ ί. &Quot; ^ Whether to change the original substance ^ economic Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau. V. Invention Description (k) The lower electrodes are connected to each other via this and the doping area 1 I. Another way is to perform a gas phase doping process, which is, for example, the following The parameters are described as follows: 900 ° (:, 3 Torr (but 〇) ^) but 1 ^ (7'1 ^ 1 ^ ¥ 131 ^ 11) [33%], 12 minutes. In arsenic-doped silicic acid When the salt glass layer diffuses outward, the Si3N4 material I 〇 and the Si 3 N4 spacer layer 9 serve as a diffusion barrier, limiting the η + -doped region 1 丨 to the main Below the surface 1 at about 00 nm. The arsenic-doped silicate glass layer and the TEOS-Si 2 layer were selectively subjected to the aging step of Si; N 4 and silicon with NHj / HF. In the melting step using HF / ethylene glycol, Si 3 N 4 is selectively eroded by SiO 2, and Si 3 N 4 of 5 nm must be measured during the etching process by Cangjiehai IJ. So Si3N4 material 10 and S "n4 spacer layer 9 can be removed (Figure 4). Then a dielectric layer 12 (which contains $ 丨 02 and Si3N4) with a thickness of 5nm is deposited» Another way is this dielectric Layer 12 contains AI203 (alumina), Ti02, and Ta205. A 30ηη thick tungsten silicide layer was deposited by CVD deposition method (Figure 4). The remaining space in trench 5 is photoresistive] 4 Insert and perform back etching with N2 / .02. Then use HCI / C12 / HF3 to perform anisotropic etching during plasma-assisted etching. Selectively Si3N4 and dielectric layer 1 2 to etch tungsten silicide. Thus, a capacitor upper electrode 15 (FIG. 5) composed of tungsten silicide is produced. After the above photoresist material 14 is removed in the etching process performed with 0 / N 2 , The remaining space in the trench 5 is deposited by depositing a polycrystalline silicon layer of 70 nm thickness and chemical-mechanical polishing to the surface of the Si3N4 layer 4 to set a multi-paper size applicable to the Chinese National Standard (CNS) A4 specification (210 x 297) ) (Please read the note on the back of the paper before filling out this page) ^ 4--I ----- Order -------- · 4 6 33 6 9 Intellectual Property of the Ministry of Economic Affairs A7 B7 was printed by the employee's cooperative. V. Description of the invention (7) Crystalline silicon material 16 (Figure 6). In the uranium engraving step performed with S F6, the polycrystalline silicon material 16 was backed up. ) Etching to 100 nm below the main surface 1. Then, a Si 3 N 4 aggressive etching step is performed with η F / ethylene glycol, in which the nitride must be etched. With the help of NH4F / HF The exposed portions of the dielectric layer 12 and the Si02 layer 6 were removed (Figure 7). After thermal oxidation (Western animal oxidation), planting was performed at a dose of 2 X 1 Ol3cnT2 and phosphorus at an energy of 10 kev. In order to form an n + -doped region 17, this region 17 is adjacent to the main surface 1 in the region above the trench 5. The depth of this n + -doped region 1 7 must be determined such that the n + -doped region 1 The basic doped region of the semiconductor substrate 2 between 7 and η + -doped region 1 1 is adjacent to the surface of trench 5 (FIG. 7). Then S i 02 generated before implantation is removed. By The deposition of polycrystalline silicon and the anisotropic etching with S F6 led to the infusion of polycrystalline silicon material 18 in trench 5. Polycrystalline sand material 16 and 18 were deposited during deposition. To do the same (insitu) doping. Polycrystalline silicon material 16 '1 8 is used as a connection structure between the capacitor upper electrode 15 and the η + -doped region 17. The n + -doped region 17 is The subsequent process is connected to the source / drain region of the selection transistor. Another method that is different from the process shown in FIG. 7 is that for the low-ohmic connection of the capacitor upper electrode 15, a 20 nm thick tungsten silicide layer 15 ′ is first deposited on the structure shown in FIG. 6 and A 50nm thick polycrystalline silicon layer 16 'is deposited thereon (Fig. 8). By chemical-mechanical polishing of the polycrystalline silicon and tungsten silicide layers up to the surface of the Si3N4 layer 4 and then etched with HCL / CI2 / NF3 (where Si02 -9- ^ paper size towel standard (CNS) A4 specification (210 X 297 mm) ---------- 丨 丨 -Packing -------- Order --------- Line (Please read the precautions on the back before filling in this Page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 33 6 9 A7 B7 V. Description of the invention (square) and polysilicon etch rate is higher than those of tungsten silicide) In order to the tungsten silicide layer 1 5 and 'polycrystalline silicon layer 1 6 · The Si 6 layer 6 and the dielectric layer 12 at 1000 nm below the main surface 1 are etched back. Thus, the capacitor upper electrode 15 (which protrudes above the height of the η + -doped region 1 1) and the polycrystalline silicon material 16 (quoting the remainder of the trench 5 in the capacitor upper electrode 15) are generated. (See Figure 9). Then, similar to that shown in Figure 7, a 10nm Si3N4 etch using FH / ethylene glycol, a 5nm isotropic etch on the dielectric material, and a western Animal oxidation and a beveled implantation with phosphorus etc. to form an η + -doped region 17. DHF (diluted hydrofluoric acid) was used to remove the formed After the oxide layer, a polycrystalline silicon paste 18 was formed by depositing 8 Onm polycrystalline silicon and performing chemical-mechanical polishing until the surface of the Si 3N 4 layer 4. A mask produced by lithography (not shown) And implanted with a dose of 1.3 M ev of 10 ucm _2 phosphorus to form an n _ doped well 19 (circle 9). The polycrystalline silicon material 18 was etched by SF 6 Etching to the main surface 1. In order to define some active areas, some isolation structures 20 must be subsequently created, Phosphorus is attached to these active areas on the side (Fig. 10). A mask (not shown) created by lithography is then formed, which covers the active area. Then CHF ^ NVNF; a non-selective In the etching step, silicon, tungsten silicide, Si02, and polycrystalline silicon must be etched. The period of this insect-depleting etch must be adjusted to etch 200nm polycrystalline silicon. The photoresist mask is removed at n2 / 02 and the dielectric is removed. The quality layer 12 is wet chemically etched to 3 nm -1 0- This paper size is applicable to China National Standard (CNS) A4 (210 χ 297 mm) 丨 丨 111 !!! Order --------- line (please read the notes on the back before filling this page) A7 4633 6 9 B7__ 5. Description of the invention (9) (Please read the notes on the back before filling this page) After the depth, an oxidation process was performed and S 3 N 4 was deposited at 5 nm. Then 250 nm thick Si 2 ° was deposited with TEOS by chemical-mechanical polishing to the surface of the Si 3N 4 layer 4 with a heat treatment of 3Ϊ> 4 To perform an etching step (which can etch S i) and an etching step performed with DHF (which can etch S i Ο 2) to This isolation structure 2 was made and the S 丨 3 N 4 layer 4 and S i 0 2 layer 3 were removed (Figure 10). A 10 nm-thick stray oxidation was formed on the entire surface by thermal oxidation. (Not shown). These masks (not shown) created by lithography and the implantation steps are used to generate η-doped wells and p-doped selective transistors for peripheral and memory cell configuration. Hybrid and on-voltage implants. In particular, a P-doped well 21 is formed, which is disposed above the η-doped well I 9 and has a depth greater than the depth of the η + -doped region 17 but greater than the depth of the η -doped well i 9. Still small (picture Π). The doping substance concentration of the p-doped well 21 is 5 × 1017 cm_3. After removing the above-mentioned stray oxide with D H F, the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has formed a gate oxide 22 having a thickness of 60 nm by thermal oxidation. A polycrystalline silicon layer 23 or a tungsten silicide layer 24 is formed thereon by integrated deposition. Integrated deposition in academia refers to a multilayer deposition in a device, in which the silicon crystal circle does not contact the atmosphere during each deposition step. Form 80 nm thick polycrystalline silicon layer 23 and 60 nm thick tungsten silicide layer 2 4 (Fig. 11) "After depositing a 200 nm thick Si3N4 layer 25, a photolithography is used to generate a mask, which The outer shapes of the word lines WL extending parallel to each other may be defined, and the word lines include gate electrodes. When using this type of mask (not shown) as an etching mask, the plasma is performed by using CHF3 / 02 / CF4-1 1-This paper is again applicable to China National Standard (CNS) A4 (210 X 297) (Mm) A7 B7 4633 6 9 V. Description of the invention (, °) Etching and etching the polycrystalline silicon layer 2 3 with HC 1 / C 12 to form the gate electrode 26. Then-a kind of oxidation is performed, in which a gate electrode 26 is provided with a Si02 layer 27 on its side wall (Fig. 12). The source / drain regions 28 of each selected transistor are generated using a mask (not shown) created by lithography and during each step of the implantation process. The implantation process was performed with a disk of energy 25 Kev and a dose of 3x1ο13 cm — 2 ”. By depositing 35nm thick Si02 · and anisotropic etching with CHF3, the gate electrodes 26 and Si 3N 4 A Si3N4 spacer layer 29 is formed on each edge of the layer 25-and then a 2 3 nm thick nitride oxide layer 30 is deposited on the entire surface. A 550 nm thick BPSG layer 31 is deposited thereon. The B P S G layer 31 was fused in an annealing step at 85 ° C. By chemical-mechanical polishing in which the nitride oxide layer 30 is used as an etch stop layer, a flat surface is produced (Fig. 12). A 3o02 layer 32 with a thickness of 45 nm was formed on the entire surface by TEOS deposition (Figure 13). Some contact holes 3 3 to the source / drain regions 2 8 are opened in the 5′02 layer 32 and the BPSG layer 31. These contact holes 33 are respectively opened to a source / drain region of a selective transistor, and the source / drain region is not in contact with the η + -doped region 17. To open these contact holes 3 3 ', a mask (not shown) created by lithography is used. This etching is performed at 02 / C4F8 / CO. This nitride oxide layer 30 thus functions as an etch stop layer. In order to make this wow contact hole 33, the oxide nitride layer 30 must be removed with 02 / CHF3. These contact holes 33 are deposited by in-situ doped polycrystalline silicon at -12-. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ---------- ------- 丨 Order --------- (Please read the notes on the back before filling out this page) Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4633 6 9 \\ Correction Month B7 5. Description of the invention (") (please read the precautions on the back before filling in this page) and use CF4 / SF6 to etch back the polycrystalline silicon and set the polycrystalline silicon material 3 4 (Figure 13) = with the help of A mask generated by lithography (not shown, which covers the cell array of this memory cell configuration) and is etched in the surrounding area by CF4 / CHF3 to remove the Si02 layer 32 and to the surrounding area Each transistor undergoes an HDD implant. After forming a mask generated by lithography (which covers the outer shape of the bit line BL of the strip, the bit lines extend parallel to each other and extend perpendicular to the word line WL). : 1 ^ 3 An etch is performed in 5 丨 02 layer 32. After removing this mask with 〇2 / N2, each bit line is generated by the deposition of titanium and tungsten and subsequent chemical-mechanical polishing. To make such a memory cell configuration, some wiring planes must be formed in a known way. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed this capacitor and a flat selection transistor. The area requirement of each memory cell is 8F2, of which F is the smallest structure size that can be made by the technology at that time. Figure 14 shows the layout of the memory cell configuration (丨 ay ut). The bit lines BL extend parallel to each other in a stripe manner, and the bit lines bl The width is F and the distance between them is also F. The character line W L. extends perpendicular to the bit line, and the width of the character line WL is also F and the distance between them is also F. Active area A configuration Below the bit line BL, two word lines WL cross each active Above the active area a. The active area a is arranged below the adjacent bit line BL at an offset from each other. A bit line contact area BLK is arranged in the center of the active area A, which can be located between each bit line BL and the active area A. An electrical connection is formed between them. The trench 5 is arranged below the character line WL. The expansion of the trench 5 in the lower area is based on the reference symbol 1-3 3- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (%) Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 33 6 9 A7 B7 V. Description of the invention ( < >) 51. Gate electrodes 2 6 (FIG. 14) of the respective selected transistors are arranged at the intersections between one of the bit lines BL and one of the word lines WL, respectively. The active area A extends between the two trenches 5 respectively. The active area A includes two selection transistors, which are connected to the corresponding bit line BL via a shared bit line contact area B LK. According to which word The element line WL is controlled to read information from a memory capacitor (which is arranged in one of the trenches 5 or the other of the trenches 5). According to another configuration of the present invention, an 8 nm thick Si02 layer 43 and a 220 nm thick Si3N4 layer 44 are applied on the main surface 41 of a single crystal silicon semiconductor substrate 4. A 620 nm thick BPSG layer (not shown) was deposited thereon. The BPSG layer, 3 丨 3 & layer 44 and Si02-43 were etched with the help of a lithography structured mask (not shown, which defines the configuration of the memory capacitor) by electro-paddle etching using CF4 / CHF3. Structured. After removing this mask with 02 / N2, a BPSG layer was used as a hard mask to perform plasma etching with HBr / NF3 to form a trench 45 in each cell. The depth of this trench is 7em and the width is 100nmx250nm (Figure 15). The BPSG layer was removed by wet chemical etching with H3S04 / HF. A Si02 layer 46 'having a thickness of 10 nm is formed by thermal oxidation to cover at least the wall of the trench 45. Then a polycrystalline silicon layer with a thickness of 7 0 // m is deposited, whereby the polycrystalline silicon layer is chemically and mechanically polished up to the surface of the Si 3N4 layer 44 and etched with SF6 to form a polycrystalline silicon material 4 7, which is arranged on the main surface. 4 1 at 1 100 nm. On the surface of the polycrystalline silicon layer 47, lm -14 is formed by oxidation. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm). .------ Order --------- Line I j (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 33 6 9 A7 B7 V. Description of the invention (4) Thick S i 0 2 layers 4 8 S was generated over polycrystalline silicon material 4 7 by depositing a 10-nm-thick Si3N4 layer by CVD and anisotropic plasma etching with CHF., Where Si02 must be selectively etched to Si; N4. i 3 N 4 spacer layer 4 9 (Figure 15). The Si02N4 and silicon were used to selectively wet the Si02 with NH4 / HF to chemically etch the Si02 layer 48, and the Si02 layer 46, thus exposed, was removed. This etching period must be adjusted to etch S i 0 2 of 25 nm. S i 3N is used in wet chemical oxide etching by depositing a 5 nm Si3N4 layer by CVD and an anisotropic etch using CHF3 (wherein the etching period must be adjusted to etch 5 i 3N4 at 5 nm). 4 material 50 is inserted into the resulting under-etched area (Figure 16). The polycrystalline silicon material 47 is then selectively removed from Si3N4 and Si02 by means of SF6. The exposed portion of the Si02 layer 46 is removed by wet chemical etching using NH4F / HF. Ammonia is used for isotropic etching (where Si 3N 4 is selectively etched and silicon is etched) so that the cross section of the trench 45 extends below the Si3N4 spacer layer 49 and the Si3N4 material 50. This saturation period must be adjusted to touch the 20 n m sand. That is, the cross section of each of the trenches 45 has been extended by 40 n m (Fig. 17). The Si3N4 spacer layer 49 and the Si3N4 mask 50 are selectively removed from SiQ2 and silicon by wet chemical etching using HF / ethylene glycol. This etching time must be adjusted to etch S i 4 of 15 nm. A 30nm-thick arsenic-doped tungsten silicide layer 51 (FIG. 18) was produced by in-situ doping of tungsten silicide. -1 5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- install it ----- order ------ --- Line {Please read the notes on the back before filling this page) A633 6 9 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The trench 4 5 in A photoresist material 52 is provided in the lower area (where the cross-section of the trench 4 5 is enlarged by isotropic silicon etching). The height of the photoresist mask 52 is adjusted by etching with N2 / 02. By anisotropic etching with HC 1 / C 12 / NF 3 (where Si3N4 and Si02 must be selectively etched with tungsten silicide), in trench 4 5 by tungsten silicide layer 5 1 This is structured to form the capacitor lower electrode 53. The capacitor lower electrodes 5 3 are respectively arranged in the above-mentioned enlarged regions along the surfaces of the respective trenches 4 5. The portion of the tungsten silicide layer 51 doped with arsenic disposed above the enlarged cross-section of the respective trench 45 or the portion disposed on the surface of the silicon nitride layer 4 4 is therefore removed (No. 1 Figure 9). The photoresist material 52 was then removed at 0 2 / N 2. A 5 nm thick dielectric layer 54 is subsequently deposited, which contains SiO 2 and Si 3 N 4 or contains another dielectric made in connection with the first embodiment and used as a capacitor dielectric in the fabricated memory cell configuration. "Characteristics" by depositing a 70-nm thick doped polycrystalline silicon layer, performing an annealing step at 1100 ° C for 60 seconds, and chemical-mechanical polishing the polycrystalline silicon layer until the surface of the Si3N4 layer 44 and The capacitor lower electrode 53 is diffused outward to form an n + -doped region 5 5 (which connects adjacent capacitor lower electrodes 5 3 to each other) and a polycrystalline silicon material 5 6 is formed by structuring the polycrystalline silicon layer (No. 2 0 figure). This polycrystalline silicon material 56 is etched with SF6 to etch back to 100 nm below the main surface 41. Then HF / ethylene glycol was used to etch Si3N4 (in which Si3N4 was etched with 1 ηΐΏ) and MH4F / HF was used to etch (in which SiO2 and dielectric materials were etched). -1 6- This paper size applies Chinese national standards < CNS) A4 size (210 X 297 mm) ------------- install --- --- order --------- line (please read the first Note for refilling this page} 4 6 33 6 9 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du V. Description of the Invention (π) A western-style animal oxidation to form stray oxides (not shown) An implantation process in which a n + -doped region 57 (circle 21) can be formed in each side wall of the trench 45 in the area of the main surface 41. Polysilicon is formed in each of the trenches 4 5 The remaining space above the material 5 6 is deposited with the same doped polycrystalline silicon to etch back the polycrystalline silicon with SF 6 and inject with the polycrystalline silicon material 5 8. The polycrystalline silicon material 5 6 This capacitor is used as the upper electrode of this capacitor. Polycrystalline silicon material 5 8 is used as the connection structure between n + -doped region 57 and polycrystalline silicon material 56 (which is used as the upper electrode of the capacitor). To manufacture the upper electrode of the capacitor, another way is to deposit a 20 nm thick tungsten silicide layer 59 after depositing the dielectric layer 5 4 and deposit 30 nm thick thereon. Doped polycrystalline silicon layer 60 (Figure 22). The annealing step is performed at I 100 ° C for 60 seconds to restore the polycrystalline silicon layer 60 and diffuse out through the arsenic-doped tungsten silicide layer 51. An n + -doped region 5 5 is formed, which connects the capacitor lower electrodes 5 3 to each other (FIG. 22). The tungsten silicide layer 59 and the polycrystalline silicon layer 60 are chemically and mechanically polished up to the surface of the SijNq layer 44 It is structured. Then, Si3N4 is selectively etched with HCI / C12 / NF3 to etch polycrystalline silicon, tungsten silicide, and Si〇2. The etching rate of S i 〇 2 and polycrystalline silicon is slightly higher than those of tungsten silicide. Use HF / B Dioxide was used to etch 100 nm of Si3N4. The surface of the semiconductor substrate 42 was exposed in the upper region of the trench 45. The dielectric layer 54 was then isotropically etched with DHF. The etching period must be adjusted to allow 5 nm After the formation of a stray oxide, with an energy of 10 Kev I----II — I--II-— — — — I! — < I t I f I —1 II (Please read the notes on the back before filling in this page) The paper size applies to the ten national standards (CNS) A4 size 010 × 297 mm) Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 4633 6 9 A7 B7 V. Description of the invention (4) The inclined implantation of phosphorus with a dose of 2x10l3cm 〃 formed η, doped region 57 (Figure 23). A mask implant is then performed to form an n-doped well (not shown). The polycrystalline silicon material 6 3 is etched to the main surface 4 1 by etching with S F price. Isolation structures 64 are then created which surround the active area and thus define the active area. Form a mask > which defines active areas (not shown). Non-selective plasma-etching of silicon, tungsten silicide, Si 02, and polycrystalline silicon by means of CHF3 / N2 / NF3. The etching time must be adjusted to etch 200nm polycrystalline silicon and remove the used 02 / N2. The photoresist mask is made by wet-chemically etching a 3 nm dielectric layer, oxidizing and depositing a 5 nm-thick Si3N4 layer, TEOS method is used to sink a 2 50 nm-thick Si02 layer, and subsequent chemical-mechanical polishing Each isolation structure 64. Etching is then performed with hot H3P04 to remove the Si3N4 layer 44 and etching is performed with D H F (diluted hydrofluoric acid) to remove the Si 0 2 layer 4 3 (Fig. 24). A stray oxide is then formed by the oxidation of the western animal. The masks generated by some implantation processes and lithography are used to form η-doped wells, P-doped wells and in selected peripheral regions of the cell array and selected transistor regions (not shown separately) The implantation of each on-voltage is performed during the process. In particular, a ρ_ doped well 65 with a dopant concentration of 5 × 10 7 cm · 3 was generated in the active region, which is fixedly used to accommodate each selected transistor (FIG. 25). After the stray oxide was removed with DHF, a gate oxide 66 having a thickness of 6 nm was formed by thermal oxidation. And then shaped by integrated deposition -1 8- < Paper size iS t Guan Jia Xian (CNS) A4 specification (210 x 297 mm) --- ill --------------- ^ I -------- (Please read the notes on the back before filling this page) A7 B7 Λ6336 9 V. Description of the invention (7) Polycrystalline silicon layer 6 7 and tungsten silicide layer 6 8 The polycrystalline silicon layer 67 is doped at the same time and has a thickness of 80 η π. The thickness of the tungsten silicide layer 68 is 68 nm (Fig. 25). A 200 nm thick Si3N4 layer 69 is then deposited. With the help of the mask generated by lithography (not shown, the boundary of these character lines containing the gate electrode configuration, each character line is stripe and extends parallel to each other), and CHF3 / 02 / CF4 To etch the Si3N4 layer 69, the gate electrode 70 is formed from the tungsten silicide layer 68 and the polycrystalline silicon layer 67 (FIG. 26). The side wall of the gate electrode 70 is provided with a Si 02 layer 71 by oxidation. A masked implant is then performed to form the source / drain regions 72. After removing the last photoresist mask, Si3N4 was formed on the sides of the gate electrode 70 and Si3N4 layer 69 by depositing a 3 5 nm thick Si 3N4 layer and anisotropic etching with c HF3. Spacer layer 73. A 23 nm thick nitride oxide layer 74 is then deposited. By depositing a BPSG layer 75 with a thickness of 550 nm, the BPSG layer 75 is fused and subjected to chemical-mechanical polishing (where the oxide nitride layer .74 is used as an etch stop layer) to form a flat surface (Fig. 26) On this flat surface, a 450 nm thick Si0 2 layer is applied by TEO S method 76 »with the help of a mask (not shown) created by lithography to create some contact in 3 丨 02 layer 76 The holes 77 and the contact holes 77 reach the source / drain regions 72 (FIG. 27) of the selection transistors in the periphery and the transistors that are not connected to the n + -doped regions 57. When the opening of this contact hole 76 is anisotropically etched with 02 / C4F8 / CO, the oxidation-19- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 issued) ---- ----- ---- Shock -------- Order --------- line (Please read the precautions on the back before filling out this page) Employee Cooperatives of Intellectual Property Bureau, Ministry of Economic Affairs Printing 4 633 6 9 A7 B7 V. Description of the Invention (j) The nitride layer 74 is used as an etch stop layer. The nitride oxide layer 74 is removed in the area of the contact hole 77 by 0 / CHF3. With the help of lithography, which covers the cell array of this memory cell configuration, the required HDD implantation (not shown) for each transistor is performed in the peripheral area. A polycrystalline silicon wafer 78 is formed in the contact hole 77 by depositing a polycrystalline silicon layer of the same doping and subsequent anisotropic etching with CH4 / SF6 (Fig. 27). Etching in CF4 / CHFj in the SiCh layer 76 by means of another mask (not shown) produced by lithography, this mask defines the arrangement of stripe bit lines parallel to each other, bit lines It is perpendicular to the character line and extends. Therefore, it can be etched to a depth of 270 nm. After removing such a mask produced by lithography with 0 2 / N 2, titanium and tungsten are deposited and structured by a chemical-mechanical polishing method. Bit line 79 is then generated = this memory cell configuration is made conventionally by the formation of other wiring planes. ------------ * --- Please read the back of the page; i-Identification page on this page) .. line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -20- This paper size applies China National Standard (CNS) A4 Specification (210 X 297 mm) 463369 A7 X B7 \ years \\ Fifth, description of the invention () Description of the main component symbols 2 Semiconductor substrate 3,6,8 Si02 layer 4,25 Si3N4 layer 5 trench 7,1 6,1 6 Μ 8 polycrystalline silicon material 9,29 Si3N4 spacer layer 10 Si3N4 material 11,17 n + -doped region 12 dielectric Electrical layer 13,15s, 24 Tungsten silicide layer 14 Photoresistor 15,15 ”Capacitor upper electrode I6 ', 23 Polycrystalline silicon layer 19 η-doped well 20 Isolation structure 21 P-doped well 22 Gate oxide 26 Gate Electrode 27, 32 Si02 layer 28 source / drain region 30 nitride oxide layer 31 BPSG layer 33 contact hole -21----------- ^ ------ 1T ----- -C Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 463369 A7 B7 V. Description of Invention (π) Intellectual Property of the Ministry of Economic Affairs Printed by employee consumer cooperatives 34,47,5 6,5 8,6 3,7 8 Polycrystalline silicon material 41 Main surface 42 Semiconductor substrate 43, 46, 48, 7 1,76 Si02 layer 44, 69 Si3N4 layer 45 Ditch 49, 73 S i 3 N 4 spacer layer 50 Si3N4 material 51, 59, 68 tungsten silicide layer 52 photoresist material 53 capacitor lower electrode 54 dielectric layer 55, 57 n + -doped region 60, 67 polycrystalline silicon layer 64 isolation Structure 65 P-doped well 66 Gate oxide 70 Gate electrode Ί 1 source / drain region 74 nitride oxide layer 77 contact hole 79 bit line A active region BLK bit line contact region WL word line -22 -I --------- ^ ------- 1T ------ ^ (Please read the precautions on the back before writing this page) The paper size applies to Chinese national standards (CNS ) A4 size (210 × 2ίΠ mm)