DE10217261A1 - Memory module with a memory cell with low-temperature layers in the memory trench and manufacturing process - Google Patents

Abstract

Memory cells with trench capacitors are described, the trench capacitor being at least partially filled with a material that could not survive the high-temperature processes used in the production of a memory chip without impairing its electrical parameters. It is essential to the invention that the material of the trench capacitor is only introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers with large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved compared to known trench capacitors.

Description

The invention relates to a memory chip with a Trench capacitor memory cell according to the preamble of Claim 1. The invention further relates to a Method for producing a trench capacitor memory cell according to the preamble of claim 7.

Memory chips are preferably made using semiconductor technology manufactured and are with dynamic or static Provide memory cells. A dynamic memory cell exists from a selection transistor and a storage capacitor. The memory states 0 and 1 correspond to a positive or a negative polarity of the storage capacitor. Since the Capacitor charge due to recombination and leakage currents dismantled in a time of approx. 1 second, the Charge refreshed again and again. The Storage capacitor is, for example, a trench capacitor educated. The peculiarity of the trench capacitor exists in that the capacitor in the form of a trench in one Substrate is introduced. In the surface of the substrate (Planar transistor) or in the upper section of the Memory trench (vertical transistor) is the selection transistor Control of the trench capacitor arranged.

Corresponding memory cells with trench capacitors are in the published documents DE 199 41 147 and DE 199 41 148 described. In the memory cells described, the Storage capacity in the form of a deep in the semiconductor substrate recessed trench, while the rest Functional and wiring elements of the memory matrix and the Storage periphery above the trench without any annoying Topography arranged on the planar substrate surface are. This embodiment facilitates the structuring the levels above the ditch level. For example, allowed this arrangement further scaling, i. H. a further downsizing of the structures and an optional Integration of memory and other functions on the chip without elaborate, specific process adjustments.

An increase in the area-specific storage capacity scaling has so far been conventional Expansion / expansion of the following solutions have been realized: The Thickness of the storage dielectric is below 5 nm reduced. However, a further reduction in thickness is due to Yield, leakage current and reliability problems to about 4 nm limited.

The depth of the trench is increased to 7 µm, which makes one Aspect ratio of approximately 40 corresponds. So that is currently a high effort for the production of Etching hard mask and a long process time in the industrial available etching systems inevitable. An enlargement of the Trench aspect ratio of> 60 currently appears for one Series production not possible.

A lateral widening of the trench extends to the region of the trench floor by partially isotropic etching (botteling) maximized. Experience has shown that this measure can take up to one Distance between adjacent trench flanks of about 0.6 times that minimal structure size and is driven by Process stability and homogeneity of the trench structuring limited.

The cost reduction per Storage unit forces the storage size to increase further by increasing the integration density (Memory cell / die area). The associated scaling of the area and Structure size of the memory cell and the storage capacitor increasingly requires further measures to secure the Minimum capacitance for trench capacitors at around 35 to 40 fF lies.

Sense amplifier, which is used to read the trench capacitor stored information used require a sufficient signal level for reliable reading of the information in the memory cell. The relationship the storage capacity to the capacity of the bit line over which the stored information is passed to the sense amplifier is crucial in determining the signal level. If the storage capacity is too low, then the im Trench capacitor information no longer unique as Signal level detected by the sense amplifier on the bit line become.

Since the stored charge also flows through leakage currents, A smaller capacity has the disadvantage of being shorter Intervals the load needs to be refreshed (larger Refresh rate). Is a due to the leakage currents The minimum amount of charge in the storage capacitor is undercut it is not possible for the sense amplifier to save the stored one Read out information.

So far, only material combinations of thin silicon dioxide and silicon nitride (Si ₃ N ₄ ) layers (NO, ON, ONO) as a storage dielectric and doped polysilicon layers as electrode material have been used in memory cells with trench capacitors. These materials are resistant to high temperatures and are not adversely affected in their properties by the temperatures which are required to produce a transistor after the production of the trench capacitor.

The object of the invention is a memory cell to provide with a trench capacitor opposite the previously used trench capacitors Has storage capacity. The task of Invention therein, a method for producing a To provide memory cell with a trench capacitor that an increased storage capacity compared to the previously known Has trench capacitors.

The object of the invention is characterized by the features of Claim 1 and solved by the features of claim 7. An advantage of the invention is that the trench with a filling is at least partially provided at high temperatures that are common in manufacturing of a transistor are applied, is unstable.

The filling preferably has at least partially metallic material. By using a metallic material as the electrode material becomes the resistance reduced to contact the trench capacitor. The small Resistance enables the signal to be connected to a To be able to reliably detect read-out amplifiers.

In a further advantageous embodiment, the Filling at least partially with a dielectric material large dielectric constant. dielectric Are materials with a large dielectric constant Usually only stable up to temperatures of around 800 ° C. That is why the application of the dielectric was previously Materials with high dielectric constants during manufacture a memory cell in the form of a trench capacitor possible. However, since in the embodiment according to the invention the memory cell, the dielectric material only after the High temperature processes inserted in the trench, it can thereby used without problems in the trench memory cell become. The use of a dielectric material with a large dielectric constant has the advantage that a larger amount of charge with the same area the trench capacitor is storable, d. H. the The storage capacity of the trench capacitor is increased.

In a further preferred embodiment, both a metallic layer as well as a dielectric layer used with a large dielectric constant. By the combination of the two advantageous materials becomes one get particularly advantageous trench capacitor. The metallic layer ensures low resistance the contacting of the trench capacitor and the dielectric layer ensures a large charge capacity of the Grave capacitor.

Preferably, one is electrical adjacent to the trench conductive layer formed in the substrate, the one Counter electrode of the capacitor forms. Due to the arrangement of the electrically conductive layer close to the filling of the Trench capacitor becomes a particularly high storage capacity receive.

In a further preferred embodiment, the trench is covered by a cover layer that has an opening to the electrical contact of the filling of the trench. On the underside of the cover layer is a dielectric layer at least partially applied. This way too the area of the top layer for storing the load exploited. This will increase the capacitance of the trench capacitor elevated.

The inventive method according to claim 7 has the significant advantage that after the manufacture of the Trench the trench is filled with an intermediate filling, that then the transistor for driving the Trench capacitor is introduced that thereupon the Intermediate filling is removed from the trench again and finally the dielectric effective, final capacitor filling in the Digging is made. The method according to the invention has the advantage that during the process steps with high Temperatures the intermediate filling is placed in the trench and the dielectric layer and / or an electrode layer only be introduced into the trench afterwards. The Intermediate filling is selected in such a way that it is high Temperatures without significantly affecting them mechanical properties that it survives the trench not adversely affected, and that they are easy again can be removed from the trench. After integrating the The transistor becomes the trench with a capacitor filling at least partially filled. In this way it is possible to use as a capacitor filling materials that a enable improved functioning of the memory cell, but high temperatures are not without reducing their Tolerate material quality.

A dielectric is preferably used as the capacitor filling Material used that has a large dielectric constant having. The storage capacity of the Trench capacitor increased.

In a development of the method according to the invention preferably for contacting the dielectric layer a metallic conductive layer as an electrode in the trench brought in. The use of the metallic layer is only possible because it is only after the High temperature processes is introduced. The metallic layer has the Advantage on having a lower contact resistance of the trench capacitor is reached.

A channel is preferably used to remove the intermediate filling etched and the side walls of the channel with a Protective layer covered. Then the intermediate filling is made etched out of the ditch across the canal. That way easy removal of the intermediate filling possible.

The invention is explained in more detail below with reference to the figures explained. Show it

Fig. 1 shows a cross section through a first memory device having a first memory cell,

Fig. 2 is a view from above of the first memory block,

Fig. 3 is a schematic representation of a process flow for producing a first memory cell,

Fig. 4 shows a cross section through a memory device with a second memory cell,

Fig. 5 is a view from above of the second memory block,

Fig. 6 is a schematic process flow for manufacturing the memory cell of the second memory device and

Fig. 7 is a schematic process flow for forming a third memory cell.

Fig. 1 shows part of a cross section through a memory device, which is designed in the form of a DRAM. The section shows a memory cell consisting of a transistor and a trench capacitor. The trench capacitor has a trench 2 , which is introduced into a semiconductor substrate 1 . The semiconductor substrate 1 is usually designed in the form of a silicon wafer. The trench 2 has a rectangular cross section, vertical plate doping zones 5 being introduced in the side walls which delimit the trench 2 . The vertical plate doping zones 5 represent first doping zones and are formed on the side walls of the trench 2 . In the upper area of the trench 2 , adjacent to the vertical plate doping zones 5, there are arranged horizontal plate doping zones 15 , which represent second doping zones, which are essentially horizontal and both laterally to a vertical plate doping zone 5 and above the trench 2 in an epitaxial layer 6 are formed. The epitaxial layer 6 is essentially designed as an epitaxial silicon layer. The vertical and horizontal plate doping zones 5 , 15 represent a second electrode of the trench capacitor. A storage dielectric 3 is applied to the inner wall of the trench 2 . The storage dielectric 3 preferably covers the entire wall of the trench 2 . In the upper region, the trench 2 opens into a strap channel 24 , which is preferably led vertically upwards through the epitaxial layer 6 to an intermediate insulation layer 23 . The strap channel 24 is laterally delimited by the epitaxial layer 6 . Furthermore, the & strap channel 24 is disposed an insulating collar 7 in the strap-channel 24 at a predetermined distance from the lower edge. The insulation collar 7 is sleeve-shaped and extends up to a predetermined distance from the top of the epitaxial layer 6 . The storage dielectric 3 is also arranged on the underside of the epitaxial layer 6 above the trench 2 and is preferably guided up to the lower edge of the insulation collar 7 . A trench electrode 4 is arranged on the inside of the storage dielectric 3 and is also led into the strap channel 24 . The grave electrode 4 is an electrode of the grave capacitor. Preferably, the grave out electrode 4 upwards into the strap channel 24 to beyond the lower edge of the insulation collar. 7 In the strap channel 24 , a conductive strap filling 17 is arranged, which is guided up to just below the upper edge of the cover layer 6 . The strap filling 17 is surrounded in the upper end area by a strap cap 26 , which is made of a conductive material. The strap cap 26 is designed in the form of a sleeve with an end plate and rests with a sleeve edge on the insulation collar 7 and with the end plate on the strap filling 17 . The strap cap 26 closes approximately with the upper edge of the epitaxial layer 6 .

The epitaxial layer 6 essentially consists of a silicon layer which is arranged above the trench 2 and in the lower region of which the horizontal plate doping zone 15 is arranged. The horizontal plate doping zone 15 borders both laterally on the strap channel 24 and on the vertical plate doping zone 5 . The epitaxial layer 6 has, in the left area next to the strap channel 24, an STI field insulation layer 9 which extends up to the upper edge of the epitaxial layer 6 . In the right area next to the insulation collar 7 , a drain region 21 is formed adjacent to the strap cap 26 . A source region 22 is arranged adjacent to the top edge of the epitaxial layer 6 to the right of it at a predetermined lateral distance.

A passive word line 27 , which is covered by a word line cover insulation 19 , is arranged in a third layer 25 adjacent to the field insulation layer 9 . The word line cover insulation 19 is covered on the left side by a sealing layer 20 , on which in turn a first insulation filling 10 is applied. An active first word line 28 is arranged to the right of the strap channel 24 in the third layer 25 at a predetermined distance from the passive word line 27 . The first active word line 28 lies on an oxide layer which is arranged on the epitaxial layer 6 . The first active word line 28 is arranged in two opposite edge regions above the drain region 21 and the source region 22 . The first word line 28 , the drain and source region 21 , 22 and the region of the epitaxial layer 6 which is arranged under the first active word line represent a transistor 18 .

To the right of the first active word line 28 , a further active word line 8 is arranged in the third layer 25 at a predetermined distance. The further active word line 8 is arranged separated from the epitaxial layer 6 by an oxide layer and with a left edge region above the source region 22 . The first and the further word lines 28 , 8 are each covered by a word line cover insulation 19 . The word line cover insulation 19 is in turn covered in the lateral edge region with a sealing layer 20 , which is guided from the upper end region of the word line cover insulation 19 to the upper edge of the cover layer 6 . Between the first and further word lines 28 , 8 , a bit line plug 11 is arranged in the third layer 25 above the source region 22 and is led to the upper edge of the third layer 25 . The bit line plug 11 represents a contact connection. The further areas of the third layer 25 are filled by the intermediate insulation 23 . A bit line 12 is applied to the third layer 25 . Bit line 12 is in conductive contact with bit line plug 11 .

. The operation of the memory cell of Figure 1 is as follows: In the grave capacitor of the storage dielectric 3, the grave electrode 4 and the vertical and horizontal plate Dotierzone 5, 15 is formed, stored charge. If the charge is to be read out, a predetermined voltage is applied to the first word line 28 , so that the transistor 18 consisting of the first word line 28 , the drain region 21 and the source region 22 is switched to be electrically conductive. Since the drain region 21 is connected to the trench electrode 4 in an electrically conductive manner via the strap cap 26 , the conductive strap filling 17 , the electrical charge stored in the trench capacitor is transferred to the bit line 12 via the transistor 18 and the bit line plug 11 , The bit line 12 is usually connected to a sense amplifier which detects and passes on the voltage level on the bit line 12 due to the charge stored in the trench capacitor. The design of the trench electrode 4 in the form of a metallic material considerably reduces the ohmic resistance for contacting the trench capacitor.

Furthermore, the design of the storage dielectric 3 in the form of a dielectric material with a large dielectric constant has the advantage that a larger amount of charge can be stored in the trench capacitor with the same dimensions. On the basis of the production method according to the invention, a material can be used as the dielectric material for the storage dielectric which is stable only up to a relatively low maximum temperature of, for example, 800 to 1050 ° C. Binary oxides, such as e.g. B. tantalum oxide (Ta ₂ O ₅ ) with a dielectric constant of 25 to 26 and a temperature stability of 800 ° C. Furthermore, the use of aluminum oxide (Al ₂ O ₃ ) with a dielectric constant of 10 and a temperature stability of up to 830 ° C. as the storage dielectric 3 is advantageous.

Hafnium oxide (HfO ₂ ) with a dielectric constant of 15 to 40 is preferably used as the storage dielectric 3 as a further material. Furthermore, zirconium oxide (ZrO ₂ ) offers itself, which has a dielectric constant of 11 to 25. In addition, lanthanum oxide (La ₂ O ₃ ) with a dielectric constant of 20 to 30 can also be used as the storage dielectric 3 . When using lanthanum oxide, however, it should be noted that lanthanum oxide does not have any guaranteed stability against hydrogen. In addition, to form the storage dielectric 3 may also be yttria (Y ₂ O ₃₎ may be used which has a dielectric constant of 12 to 15

Furthermore, aluminum oxide compounds are also suitable for formation as a storage dielectric 3 . The compounds with hafnium, zirconium and lanthanum are particularly suitable for the formation of the storage dielectric 3 . For example, the material compounds Hf-Al-O, Zr-Al-O, La-Al-O can be used.

Furthermore, the storage dielectric 3 can also be made of silicate compounds such. B. Hf-Si-O, Zr-Si-O, La-Si-O or Y-Si-O. The material compound Hf ₇ Si ₂₉ O ₆₄ with a temperature stability of up to 1050 ° C. is preferably used. The material compound Zr ₄ Si ₃₁ O ₆₅ is also stable up to a temperature of 800 ° C. A 30% lanthanum-silicon oxide compound is also suitable. A 70% silicon oxide-silicon-oxygen compound is likewise stable up to a temperature of 1000 ° C. and is suitable as a storage dielectric 3 . A 30% strength hafnium oxide-silicon-oxygen and a 70% strength silicon oxide-silicon-oxygen compound are also suitable as storage dielectric 3 and are stable up to a temperature of 1000 ° C. Lanthanum dioxide silicate and silicon dioxide silicate have a dielectric constant of 14. Hafnium dioxide silicate and silicon dioxide silicate have a dielectric constant of 7.

Other material compounds that are suitable as dielectric material for the storage dielectric 3 are, for example, Y ₂ O ₃ -ZrO ₂ with a dielectric constant of 30 and strontium titanium oxide (SrTiO ₃ ) with a dielectric constant of 175. Strontium titanium oxide is up to a temperature of 800 ° C stable.

The trench electrode 4 is preferably made from doped polysilicon or from a metal compound. On the basis of the method according to the invention, the storage dielectric 3 and / or the trench electrode 4 are introduced into the trench 2 after the process steps, which require a high temperature. These are, for example, the processes for integrating the transistor. After the storage dielectric layer 3 and the trench electrode layer 4 have been introduced , only process steps with lower temperatures are carried out which do not damage the temperature-sensitive dielectric and metallic materials of the storage dielectric 3 and the trench electrode 4 .

FIG. 2 shows a view from above of the memory module of FIG. 1, different areas of the memory cell being shown schematically. A passive word line 27 is shown, which is covered with the word line cover insulation 19 . In addition to the passive word line 27 , the active first word line 28 is arranged, which is also covered by a word line cover insulation 19 . The shape of the trench 2 is indicated in the form of a dashed line. An active region 59 is indicated in the form of a continuous line, which is formed in the epitaxial layer 6 and extends over two trenches 2 , 30 . The active region 59 identifies a region of the epitaxial layer 6 which is arranged between two trenches 2 , 30 arranged next to one another and in which two transistors with the first and the further word lines 28 , 8 are formed as control connections. In addition to the first active word line 28 , the bit line plug 11 is shown. The second active word line 8 , which is also covered by a word line cover insulation 19 , is arranged to the right of the bit line plug 11 . The first and further word lines 28 , 8 are arranged parallel to one another. The bit lines 12 arranged perpendicular to the word lines are not shown in FIG. 2. The further word line 8 is partially arranged over a further trench 30 , which is also indicated in the form of a dashed line. The connection of the further trench 30 to a further transistor, which is formed by the second word line 8 , is designed corresponding to the connection of the trench 2 to the first word line 28 .

Fig. 3 shows the essential process steps for manufacturing the memory cell of the invention of FIG. 1. This is etched in a, for example, P-type silicon substrate 1 with lithography and etch a hard mask, a trench 2. For this purpose, the silicon substrate 1 is coated with a silicon dioxide layer and a silicon nitride layer as a hard mask. After mask removal and cleaning z. B. by means of a glass layer 31 doped with arsenic and the following diffusion process, the vertical plate doping zone 5 is generated in the side walls of the trench 2 . A dummy fill 32 is then deposited until the trench 2 is completely filled. The dummy fill 32 is preferably formed from silicon dioxide and optimized for large wet etching rates.

In a first embodiment of the method, the trench 2 is slightly bulbously etched in the upper section by a proportional isotropic etching method, so that a negative flank angle is generated. This increases the cross-section of the trench opening downwards. Due to the bulbous shape in the upper region of the trench 2 , the trench 2 is closed by the dummy filling 32 , even before lower-lying sections of the trench 2 are completely filled. As a result, in the lower region of the trench 2 there is an extended void along its axis of symmetry, ie a cavity, which considerably facilitates the subsequent complete removal of the dummy filling 32 . This effect can be further enhanced by an conformal deposition process with deposition rates of the silicon oxide deposited on the glass layer 31 falling sharply in the depth of the trench. Fig. 3B shows the arrangement of a filled trench 2 having a voids 60th

In a further embodiment of the method, a silicon layer is first deposited on the glass layer 31 instead of the silicon oxide. The silicon layer is then etched back planar to just below the level of the surface of the silicon substrate 1 . Then a silicon dioxide layer is deposited. Thus, in this exemplary embodiment, the dummy filling consists of the glass layer 31 and an intermediate filling designed as a silicon layer, which is covered by a silicon oxide.

Subsequently, the dummy filling 32 is etched back to the level of the surface of the silicon substrate 1 using a planar etching process. This process status is shown in Fig. 3A.

The nitride layer and the oxide layer are then removed and a single-crystalline silicon layer is formed as an epitaxial layer 6 on the open area of the silicon substrate 1 and over the trench 2 provided with the dummy filling with a homogeneous thickness. This process status is shown in Fig. 3C. A selective, epitaxial deposition method is preferably used for the deposition of the silicon layer, which is described in more detail in the published patent application DE 199 41 148.

In a subsequent method step, the horizontal plate doping zone 15 , which is n-doped, is introduced into the epitaxial layer by means of ion implantation. This process status is shown in Fig. 3D. An STI field insulation layer 9 is then introduced into the epitaxial layer 6 over a left partial region of the trench 2 . This process status is shown in Fig. 3E. The field insulation layer 9 extends up to a predetermined distance from the horizontal plate doping zone 15 and is guided up to the upper limit of the epitaxial layer 6 . The field insulation layer 9 extends laterally over part of the trench 2 .

A passive word line 27 and a first and further active word line 28 , 8 are then applied to the epitaxial layer 6 . The word lines are covered with word line cover insulation layers 19 . The drain region 21 and the source region 22 are then introduced into the epitaxial layer 6 using known methods, as described for example in DE 199 41 148. The drain and source regions 21 , 22 are introduced by known doping methods and a subsequent high-temperature diffusion phase. In addition, a sealing layer 20 is applied to the word line cover insulation layer 19 . The drain region 21 , the source region 22 and the first active word line 28 form a first transistor 18 . This process status is shown in Fig. 3F.

In a subsequent method step, a first insulation filling 10 is introduced between the passive word line 27 and the first active word line 28 . In addition, a conductive bit line plug 11 is inserted between the first and the second active word lines 28 , 8 . The first insulation filling 10 and the bit line plug 11 are etched down to the upper edge of the sealing layer 20 . The bit line plug 11 is then subjected to a healing process. This process essentially represents the last high-temperature load. Then a strap window mask 61 consisting of Si ₃ N ₄ and a strap window hard mask 63 consisting of SiO ₂ are applied to the substrate. A contact window is introduced into the strap window mask and the strap window hard mask 61 , 63 above the intermediate region between the passive word line 27 and the active word line 28 . This process status is shown in Fig. 3G. The area between the passive word line 27 and the first active word line 28 is then etched free and the first insulation filling 10 between the first active and the passive word line is removed. In addition, the strap window hard mask 63 is removed. This process status is shown in Fig. 3H.

A strap channel 24 is then etched through the cover layer 6 up to the upper edge of the filled trench 2 . This process state is shown in FIG. 31.

In the following process step, the side wall of the strap channel 24 is covered with a thin etching channel protective layer 62 . The etching channel protective layer 62 is designed as a nitride layer and is guided up to the upper edge of the dummy filling 32 . This process state is shown in Fig. 3J.

The etching channel protective layer 62 is then removed again from the surface of the dummy filling by anisotropic, selective plasma etching.

In a subsequent process step, the dummy filling and the glass layer are completely removed from the trench 2 by means of an isotropic etching process, in that the distance between active and passive word lines 27 , 28, which is necessary for the subsequent connection to the power supply, is temporarily used as a sealed etching channel. In this process step, all surfaces that are otherwise exposed on the memory chip are designed to be resistant to the etching solution that is used to remove the intermediate filling, or are covered by a sealing layer. This process state is shown in Fig. 3K.

After cleaning the inner wall of the trench 2, there is preferably a conformal deposition of the storage dielectric 3 and then a deposition of the trench electrode layer 4 . The storage dielectric 3 and the trench electrode 4 are preferably deposited using an atomic layer deposition method (ALD). This process state is shown in Fig. 3L. It can be seen in FIG. 3L that the material that forms the trench electrode 4 also fills the strap channel 24 .

The trench electrode layer 4 is then selectively etched back to just above the upper edge of the trench 2 . The etched-back trench electrode layer 4 is then used as an etching mask for the isotropic removal of the exposed areas of the storage dielectric 3 . The etching channel protective layer 62 is used as an etching mask in this process. The process state is shown in Fig. 3M.

In an advantageous embodiment of the method according to the invention, the trench electrode 4 is selectively etched back to just below the upper edge of the trench 2 , as a result of which the trench 2 is opened again. The trench electrode 4 is then deposited again, so that the thickness of the trench electrode 4 in the trench 2 is advantageously increased. This process cycle of deposition and etching back of the trench electrode 4 can be carried out several times if required. However, the last deposited trench electrode layer 4 is to be etched back to just above the top edge of the trench, as shown in FIG. 3M. A greater thickness of the trench electrode 4 in the upper region of the trench 2 has a particularly low ohmic resistance for contacting the trench electrode 4 located in the trench 2 . This embodiment is therefore particularly advantageous for contacting the trench capacitor with a low ohmic resistance.

This is followed by the formation of the strap filling 17 , which is surrounded by an insulation collar 7 . For this purpose, the etching channel layer 62 is first etched off to just below the upper edge of the trench electrode 4 and then the side walls of the strap channel 24 are provided with an insulation collar 7 . The insulation collar 7 is preferably made of silicon dioxide. The electrically conductive strap filling 17 is then introduced into the insulation collar 7 . This process state is shown in Fig. 3N.

The upper region of the insulation collar 7 is then etched off and a strap cap 26 made of an electrically conductive material is applied to the strap filling 17 and the insulation collar 7 . The strap cap 26 is conductively connected to the strap filling 17 and to the drain connection 21 . This process status is shown in FIG. 30.

Subsequently, the still open area between the passive word line 27 and the first active word line 28 is filled with an intermediate insulation 23 and the surface of the word lines is covered with it. This process status is shown in Fig. 3P. A connection hole is etched into the intermediate insulation layer 23 above the bit line plug 11 , and the connection hole is filled planar with a conductive layer. The bit line 12 is then applied to the second intermediate insulation layer 23 . In this way, a memory module with memory cells according to FIG. 1 is obtained.

Fig. 4 shows another embodiment of a memory cell in the form of a Sub8F ² DRAM cell having an open bitline layout with self-aligned attached, buried grave capacity of low-temperature high-K dielectric and a metallic electrode. The structure of the trench capacitor is essentially identical to the structure of the trench capacitor of FIG. 1. A significant difference is that two adjacent trenches 2 , 34 are electrically contacted via two strap contacts 37 , 38 , the strap contacts 37 , 38 are arranged side by side. FIG. 4 shows a cross section through a DRAM memory with a first and a second trench 2 , 34 , which are introduced into a semiconductor substrate 1 . The first and the second trench 2 , 34 are each surrounded by a vertical plate doping zone 5 , which are introduced into the semiconductor substrate 1 on the side walls of the trench 2 . Furthermore, the side walls of the first and second trenches 2 , 34 are covered with a storage dielectric 3 . On the storage dielectric 3 is a grave electrode 4 is applied. The interior of the first and second trenches 2 , 34 is partially designed as a cavity.

The semiconductor substrate 1 is formed between the mutually assigned vertical plate doping zones 5 of the first and the second trench 2 , 34 in the form of a separating web 35 . The first and the second trench 2 , 34 are covered with an epitaxial layer 6 . The epitaxial layer 6 preferably consists of an epitaxial silicon layer. A common connecting channel 36 is introduced into the epitaxial layer 6, which is arranged symmetrically with respect to the separating web 35 and is each arranged over a part of the first and the second trench 2 , 34 . The common connection channel 36 is surrounded by an insulation collar 7 and thus electrically insulated from the surrounding silicon layer. The insulation collar 7 consists for example of silicon dioxide. The epitaxial layer 6 has a horizontal plate doping zone 15 in the lower region, which adjoins the insulation collar 7 . In the common connection channel 36 , an intermediate insulation 23 is introduced symmetrically, which, starting from an area above a third word line 43 and the first active word line 28, is led down between the third and the first word line 43 , 28 through the common connection channel 36 to the separating web 35 , The intermediate insulation 23 represents an insulation filling and leads to a division of the common connecting channel 36 into the first and second strap contacts 37 , 38 , which are electrically insulated from one another. The first and the second strap contacts 37 , 38 are each filled with an electrically conductive strap filling 17 . The strap filling 17 is guided up to a predetermined distance from the upper edge of the epitaxial layer 6 . A first and second strap cap 39 , 40 is applied to the strap filling 17 of the first and second strap contact 37 , 38 , which protrudes somewhat beyond the upper limit of the epitaxial layer 6 . The first and second strap caps 39 , 40 are made of an electrically conductive material, preferably of doped silicon. In the area of the first and second strap caps 39 , 40 , the insulation collar 7 is at a predetermined distance from the upper edge of the epitaxial layer 6 . In this way, a conductive connection is formed between the first or second strap cap 39 , 40 and a drain region 21 or a further drain region 41 , which leads into the region adjacent to the first and second strap cap 39 , 40 Epitaxial layer 6 are introduced. The further drain region 41 is formed adjacent to the third word line 43 .

The epitaxial layer 3 is arranged on the underside of the strap fillings 17 of the first and second strap contacts 37 , 38 in an edge region adjacent to the insulation collar 7 . In the direction of the intermediate insulation 23 , the adjacent trench electrodes 4 adjoin the strap fillings 17 . In this way, an electrically conductive contact is established between the trench electrode 4 in the respective trench and the drain region 21 or the further drain region 41 . In the epitaxial layer 6 , in addition to the drain region and the further drain region 41, a source region 22 and a further source region 42 are introduced in the upper boundary region, which have a predetermined distance from the drain region 21 and the further drain region 41 have. In the area between the drain region 21 and the source region 22 , a first word line 28 is applied to the epitaxial layer 6 , which is surrounded by a word line cover insulation 19 . A sealing layer 20 is in turn applied to the word line cover insulation 19 . The drain connection 21 , the source connection 22 and the first word line 28 form the first transistor 18 . A second word line 8 is arranged at a predetermined distance from the first word line 28 and is in turn surrounded by a word line cover insulation 19 and a sealing layer 20 applied thereon. In the area between the first and second word lines 28 , 8 , a bit line plug 11 is introduced, which is led from the first source region 22 through the third layer 25 to a bit line 12 . The bit line plug 11 establishes an electrically conductive connection between the bit line 12 and the first source region 22 .

In the area between the further drain region 41 and the further source region 42 , the third word line 43 , which is covered by a word line cover insulation 19 and a sealing layer 20 , is applied to the epitaxial layer 6 . The third word line 43 , together with the further drain region 41 and the further source region 42, represents a second transistor 65. A second bit line plug 44 is arranged above the further source region 42 and extends through the third layer 25 to is led to the bit line 12 , which is applied to the third layer 25 . An electrically conductive connection between the further source region 42 and the bit line 12 is established via the second bit line plug 44 . The first and the second bit line plug 11 , 44 are electrically insulated from one another by the intermediate insulation layer 23 . The intermediate insulation layer 23 is applied to the sealing layer 20 , the first and the third word lines 28 , 43 . The intermediate insulation layer 23 tapers starting from the upper edge of the sealing layer 20 of the first and third word lines 28 , 43 in the direction of the separating web 35 . The space between the tapered area of the intermediate insulation layer 23 and the lateral surfaces of the sealing layer 20 of the first and third word lines 28 , 43 is filled by an intermediate layer, which is a strap separation mask, is electrically insulating and is on the upper edge of the first and second Strap cap 39 , 40 adjacent.

By driving the first word line 28, an electrically conductive connection to the trench capacitor of the second trench 34 can be established via the bit line 12 and the information stored in the trench capacitor of the second trench can be read out. The information stored in the trench capacitor of the second trench 34 is read out via the second strap contact 38 , the first drain region 21 , the first source region 22 and the first bit line plug 11 . Furthermore, by controlling the third word line 43, the information stored in the trench capacitor of the first trench 2 can be sent to the bit line 12 via the first strap contact 37 , the further drain region 41 , the further source region 42 and the second bit line plug 44 be read out.

The storage dielectric 3 is not only applied to the side walls of the first and second trench 2 , 34 , but also to the underside of the epitaxial layer 6 , which covers the first and second trench 2 , 34 , respectively. This provides an enlarged area for storing charges.

FIG. 5 shows a schematic arrangement of the memory chip of FIG. 4 from above, the trenches 2 , 34 , the bit line plug 11 and an active zone 45 being indicated in the form of a solid line in a broken line. Furthermore, the first, second and third word lines 28 , 8 , 43 are shown in the form of strips. The active zone 45 is formed in the epitaxial layer under two word lines 27 , 8 , which are connected to a source region 22 together.

To Fig. 6 shows the main process steps for fabricating a memory device according to the Fig. 4. The memory cell array is formed by a substrate coated with silicon oxide and silicon, P-type silicon substrate 1 is etched by lithography and etching through a hard mask, first trenches 2, 34 , After mask removal and cleaning, a glass layer 31 doped with arsenic is applied to the side walls of the trenches 2 , 34 . A subsequent diffusion process creates vertical plate doping zone 5 in the side walls of the trenches 2 , 34 . The trenches 2 , 34 are then completely filled with an SiO ₂ layer as a dummy filling 32 .

In a first embodiment of the method, the trenches 2 , 34 are slightly bulbously etched in the upper section by a proportionally isotropic etching, so that a negative flank angle is generated analogously to FIG. 3B. Due to the bulbous shape of the trench 2 , 34 , the opening of the trench 2 , 34 is closed by the dummy filling before lower-lying sections of the trenches 2 , 34 are completely filled. As a result, in the lower region of the trenches 2 , 34, an extended blowhole, ie a cavity, remains along its axis of symmetry. The cavity makes the subsequent complete removal of the dummy filling much easier. This effect can also be intensified by non-conformal deposition of the dummy filling, in which a strongly falling deposition rate is generated depending on the depth of the trench 2 .

In a further embodiment of the method, a silicon layer is first deposited instead of the dummy filling 32 , the silicon layer is then planarly etched back to just below the level of the surface of the silicon substrate 1 , and an SiO ₂ layer is then deposited as a dummy filling 32 .

In a subsequent process step, the dummy filling 32 is etched back to the level of the surface of the silicon substrate 1 using a planar etch-back method, then the silicon nitride and silicon oxide layers are removed and a single-crystalline silicon layer as epitaxial layer 6 on the surface of the silicon substrate 1 and on the dummy -Filling with a homogeneous thickness applied. The method for selective epitaptic deposition described in published patent application DE 199 41 148 is preferably used.

The horizontal plate doping zone 15 is then introduced into the epitaxial layer 6 by means of ion implantation. A strip-shaped STI field insulation layer 9 is then produced. The first, second and third word lines 28 , 8 , 43 are then applied in the regions between the drain and source regions. The word lines are provided with a word line cover insulation 19 and a sealing layer 20 . Thereafter, the doping regions of the transistors with the drain region 21 , the source region 22 , the further drain region 41 and the further source region 42 are preferably produced in accordance with the method described in the published patent application DE 199 41 148. A first insulation filling 10 is then introduced between the word lines. The first insulation filling 10 is removed in the area between the word lines which adjoin a common source region 22 and a first or second bit line plug 11 , 44 is introduced. The bit line plugs 11 , 44 are then backplanarized to the level of the upper edge of the sealing layer 20 of the word lines 28 , 8 , 43 . During these process steps, the bit line contacts are also healed, which represents a final, significant high-temperature load on the overall process.

A strap separating mask 46 is then applied, which, as a contact window, keeps the area between the first and third word lines 28 , 43 clear. This process status is shown in Fig. 6A. In this process status, the drain region 21 and the further drain region 41 are still coherent.

In the following process step, the insulation filling 10 is completely removed by an etching process. This process state is shown in Fig. 6B. The region arranged between the first and third word lines 28 , 43 above the doping zones 21 , 41 and the epitaxial layer 6 underneath is then etched away by means of an etching process. Furthermore, part of a separating web 35 which is arranged between the first and second trench 2 , 34 and is formed by part of the substrate 1 and the adjacent vertical plate doping zones 5 are etched off. A strap channel 24 to the dummy fillings 32 of the first and second trenches 2 , 34 is produced in this way. This process status is shown in Fig. 6C.

The walls of the strap channel 24 are then covered by an etching channel protective layer 62 made of nitride. In the area of the intermediate filling, the etching channel protective layer 62 is removed again by an anisotropic, selective plasma etching process. This process status is shown in Fig. 6D. Then the dummy filling 32 and the glass layer 31 are completely removed from the first and the second trench 2 , 34 by means of an isotropic etching process. The area between the word lines is temporarily used advantageously as a sealed etching channel. This process status is shown in Fig. 6E. In this process step, all surfaces that are otherwise exposed on the memory chip are designed to be resistant to the etching solution that is used to remove the dummy filling, or are covered by a sealing layer.

After cleaning the inner walls of the first and second trenches 2 , 34 , the storage dielectric 3 is preferably deposited in a conformal manner. On the storage dielectric 3, the grave electrode 4 is applied. The storage dielectric 3 and the trench electrode 4 are preferably applied using an atomic layer deposition method (ALD). The strap channel 24 and the surface of the memory module are covered with the memory dielectric 3 by the trench electrode layer 4 . This process status is shown in Fig. 6F.

The trench electrode layer 4 is then etched back to just above the upper edge of the first and second trench 2 , 34 by a selective etch-back process. The etched-back trench electrode layer 4 is then used as an etching mask in order to remove exposed regions of the storage dielectric 3 and the etching channel protective layer 62 using an isotropic etching method. This process status is shown in Fig. 6G.

In an advantageous embodiment of the method, the trench electrode layer 4 is selectively etched back to just below the upper edge of the first and second trenches 2 , 34 . In this way, the cavity of the first and second trenches 2 , 34 are opened again. A further trench electrode layer 4 is then deposited, so that the thickness of the resulting trench electrode layer 4 in the first and second trench 2 , 34 is advantageously increased. This process cycle of deposition and etch-back of the trench electrode layer 4 can be carried out several times if necessary, the last deposited trench electrode layer 4 being etched back up to just above the upper edge of the first and second trenches 2 , 34 .

In a further method step, the insulation collar 7 is introduced in the area of the cover layer 6 in the strap channel 24 and then the insulation collar 7 is filled with a conductive strap filling 17 . The strap filling 17 is then etched back a predetermined amount. The insulation collar 7 is then etched back in the upper region, the etched-back strap filling 17 serving as an etching mask. This process status is shown in Fig. 6H. A strap cap 26 is then applied to the insulation collar 7 and the strap filling 17 . The strap cap 26 is filled up to a predetermined distance above the upper limit of the cover layer 6 and consists of an electrically conductive material. This process status is shown in FIG. 61.

In a further process step, a strap separation mask 46 is introduced into the strap channel 24 , which covers the side walls of the sealing layers 20 of the first and third word lines 28 , 43 . The strap separating mask 46 is preferably formed from Si ₃ N ₄ and defines an etching channel 49 which extends up to the strap cap 26 . This process status is shown in Fig. 6J.

Subsequently, in an etching process, the etching channel 49 is further etched through the strap cap 26 , the strap filling 17 , the trench electrode 4 , the storage dielectric 3 as far as into the upper end of the separating web 35 and into the laterally adjacent vertical plate doping zones 5 . This process status is shown in Fig. 6K.

Subsequently, the intermediate insulation layer 23 is introduced into the etching channel 49 and the first and second strap contacts 37 , 38 are created in this way. This process status is shown in Fig. 6L. The further process steps for producing the bit line contact, for applying the bit line 12 and subsequent metallization levels for completing the memory module are carried out in the customarily known manner, as described in FIG. 3.

Fig. 7 shows a method for manufacturing a third embodiment of a memory cell array. The third embodiment has a memory cell arrangement with a vertical, double gate connection. The memory cell arrangement is produced by covering a P-type silicon substrate 1 with a silicon dioxide and silicon nitride layer as an etching mask. Using a lithography process and an etching process, a trench 2 is first etched out of the silicon substrate 1 via a hard mask. The hard mask is then removed and the trench 2 is subjected to a cleaning process. The walls of the trench 2 are then locally covered with an arsenic-doped glass layer 31 . A vertical plate doping zone 5 is introduced in the lower region of the trench 2 by a subsequent diffusion process. After removal of the mask layers and cleaning of the trench 2 , the trench 2 is filled with a dummy filling 32 . The dummy filling 32 consists, for example, of a silicon dioxide and / or a silicon layer.

In an advantageous embodiment of the method, the trench 2 is slightly bulbously etched in the lower section by a partially isotropic etching method, so that a negative flank angle is generated. In this way, the cross-section increases the opening of the trench 2 towards the top so that the opening of the trench 2 during filling of the trench 2 with the dummy panel 32 is closed is before depressed areas of the trench 2 completely to the dummy stuffing 32 are filled. As a result, in the lower section of the trench 2, along the axis of symmetry, there is an extended blow hole, ie a cavity, which considerably facilitates the subsequent complete releasing of the dummy filling 50 . The dummy filling 50 is designed in such a way that simple and complete triggering is possible using an etching process.

In a subsequent process step, the dummy filling 32 is etched back planarly into the upper part of the trench 2 . Then the exposed areas of the oxide layer, which is formed on the side walls of the trench 2 , are removed. An insulation collar 7 is then introduced in the upper region of the trench 2 by means of a conventional process control by means of multiple layer deposition processes and etch-back processes. The insulation collar 7 is preferably formed from silicon dioxide or silicon nitride. A first strap doping zone 67 is then formed on opposite sides of the trench 2 .

After removal of the auxiliary layers, the upper edge of the insulation collar 7 and the inner wall of the trench 2 are exposed and are covered with a thin silicon dioxide layer. A first insulation plate 55 is then formed using an anisotropic layer deposition method. The thin oxide layer on the inner wall of the trench 2 is then removed again and a gate oxide layer is formed on the inner wall of the trench 2 . The open, upper region of the trench 2 is then filled with a gate layer 51 and planarized down to the silicon nitride layer 53 . This process status is shown in Fig. 7A.

In a further process step, a horizontal plate doping zone 15 and a field insulation layer 9 are formed by means of conventional process steps. The gate layer 51 is then etched back to below the surface of the substrate 1 . Then the exposed side surfaces of the silicon substrate 1 are doped and a third and fourth doping zone 69 , 70 are produced, which represent two source regions. This process status is shown in Fig. 7B. The first and third doping zones and the associated gate layer 51 form a transistor. The second and fourth doping zones and the associated dual gate 51 likewise form a further transistor.

A spacer 54 made of an insulating material is then formed on the exposed side surfaces of the silicon nitride 53 . This process status is shown in Fig. 7C.

In a further process step, the gate layer 51 is anisotropically structured using the spacers 54 as an etching mask and etched down to the first insulation plate 55 . This process status is shown in Fig. 7D. The vertical surfaces of the remaining dual layer 51 are then coated with a silicon oxide layer 56 . This process status is shown in Fig. 7E.

In a subsequent step, the first insulation plate 55 is cut apart to the dummy filling 50 using an anisotropic etching process. This process status is shown in Fig. 7F.

The open trench 2 with the spacers 54 , the vertical silicon dioxide layers 56 and the vertical flanks of the first insulation plate 55 form a sealed etching opening 57 . The dummy filling 50 is completely removed from the trench 2 through the etching opening 57 . This process status is shown in Fig. 7G.

In this process step, all surfaces that are otherwise exposed on the memory chip are sufficiently resistant to the etching solution that is used to remove the dummy filling 50 or are covered by a corresponding sealing layer.

After cleaning the inner wall of the trench 2 , the conformal deposition of the storage dielectric 3 and a trench electrode 4 takes place . The storage dielectric 3 and the trench electrode 4 are preferably deposited using an atomic layer deposition method (ALD). As in the previous embodiments, a metallic material is used to form the trench electrode. This process status is shown in Fig. 7H.

The trench electrode 4 is then selectively etched back to below the upper edge of the insulation collar 7 . The etched-back trench electrode 4 is then used as an etching mask for an isotropic removal of the exposed storage dielectric 3 . This process status is shown in Fig. 7J.

The free surfaces are then covered with a protective layer 71 made of nitride and the strap filling 17 is deposited. This process status is shown in Fig. 7K.

The strap filling 17 is then etched back planar to a level which is arranged just above the first insulation plate 55 . Then a second insulation plate 58 is formed on the strap fill. This process status is shown in Fig. 7L.

The second protective layer 71 is then removed from the surface of the trench 2 . In a further method step, the silicon oxide layer 56 is removed from the gate layer 51 . A word line 8 is then deposited and structured. This process status is shown in Fig. 7M. The further processing of the bit line contacts, the bit line and subsequent metallization levels up to the completion of the memory chip is carried out in a conventional manner.

The design of the storage dielectric 3 and the trench electrode 4 in the exemplary embodiments of FIGS . 4, 5, 6, 7 are to be selected in accordance with the exemplary embodiment of FIG. 1.

On the basis of the described methods, the trench capacitors can be provided with a trench filling which cannot withstand the temperatures used in the manufacture of the transistors without reducing their material parameters. REFERENCE SIGNS LIST 1 semiconductor substrate
2 trenches
3 storage dielectric
4 trench electrode
5 vertical plate doping zone
6 epitaxial layer
7 insulation collar
8 more active word lines
9 field insulation
10 first insulation filling
11 bit line plug
12 bit line
15 horizontal plate doping zone
17 Strap filling
18 transistor
19 word line cover insulation
20 sealing layer
21 drain area
22 Source area
23 intermediate insulation
24 strap channel
25 third shift
26 strap cap
27 passive word line
28 first active word line
29 second active word line
30 more trenches
32 dummy filling
34 second trench
35 separator
36 common connection channel
37 first strap contact
38 second strap contact
39 first strap cap
40 second strap cap
41 further drain area
42 other source areas
43 third word line
44 second contact connection
45 active zone
46 Strap release mask
47 channel
49 etching channel
51 gate layer
53 silicon nitride layer
54 spacers
55 first insulation plate
56 silicon oxide layer
57 etching opening
58 second insulation plate
59 active area
60 cavities
61 Strap window mask
62 etch channel protective layer
63 Strap window hard mask
65 second transistor
67 strap doping zone
69 third doping zone
70 fourth doping zone
71 protective layer

Claims (9)

1. memory module with a substrate ( 1 ) into which memory cells are introduced,
the memory cells having a trench capacitor ( 2 ) and a transistor,
wherein the trench capacitor has at least partially a filling ( 3 , 4 ), and
wherein the transistor ( 22 , 21 , 28 ) has a source, drain ( 21 , 22 ) and a gate connection ( 28 ),
the drain connection ( 21 ) being electrically conductively connected to the trench capacitor ( 3 , 4 ),
the source connection ( 22 ) can be conductively connected to the filling ( 3 , 4 ) depending on a control of the gate connection ( 28 ),
characterized in that
the filling ( 3 , 4 ) at least partially has a material which is unstable at high temperatures, in particular at temperatures above 800 ° C. 2. Memory chip according to claim 1, characterized in that the filling ( 3 , 4 ) has at least partially a metallic material. 3. Memory module according to one of claims 1 or 2, characterized in that the filling ( 3 , 4 ) at least partially comprises a dielectric material with a large dielectric constant. 4. Memory device according to one of claims 1 to 3, characterized in that the wall of the trench ( 2 ) is at least partially covered with a dielectric layer ( 3 ), that on the dielectric layer ( 3 ) at least partially a metallic layer ( 4 ) It is applied that the metallic layer ( 4 ) is electrically connected to the drain connection ( 21 ) of the transistor via a strap filling ( 17 ). 5. Memory module according to one of claims 1 to 4, characterized in that an electrically conductive layer ( 5 ) is formed adjacent to the trench ( 2 ) in the substrate ( 1 ). 6. Memory block according to one of claims 1 to 5, characterized in
that the trench is covered by an epitaxial layer ( 6 ),
that an opening is made in the epitaxial layer ( 6 ),
that a conductive connection between the filling ( 3 , 4 ) and the drain connection ( 21 ) is formed through the opening,
that a dielectric layer ( 3 ) is at least partially applied to the side of the epitaxial layer ( 6 ) which faces the trench ( 2 ). 7. Method for producing a memory cell with a trench capacitor with the following method steps:
Introducing a trench ( 2 ) into a substrate ( 1 );
Filling the trench ( 2 ) at least partially with a dummy filling ( 32 );
Applying a cover layer ( 6 ) to the substrate ( 1 ), which is preferably designed as an epitaxial layer;
Introducing a transistor ( 21 , 22 ) into the cover layer ( 6 );
Removing the dummy fill ( 32 ) from the trench ( 2 );
Introducing a storage dielectric ( 3 ) and a trench electrode ( 4 ) into the trench ( 2 ), a trench capacitor being created and
Forming a connection of the trench electrode ( 4 ) to a connection ( 21 ) of the transistor. 8. The method according to claim 7, characterized in that a channel ( 24 , 57 ) is etched into the cover layer ( 6 ) up to the dummy filling ( 32 ),
that the dummy filling ( 32 ) is etched out via the channel ( 24 , 47 , 57 ),
that a dielectric layer ( 3 ) is at least partially applied to the wall of the trench ( 2 ),
that a conductive layer ( 4 ) is applied to the dielectric layer ( 3 ),
that the conductive layer ( 4 ) is electrically conductively connected to a terminal ( 21 ) of the transistor. 9. The method according to any one of claims 7 or 8, characterized in
that after the etching of the channel ( 47 , 57 ), the side walls of the channel ( 47 , 57 ) are covered with a protective layer ( 62 , 71 ), preferably made of nitride,
that the dummy filling ( 32 ) is then etched out of the trench ( 2 , 3 ).