EP1552546A2

EP1552546A2 - Integrated circuit arrangement comprising a capacitor, and production method

Info

Publication number: EP1552546A2
Application number: EP03757708A
Authority: EP
Inventors: Ralf Brederlow; Jessica Hartwich; Christian Pacha; Wolfgang RÖSNER; Thomas Schulz
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2002-10-18
Filing date: 2003-10-10
Publication date: 2005-07-13
Also published as: CN100468621C; TWI255038B; DE10248722A1; WO2004038770A3; EP2169715A3; CN101286517B; JP4598531B2; US20060003526A1; US20080038888A1; US7820505B2; EP2169715A2; WO2004038770A2; CN101286517A; US8124475B2; US20090184355A1; CN1706027A; TW200411908A; EP2169715B1; JP2006503440A; US7291877B2

Abstract

Disclosed is an integrated circuit arrangement (120), among others, comprising a transistor (122), preferably a FinFET, and a capacitor (124). The lower electrode of the capacitor (124) is disposed within an SOl substrate along with a channel section of the transistor (122). The inventive circuit arrangement (120) is easy to produce and has excellent electronic properties.

Description

description

Integrated circuit arrangement with capacitor and manufacturing process

The invention relates to an integrated circuit arrangement which contains an electrically insulating insulation region and at least one capacitor. The capacitor is formed from a region sequence which, in the order specified, contains: an electrode region near the insulation region, a dielectric region, and an electrode region remote from the insulation region.

The electrically insulating area consists, for example, of an electrically insulating material with a specific resistance greater than 10 ¹² Ωcm (ohm by centimeter) at 20 ° C. room temperature, for example of an oxide, in particular silicon dioxide. The electrode area contains, for example, a metal with a specific electrical resistance less than 10 ^{~ 4} Ωcm at 20 ° C room temperature. Alternatively, the electrode regions contain, for example, polycrystalline silicon which is highly doped. The dielectric region also consists of an electrically insulating material, for example an oxide, in particular silicon dioxide, which has a dielectric constant of approximately 3.9. However, dielectric materials with a much larger dielectric constant in the dielectric range are also used.

It is an object of the invention to provide an easily produced integrated circuit arrangement with a capacitor. The circuit arrangement should be able to be produced in particular with a small number of process steps and in particular using fewer lithographic masks. In addition, a simple manufacturing method for an integrated circuit arrangement with a capacitor is to be specified. The problem related to the circuit arrangement is achieved by an integrated circuit arrangement with the features specified in claim 1. Further developments are specified in the subclaims.

In the circuit arrangement according to the invention, the insulating area is part of an insulating layer arranged in one plane. The capacitor and at least one active component of the integrated circuit arrangement, preferably all active components of the integrated circuit arrangement, are on the same side of the insulating layer. In addition, the electrode region close to the insulating region and the active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged.

The circuit arrangement according to the invention is of simple construction and can be produced in a simple manner because the electrode region close to the insulation region and the active one

Area are on one level. In addition, the electrode region close to the insulation region and also the active region are insulated by the insulation region. Freely selectable potentials can be applied to both electrode areas of the capacitor.

The capacitor also has excellent electronic properties:

The ratio between parasitic capacitances and resistances in relation to the useful capacitance is small, whereby different differential capacitances are due to space charge zones. In the case of analog capacities, the differential capacitance is the capacitance effective at the operating point. the leakage currents are small, the differential non-linearity of the capacitance is small, the capacity is constant over a wide operating point range, the achievable capacity-area ratio is large, for example more than ten femtofarads per square micrometer or even greater than twenty femtofarads per square micrometer.

In addition, no further layer or further layer sequence is required between the active components and the capacitor. This makes it possible to reduce the number of layers required and to increase the planarity of the integrated circuit arrangement.

In a further development, the electrode area close to the insulation area and the active area are semiconductor areas which contain a semiconductor material, ie a material with a specific electrical resistance between 10 ^-5 and 10 ⁺¹² Ωcm, in particular between 10 ^{~ 6} and 10 ⁺¹ ° Ωcm, eg germanium, silicon or gallium arsenide. In one embodiment, the specific resistance of the electrode region of the capacitor close to the insulation region is reduced by doping.

In a further development of the circuit arrangement, the electrode region close to the insulation region and the active region are single-crystalline regions, which may be doped. The electronic properties of active components in single-crystalline layers are particularly good. In addition, the electrical resistance of a single-crystal electrode of the capacitor can be reduced particularly well by doping. In one configuration, the electrode region close to the insulation region and also the active region have a thickness of less than one hundred nanometers or even less than fifty nanometers. Active components that have a very short channel length can be produced in a particularly simple manner in such thin semiconductor layers. In a further development, the insulating layer adjoins a carrier substrate, as is the case with a so-called SOI substrate (Silicon On Insulator). Such substrates can be produced in a simple manner. In addition, the electronic circuits which are arranged on these substrates have particularly good electronic properties.

In a next development, the dielectric region and the electrode region remote from the insulation region are arranged on at least two side surfaces of the electrode region near the insulation region. This measure allows the capacitance of the capacitor to be increased in a simple manner. If the side surfaces lie transversely to the carrier substrate, no or only a small additional chip area is required to increase the capacity. Another measure to increase the capacity is that the electrode areas contain a large number of interlocking webs. The web height is preferably greater than the web width.

In another development, the active component is a field effect transistor: the channel region of the field effect transistor is the active region. If the channel region is undoped, particularly good electronic properties result, in particular with very short channel lengths of, for example, ten nanometers.

The control electrode of the field effect transistor is part of a structured electrode layer in which the electrode region of the capacitor, which is remote from the insulation region, is also arranged. The control electrode and the electrode region remote from the insulating region consist of the same material. The thickness of these areas and their dopant concentration are also the same. - A control electrode insulation area of the field effect transistor in one embodiment consists of the same Material like the dielectric area of the capacitor. The thickness of these areas is also the same.

As a result of this measure, only three layer production processes are required for the production of the capacitor and for the production of the field effect transistor. The areas of the field effect transistor and the capacitor which are in the same layer can be structured together. An additional mask for producing the capacitor is only required if the lower electrode area of the capacitor is doped differently than the channel area of the field effect transistor. A further additional mask is only required if the materials and / or the insulation thicknesses of the control electrode insulation region and the dielectric region of the capacitor differ. But even then, the number of masks required to manufacture the circuit arrangement is still small.

In a further development, the field effect transistor contains a web or a fin. Control electrodes are arranged on opposite sides of the web. This creates a field effect transistor with excellent control properties, for example a so-called FinFET.

In one development, there is a connection area that connects the control electrodes in an electrically conductive manner. In one embodiment, the connection area is separated from the channel area by an insulation area, the insulation thickness of which is greater than the insulation thickness of the control electrode insulation area. These measures prevent edge effects when controlling the transistor.

In another embodiment, the control electrode is adjacent to a silicide area. This measure makes it easier to contact the control electrode. In addition, the connection resistance and the sheet resistance are reduced. In a next development of the circuit arrangement according to the invention, connection regions of the field effect transistor border on the insulating layer. In one embodiment, the connection areas also border on silicide areas. Sufficient material for silicide formation is present if the semiconductor layer in the area of the connection areas has a greater thickness both before and after the silicide formation than in the area of the electrode near the insulation area.

In a next development, spacers are arranged on both sides of the control electrodes, which also contain a different material or consist of a different material than the electrode layer, in particular a material that is not suitable as a starting point for epitaxial layer growth in an epitaxial process for producing a semiconductor epitaxial layer, for example from silicon nitride. By using the spacers, side areas of the control electrode are covered so that no epitaxy can emanate from them and short circuits are avoided.

In one embodiment, a spacer is also arranged on at least one side of the electrode region remote from the insulation region. The spacers have the same task as the spacers arranged on the control electrode. If a spacer arranged on the gate and a spacer arranged on an electrode come into contact, a mask is produced which, for example, prevents doping or silicidation in the masked area.

In a next development, a connection area of the field effect transistor and the electrode area of the capacitor close to the insulation area adjoin one another and thus form an electrically conductive connection. In this way, a simply constructed memory cell of a DRAM (Dynamic Random Access Memory) is created without additional measures. Men are required for contacting the electrode near the insulation area.

In a further development, the side of the electrode region near the insulation region adjacent to a connection region of the transistor is longer than a side of the electrode region near the insulation region, preferably at least twice as long or at least five times as long. In this case, the transistor has a transistor width which is a multiple of the minimum structure width, preferably more than three times or more than five times. These measures result in a particularly low-resistance connection between the transistor and the capacitor. This leads in particular to so-called analog capacities in analog circuits to improve the electronic properties. Examples of such analog circuits are analog-to-digital converters. Another example of an analog capacitance is a so-called bypass capacitance with which voltage peaks can be smoothed out on an operating voltage line or a signal line.

In an alternative development, on the other hand, a side of the electrode area near the insulation area adjacent to the connection area of the electrode area is longer than the side adjacent to the connection area, preferably at least twice as long or at least five times as long. In this case, the transistor has a transistor width that is smaller than three times the minimum structure width, preferably smaller than twice the minimum structure width. This measure, in particular in the case of memory cells, increases the ohmic resistance of the bottom electrode of the capacitor and thus counteracts rapid discharge of the storage capacity.

In another development, the circuit arrangement contains at least one processor which has a large number of logic see switching functions contains. If the circuit arrangement also contains a plurality of DRAM memory units (Dynamic Random Access Memory) in addition to the processor, this is also referred to as embedded memory. To produce this circuit arrangement, in addition to the process steps and masks required in any case for the production of the logic, only a small number of additional process steps and additional masks are required for producing the capacitor or the transistors connected to it in an electrically conductive manner.

In a further aspect, the invention also relates to a method for producing an integrated circuit arrangement, in particular for producing the circuit arrangement according to the invention or one of its developments. In the method according to the invention, the following method steps are carried out without being restricted by the sequence specified:

Providing a substrate containing an insulating layer of electrically insulating material and a semiconductor layer, e.g. an SOI substrate,

Structuring the semiconductor layer to form at least one electrode region for a capacitor and to form at least one active region of a transistor, after structuring the semiconductor layer producing a dielectric layer, after producing the dielectric layer producing an electrode layer, and - forming an electrode of the capacitor remote from the insulation region and a control electrode of the transistor in the electrode layer.

The method according to the invention is particularly suitable for producing a so-called FinFET together with the capacitor. The above-mentioned technical effects of the circuit arrangement according to the invention and its developments also apply to the method according to the invention and its developments.

Exemplary embodiments of the invention are explained below with reference to the accompanying drawings. In it show:

Figures 1A to 16B

Manufacturing stages in the manufacture of an integrated DRAM memory cell,

Figure 17 is a plan view of the memory cell, and

Figure 18 is a plan view of a DRAM memory cell with three transistors.

FIGS. 1A to 16B show production stages in the production of an integrated memory cell, with FIGS. 1A to 16A relating to a section along a section plane I, which lies along a channel of a field effect transistor, in particular along the direction of current flow in FIG

Channel. Figures 1B to 16B each relate to the section along a section plane II, which is transverse to the channel.

The production of the memory cell starts from an SOI substrate 10, which contains a carrier substrate 12 made of single-crystal silicon, a so-called buried insulating layer 14 made of silicon dioxide, for example, and a thin semiconductor layer 16 made of monocrystalline silicon. In the exemplary embodiment, the thickness of the carrier substrate 12 is five hundred and fifty micrometers, the thickness of the insulating layer 14 is one hundred nanometers and the thickness of the semiconductor layer 16 is fifty nanometers. In the manufacturing stage shown in FIG. 1A, there are still no differences along the sectional plane I or II, see FIG. IB.

As shown in FIGS. 2A and 2B, a silicon nitride layer 18 is subsequently deposited on the SOI substrate 10. different, for example with the help of a CVD process (Chemical Vapor Deposition). In the exemplary embodiment, the silicon nitride layer 18 has a thickness of fifty nanometers. A silicon dioxide layer is then deposited over the entire surface of the silicon nitride layer 18, for example a TEOS layer 20 (tetraethyl orthosilicate) with the aid of a TEOS method. In the exemplary embodiment, the TEOS layer 20 has a thickness of seventy-five nanometers. The same conditions still exist along the sectional planes I and II, see FIG. 2B.

In another embodiment, the double layer of silicon nitride layer 18 and TEOS layer 20 is replaced by a single layer. This simplifies the process.

As shown in FIGS. 3A and 3B, a lithography process is then carried out. For this purpose, a photoresist 22 is applied over the entire surface, exposed and developed in accordance with a predetermined layout. The TEOS layer 20, the nitride layer 18 and the semiconductor layer 16 are then structured, for example using a dry etching method. This creates a layer stack 30 or mesa, which tapers to a web area in the area of the sectional plane II, see FIG. 3B, and then widens again. The geometry for the field effect transistor to be manufactured and the capacitor can be specified independently of one another and thus optimized.

The photoresist 22 is then removed. As an alternative to a photolithographic process, an electron beam lithography process or another suitable process is carried out in another exemplary embodiment.

As shown in FIGS. 4A and 4B, a further photolithography process is then carried out, in which an additional mask is required to produce the capacitor. A photoresist layer 32 is applied exposed, developed and structured with the mask. During the structuring, the TEOS layer 20 and the silicon nitride layer 18 above a bottom electrode region 34 in the semiconductor layer 16 are removed. As a result, the stack 30 is divided into a transistor part 30a and a capacitor part 30b.

An ion implantation is then carried out using the structured photoresist layer 32, the bottom electrode region 34 being heavily n-doped, represented by n ⁺⁺ in FIG. 4A and by implantation arrows 40. The semiconductor layer 16 is not doped in the region provided for the transistor. The additional electrode implantation makes the bottom electrode region 34 low-resistance. For example, the doping density is 10 ²⁰ doping atoms per cubic centimeter. The doping density is preferably in the range between 10 ¹⁹ to 10 ²¹ doping atoms per cubic centimeter. With increasing doping density, the dielectric grows faster than on undoped or only moderately heavily doped areas. However, the space charge zones that form become smaller with increasing doping density, so that parasitic effects also become smaller.

The later channel region of the transistor, in particular the side faces of this channel region, are protected by the photoresist layer 32, so that no ions penetrate into these regions, which could cause doping.

As shown in FIGS. 5A and 5B, the photoresist layer 32 is then removed. A thin oxide layer is subsequently produced on all exposed sides of the semiconductor layer 16 and in particular also on the exposed sides of the bottom electrode region 34, which forms the gate oxide 42 or 44 in the region of the transistor and a dielectric 46 in the region of the capacitor. For example, the oxide layer grows thermally. In the embodiment the oxide layer has a thickness of two nanometers in the area of the undoped silicon.

In an alternative embodiment, using a further lithography method, a dielectric made of a different material and / or a dielectric with a different thickness than in the area provided for the transistor is produced in the area of the capacitor.

As shown in FIGS. 6A and 6B, polycrystalline silicon is subsequently deposited in situ or subsequently doped, a polysilicon layer 50 being produced. The polysilicon layer 50 has, for example, a thickness of one hundred nanometers and a dopant concentration of 10 ²¹ dopant atoms per cubic centimeter. The strong n-type doping is again represented by the symbol n ⁺⁺ . Phosphorus atoms, for example, are used as doping atoms.

As shown in FIGS. 7A and 7B, a further TEOS layer 52, which is thicker than the TEOS layer 20, is subsequently deposited on the polysilicon layer 50. In the exemplary embodiment, the thickness of the TEOS layer 52 is one hundred nanometers.

The TEOS layer 52 has a dual function. As explained further below, the TEOS layer 52 initially serves as a hard mask for structuring the control electrode (gate) of the transistor. Thereafter, the TEOS layer 52 serves as an implantation mask, which prevents the gate electrode from being doped again. In this way it is possible to dope the gate electrode and source / drain regions differently. This allows the gate electrode work to be chosen freely.

As shown in FIGS. 8A and 8B, a further lithography process for structuring a gate electrode 54 is then carried out. For this purpose, one in turn Figures not shown photoresist layer applied, exposed and developed. The TEOS layer 52 and the polysilicon layer 50 are then structured, for example etched. This creates the gate electrode 54 in the region of the transistor and a cover electrode 56 in the region of the capacitor. The gate electrode 54 is covered by a TEOS layer region 52a. The cover electrode 56 is covered by a TEOS layer region 52b. The etching stops on the TEOS layer 20. When the polysilicon layer 50 is etched, it is significantly over-etched so that all parasitic polysilicon spacers on the side walls of the layer stack 30a are removed. The side walls are only covered by the thin oxide layer after the etching.

As shown in FIGS. 9A and 9B, a thin silicon nitride layer 60 is subsequently deposited over the entire surface, for example with the aid of a CVD method. The silicon nitride layer 60 has a thickness of fifty nanometers in the exemplary embodiment.

As shown in FIGS. 10A and 10B, the silicon nitride layer 60 is then, in an anisotropic etching process, spacers 60a on the side walls of transistor part 30a, spacers 60b, 60c on the side walls of gate electrode 54 and TEOS layer region 52a, and also a spacer 60d etched back on the side walls of the cover electrode 56 and the TEOS region 52b.

As shown in FIGS. 11A and 11B, the thin TEOS layer 20 is then etched without using a lithography process, ie self-aligning, for example using an RIE (reactive ion etching) process. A TEOS layer region 20a is formed below the spacers 60b, 60c and below the gate electrode 54. A TEOS layer region 20b is formed below the spacer 60d. During the etching, the TEOS layer regions 52a and 52b are also thinned, for example to twenty-five nanometers. Arise thinned TEOS layer regions 52c above the gate electrode 54 and 52d above the top electrode 56. The etching also exposes the silicon nitride layer 18 in regions which are not covered by the TEOS layer region 20a. The spacers 60a to 60d are made by the etching of the

TEOS layer 52 is not attacked, so that they protrude slightly beyond the thinned TEOS layer regions 52c and 52d.

As shown in FIGS. 12A and 12B, the nitride layer 18 is then structured in a self-adjusting manner, with exposed regions of this silicon nitride layer 18 being removed. A nitride layer region 18a remains below the TEOS layer region 20a. A nitride layer region 18b remains below the TEOS layer region 20b. For example, RIE (Reactive Ion Etching) is used for etching.

The spacers 60a to 60d are also shortened. The layer thicknesses and etchings are dimensioned such that the gate electrode 54 is still surrounded on the sides by the spacers 60b and 60c after the etching of the silicon nitride layer 18. From above, the gate electrode 54 is further masked by a sufficiently thick TEOS layer, for example a TEOS layer 52c with a thickness of twenty-five nanometers. The source / drain regions are exposed after the etching of the silicon nitride layer 18.

The spacers 60b and 60c now terminate with the upper surface of the TEOS region 52c. The spacer 60d is flush with the upper surface of the TEOS layer region 52d.

As shown in Figures 13A and 13B, a selective epitaxial procedure is then performed. A monocrystalline epitaxial layer only grows on the exposed source / drain regions of the semiconductor layer 16. Epitaxial regions 62 and 64 arise on monocrystalline

Silicon. The epitaxial regions 62 and 64 extend approximately up to half the height of the TEOS layer regions 20a and 20b. The epitaxial regions 62 and 64 are also referred to as "raised" (elevated) source / drain regions. The thickness of the epitaxial layer for the epitaxial regions 62 and 64 depends primarily on the thickness of the semiconductor layer 16 and the silicidation explained below. Silicidation consumes existing silicon, so that a corresponding amount of silicon is made available for the reaction. This measure avoids "tearing off" the channel connections in the region of the drain / source region.

As shown in Figs. 14A and 14B, an ion implantation, e.g. n ++, i.e. heavily n-doped, carried out to produce the highly doped source / drain regions 70 and 72, see implantation arrows 80. A mask is only required here to separate regions with complementary transistors in a CMOS process (Complementary Metal Oxide Semiconductor). The epitaxial regions 62, 64 and the regions below them of the semiconductor layer 16 are doped with low resistance n + - by the implantation. In addition, a connection is established between the source / drain region 72 and the bottom electrode region 34 of the capacitor. A channel region 82 lying in the semiconductor layer 16 between the source / drain regions 70 and 72 remains undoped.

During the implantation, the TEOS layer regions 52c and 52d serve as an implantation mask. The doping of the gate electrode 54 and the cover electrode 56 are therefore not changed during the implantation.

As shown in FIGS. 15A and 15B, the residues of the TEOS layer 52, ie in particular the TEOS layer regions 52c and 52d, are etched away after the HDD implantation (high density drain). A salicide process (Seif aligned silicide) is then carried out. For this purpose, a nickel layer is deposited over the entire surface, for example. At temperatures of 500 ° C, for example, forms Nickel silicide on epitaxial areas 62, 64, on gate electrode 54 and on top electrode 56, see silicide areas 90 to 96. Instead of nickel, another metal with a melting temperature above 1400 degrees Celsius, in particular a refractory metal, can be used For example, titanium silicide or cobalt silicide.

As shown in FIGS. 16A and 16B, a passivation layer 100 is subsequently applied, for example made of silicon dioxide. Contact holes are etched into the passivation layer 100 and filled, for example, with tungsten, whereby connecting sections 102, 104, 106, 108 and 110 are formed, which lead in this order to the silicide region 90, 94, 96 and 92, respectively. Instead of the two connecting sections 108 and 110 leading to the silicide area 92, only one connecting section is provided in another exemplary embodiment. The connecting sections 102 to 110 are then connected to conductor tracks of one or more metallization layers. A conventional CMOS process is carried out, which is also referred to as a "back end".

FIG. 17 shows a top view of the memory cell 120, which contains a FinFET 122 and a capacitor 124. The capacitor 124 is shown reduced in size in relation to the transistor 122 in all FIGS. 1A to 17.

The effective effective area of the capacitor 124 is as follows:

_Ä = L - B + H - (2 - L + B), where A is the effective area, B the width of the capacitor, L the length of the capacitor, H the height of the bottom electrode region 34 which is entered in FIG. 16A.

A preferred application of such an embedded DRAM capacity is the replacement of medium-sized SRAM Storage units through a fast embedded DRAM, for example in the second and third access levels of a microprocessor memory hierarchy, ie in the second and third level cache. For example, an SRAM memory cell so far has an area of 134 F ² , where F is the minimum structure size. If, for example, a dielectric with a dielectric constant εr equal to twenty-five, for example tantalum pentoxide, is used, a typical embedded DRAM capacitance CMEM of twenty femtofarads per memory cell can be realized according to the following calculations. The oxide capacity is:

COX = εr εO / tphys = 110 fF / μm ² , where tphys is the oxide thickness, which in the exemplary embodiment is two nanometers. The required area AMEM of the storage capacity is:

AMEM = CMEM / COX = 0.18 µm ² .

For a minimum structure width F equal to fifty nanometers, this corresponds to 72 F ² for the capacitance. This area can be produced, for example, with a cuboid-shaped bottom electrode area 34, which has a base area of L • W = 8 F • 6 F, the height H being 1 F. This corresponds to a thirty-three percent reduction in area based on a planar SOI process. For higher heights H, this area gain increases. Including the access transistor, the total area of the FinFET capacitance arrangement is 68 F ² , the FinFET 122 being implemented with a gate contact. The area of the embedded DRAM memory cell is therefore below the SRAM cell size of 134 F ² .

In the invention, a capacitance is integrated in the FET level, that is, in the so-called top silicon on an SOI substrate. In contrast to SOI-CMOS technologies with planar, completely depleted SOI transistors, a FinFET is used, which has better control properties due to the two control channels on the side walls. There is only one additional process step to create the SOI capacity required if the particularly high quality gate dielectric of the transistor is used as the dielectric of the capacitor.

With an effective oxide thickness of one nanometer, a correction of 0.8 nanometers for the gate and top silicon depletion and due to the quantum mechanical effects, the capacity per area is:

COX = 3.9 εO / tfox = 19 fF / μm ² , where tfox is 1.8 nanometers for the electrically effective oxide thickness and εO for the dielectric constant in a vacuum. When using a metal gate, the electrically effective oxide thickness is reduced by about 0.4 nanometers due to the lack of gate depletion, which increases the capacity per area to:

COX = 3.9 εO / tfox = 24 fF / μm ² .

The capacitances according to the invention are also used as so-called bypass capacitances for damping so-called spikes and for damping crosstalk in the voltage supply of the integrated circuit arrangement. They are also ideally suited as analog capacitors, especially in oscillators or analog-digital converters. The capacities are also used for so-called mixed-signal circuits, i.e. for circuits with analog capacities and e.g. storage capacities in memory cells.

In other exemplary embodiments, a separate high-K DRAM dielectric with εr greater than one hundred is used instead of the gate oxide. For example, a dielectric, the barium strontium titanate (BST) or epitaxy

Contains barium strontium titanate. This reduces the space requirement to approx. 22 F ² . The area for the high-K dielectric on the SOI stacks is defined with the aid of a second additional mask. A further advantage compared to previous technology concepts is a planar transition between pure logic blocks and embedded DRAM blocks. Deep vias and contacts are also avoided.

The low leakage current in FinFET transistors and the lower parasitic capacitances, which increase the share of the useful capacity in the total capacitance, also lead to a further reduced embedded DRAM capacitance of CMEM equal to ten femtofarads.

In the exemplary embodiment explained with reference to FIGS. 1A to 17, no LDD doping (lightly doped drain) was carried out. In another exemplary embodiment, LDD doping is also carried out in addition to the HDD doping.

In a further exemplary embodiment, a transistor and the capacitor are arranged at a greater distance from one another and are each connected to their own connecting sections.

In particular in the case of DRAM memory cells (dynamic random access memory) with only one transistor, the connection section 104 is not required. The spacers 60c and 60d can then touch, so that they serve as a mask for the doping of the connection region 70 and for the selective silicidation. A connection region is then formed under the spacers 60c and 60d by diffusion of doping atoms out of the bottom electrode region 34.

FIG. 18 shows a circuit diagram of a DRAM memory cell 200 (dynamic random access memory) with three transistors M1 to M2 and with a capacitor Cs, which have been produced using the method steps explained with reference to FIGS. 1A to 16A. For example, transistor 122 shown in FIG. 17 is transistor M1 in a first case. The Capacitor 124 is then capacitor Cs. In the first case, an electrically conductive connection leads from an additional connection area in the semiconductor layer 16 adjoining the bottom electrode region 34 or from the connection section 104 to the gate of the transistor M2.

Alternatively, in a second case, however, the layout is selected such that transistor 122 corresponds to transistor M2, capacitor 124 again corresponding to capacitor Cs. In the second case, the cover electrode 56 is electrically conductively connected to the one connection area of the transistor M1 and to the gate of the transistor M2.

The circuit of the memory cell 200 contains a subcircuit for writing and a subcircuit for reading, the charge of the capacitor Cs not being changed during reading, so that it is not necessary to refresh this charge after a reading process.

The subcircuit for writing contains the write transistor Ml and the capacitor Cs. The gate terminal of transistor Ml is connected to a write word line WWL. The source terminal of transistor Ml is connected to a write bit line BLl. In a circuit arrangement with particularly good electrical properties in accordance with the above-mentioned first case, the drain connection of the transistor M1 leads to a storage node X, which is formed by the bottom electrode 34 of the capacitor 124. The cover electrode 56 of the capacitor Cs is at a ground potential VSS. In the alternative according to the second case, the drain connection of the transistor Ml leads to a storage node X which is formed by the cover electrode 56 of the capacitor 124. The bottom electrode 34 of the capacitor Cs is at a ground potential VSS.

The subcircuit for reading contains the transistors M2 and M3. The gate connection of transistor M3 is with a read RWL word line connected. The drain connection of the transistor M3 is connected to a read bit line BL2, which is charged, for example, to an operating potential VDD before the start of the reading process. The source terminal of transistor M3 is connected to the one drain terminal of transistor M2. The

The gate of transistor M2 is connected to storage node X. The source terminal of the transistor M2 is at the ground potential VSS.

The transistor M2 takes on the task of an amplifier, so that reliable reading is still possible even if there is a loss of charge on the storage node X. If there is a positive charge on the storage node X, the transistor M2 is in the on state and the precharged read bit line BL2 is discharged during the reading process.

Since the gate-source capacitance of transistor M2 is parallel to capacitor Cs, the effective storage capacitance Ceff increases: Ceff = Cs + CGS (M2), where Cs is the capacitance of capacitor Cs and CGS is the gate-source capacitance of the transistor M2 are. Due to the manufacturing process, the capacities per area of the storage capacitor Cs and the transistor M2 are, for example, the same size, if the gate oxide and the capacitor dielectric are produced in the same dielectric layer and the layer has the same layer thickness everywhere.

The area requirement of the memory cell 200 is determined by the requirements for the effectively effective storage capacity Ceff. With low leakage currents and a high transistor gain, which results in a high read current, the storage capacitor Cs can be reduced. The area required for the capacitor Cs and its electrical properties are the main criteria for the economical production of a storage unit with a multiplicity of storage cells 200. A storage unit with a multiplicity Number of memory cells 200 is suitable for replacing an SRAM in a processor memory hierarchy.

In another exemplary embodiment, a multi-FinFET transistor is used instead of the FinFET transistor, which instead of only one web contains a plurality of webs arranged parallel to one another between its drain connection region and its source connection region.

Claims

claims

1. Integrated circuit arrangement (120),

with an electrically insulating isolation area,

and with at least one region sequence forming a capacitor (124), which contains in the specified order:

an electrode region (34) close to the insulation region,

a dielectric region (46), and

an electrode region (56) remote from the insulation region,

the insulation region being part of an insulation layer (14) arranged in one plane,

the capacitor (124) and at least one active component (122) of the integrated circuit arrangement (120) being arranged on the same side of the insulating layer (14),

and wherein the electrode region (34) close to the insulation region and the active region (82) of the component (122) are arranged in a plane which lies parallel to the plane in which the insulation layer (14) is arranged.

2. The circuit arrangement (120) according to claim 1, characterized in that the electrode region (34) close to the insulation region is a single-crystalline region, preferably a doped semiconductor region,

and / or that the electrode region (34) close to the insulation region and / or the active region (82) has a thickness of less than one hundred nanometers or less than fifty nanometers, and / or that the active region (82) is a single-crystalline region, preferably a semiconductor region which is doped or undoped,

and / or that the insulating layer (14) adjoins a carrier substrate (12) on one side, preferably a carrier substrate that contains a semiconductor material or consists of a semiconductor material, in particular silicon or single-crystal silicon,

and / or that the insulating layer (14) adjoins the electrode region (34) close to the insulating region on the other side,

and / or that the interfaces are preferably completely in two mutually parallel planes,

and / or that the insulating layer (14) contains an electrically insulating material or consists of an electrically insulating material, preferably an oxide, in particular silicon dioxide,

and / or that the active component (122) is a transistor, preferably a field effect transistor, in particular a FinFET.

3rd Circuit arrangement (120) according to Claim 1 or 2, d a d u r c h g e k e n n e e c i n e t that the dielectric region (46) contains silicon dioxide or consists of silicon dioxide,

and / or that the dielectric region (46) consists of a material with a dielectric constant greater than four or greater than ten or greater than fifty,

and / or that the electrode region (56) remote from the insulation region contains silicon, preferably polycrystalline silicon or consists of silicon, preferably polycrystalline silicon,

and / or that the electrode region (56) remote from the insulation region contains a metal or consists of a metal,

and / or that the electrode region (56) remote from the insulation region contains a low-resistance material, preferably titanium nitride, tantalum nitride or rubidium or highly doped silicon magnesium,

and / or that the electrode region (56) remote from the insulation region adjoins a region containing metal semiconductor connections, in particular a silicide region (96).

4. Circuit arrangement (120) according to one of the preceding claims, characterized in that the dielectric region (46) and the electrode region (56) remote from the insulating region have two, three, four or five side surfaces or more are arranged as five side surfaces of the electrode region (34) close to the insulation region,

and / or that the electrode region (34) close to the insulation region contains a multiplicity of webs, the web height of which is preferably greater than the web width, preferably at least twice as large.

5. Circuit arrangement (120) according to one of the preceding claims, characterized in at least one field effect transistor (122), the channel region (82) of which is the active region, the channel region (82) preferably being undoped,

and / or whose control electrode (54) contains the same material and / or material of the same dopant concentration as the electrode region (56) remote from the insulation region, and / or whose control electrode insulation region (42, 44) contains the same material and / or a material with the same thickness as that of the dielectric region (46),

and / or whose control electrode insulation region (42, 44) contains a different material and / or a material with a different thickness than the dielectric region (46).

6. The circuit arrangement (120) according to claim 5, characterized in that the field effect transistor (122) contains at least one bridge,

and / or that a plurality of control electrodes (54) are arranged on opposite sides of the web (30a), preferably two or three control electrodes,

and / or that at least one control electrode (54) adjoins a region containing metal semiconductor connections, in particular a silicide region (92),

and / or that a connection region electrically connects the control electrodes (54), the connection region being preferably separated from the channel region by a thick insulation region (18, 20), which preferably has an insulation thickness which is greater than the thickness of control electrode insulation regions (42, 44) is

and / or wherein the connection region consists of the same material and / or has the same doping strength as the electrode region (56) remote from the insulation region.

7. The circuit arrangement (120) according to claim 5 or 6, characterized by the fact that one connection area or both connection areas (70, 72) of the field effect transistor (122) adjoin the insulating layer (14), and / or that at least one connection area (70, 72) adjoins an area containing a metal semiconductor connection, preferably a silicide area (90, 94),

and / or that the connection regions (70, 72) have a greater thickness than the active region (82).

8. Circuit arrangement (120) according to one of claims 5 to

7, that means that spacers (60b, 60c) are arranged on both sides of the control electrodes (54), which preferably contain a different material than the electrode layer, preferably silicon nitride, or which are made of a different material than the electrode layer, preferably silicon nitride,

and / or that a spacer (60d) is arranged on at least one side of the electrode region (56) remote from the insulating region, which contains a different material, preferably silicon nitride, or consists of a different material than the electrode layer (50), preferably silicon nitride,

and / or that a spacer (60c) arranged on a control electrode (54) and a spacer 60d arranged on the electrode region (56) remote from the insulating region touch.

9. Circuit arrangement (120) according to one of claims 5 to

8, characterized in that a connection region (72) of the field effect transistor (122) and the electrode region (34) of the capacitor (124) close to the insulation region adjoin one another and have an electrically conductive connection at the boundary,

and / or that the connection area (72) adjoining the electrode area (34) does not adjoin an area containing a metal semiconductor connection, and / or that the other connection area (70) adjoins an area containing a metal semiconductor connection.

10. The circuit arrangement (120) according to claim 9, characterized in that the side of the electrode region (34) close to the insulation region (34) adjoining the connection region (72) is longer than a side of the electrode region (34) near the insulation region, preferably at least twice as long or at least five times as long,

wherein the transistor (122) preferably has a transistor width which is a multiple of the minimum structure width (F), preferably more than three times or more than five times,

or that a side of the electrode region (34) close to the insulation region adjacent to the connection region (72) is longer than the side adjacent to the connection region (72), preferably at least twice as long or at least five times so long

wherein the transistor (122) preferably has a transistor width which is less than three times the minimum structure width (F), preferably less than twice the minimum structure width (F).

11. Circuit arrangement (120) according to one of the preceding claims, characterized in that the circuit arrangement contains at least one processor, preferably a microprocessor,

and / or that the capacitor (124) and the active component (122) form a memory cell (120), in particular in a dynamic RAM memory unit, and / or that a memory cell contains either a capacitor (122) and only one transistor (122) or a capacitor (Cs) and more than one transistor (Ml to M3), preferably three transistors (Ml to M3).

12. A method for producing an integrated circuit arrangement (120) with a capacitor (124), in particular a circuit arrangement (120) according to one of the preceding claims,

in which the following procedural steps are carried out without being restricted by the specified sequence:

Providing a substrate (10) which contains an insulating layer (14) made of electrically insulating material and a semiconductor layer (16),

Structuring the semiconductor layer (16) to form at least one electrode region (34) for a capacitor and to form at least one active region (82) for a transistor (122),

after structuring the semiconductor layer (16), producing at least one dielectric layer (42, 44, 46),

after producing the dielectric layer (42, 44, 46) producing an electrode layer (50),

Forming an electrode (56) of the capacitor (124) remote from the insulation region in the electrode layer (50).

13. The method according to claim 12, the steps of:

Applying at least one insulating layer (18, 20) to the semiconductor layer (16) before structuring, preferably a silicon nitride layer (18) and / or an oxide layer (20) with a first thickness,

and / or doping the electrode (34) close to the insulation region, preferably before producing the dielectric layer (42, 44, 46),

and / or producing the dielectric layer (42, 44, 46) simultaneously with a dielectric layer on the active region (82) of the transistor (122),

and / or forming a control electrode (54) of the transistor (122) simultaneously with the formation of the electrode region (56) remote from the insulation region.

14. The method according to claim 12 or 13, characterized by the steps:

Producing an auxiliary layer (52) after producing the electrode layer (50), preferably an auxiliary layer with a greater thickness than the oxide layer (18, 20),

and / or structuring the electrode region (56) remote from the insulation region and / or a control electrode (54) of the transistor using the auxiliary layer (52) as a hard mask.

15. The method according to any one of claims 12 to 14, characterized by the steps:

Applying a further auxiliary layer (60) after structuring a control electrode (54) of the transistor (142), preferably a silicon nitride layer,

and / or anisotropic etching of the further auxiliary layer (60)

16. The method as claimed in one of claims 12 to 15, characterized by the steps: repeated structuring of the insulating layer (18, 20), the thickness of the auxiliary layer (52) preferably being reduced and / or the auxiliary layer (52) not being completely removed,

and / or anisotropic etching of the further auxiliary layer (60) after structuring the insulating layer (20).

17. The method according to any one of claims 12 to 16, characterized by the steps:

Performing a selective epitaxy on exposed areas made of semiconductor material (16) after forming the electrode area (56) remote from the isolation area and / or after structuring a control electrode (54) of the transistor (122),

and / or doping connection regions (70, 72) of the transistor (122) after the isolation region is formed

Electrode region (56) and / or after structuring the control electrode (54) and preferably after the epitaxy.

18. The method according to any one of claims 12 to 17, g e - identifies by the steps:

Removing the auxiliary layer (52), preferably after structuring the insulating layer (18, 20) and / or after performing the selective epitaxy,

and / or selective formation of a metal semiconductor connection, in particular selective silicide formation, on the electrode layer (54) and / or on exposed semiconductor regions (16).