JPS61113271A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To theoretically eliminate the soft error of the bit wire or to enable to significantly reduce it by a method wherein the switching transistor, one of the constituent elements of the memory cell, is formed on the polycrystalline silicon film to be laminated on the insulating layer. CONSTITUTION:2 is the switching transistor and 3 is the bit wire to be formed of an aluminum electrode. 5 is formed on a part of an N<+>-type diffusion region 7 and an inversion layer 10, the inversion layer 10 is formed on an insulating layer 12 and the so-called (semiconductor on insulator) structure is formed. This structure can be obtained by the following method, for example, wherein the polycrystalline silicon film to be laminated on the insulating layer 12 is made to single-crystallize by performing an annealing. As the N<+>-type diffusion region to be formed on the SOI structure is diffused over up to the surface of the insulating film on the SOI structure is diffused over up to the surface of the insulating film on the SOI structure, no depletion layer does exist theoretically. Accordingly, the generation of depletion layers can be completely eliminated excluding some depletion layers to be formed in gate electrodes 1 and the N<+>-type diffusion region in the structure embodiment in this case against that depletion layers are sure to be inevitally formed in the drain of a conventional semiconductor memory element, wherein the SOI structure is not used. Hence, it follows that the soft error of the bit wire due to alpha rays cannot be theoretically generated at all.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor memory element.Conventional structure and problems thereofRecently, development of MOS memory centered on dynamic RAM has progressed, and 256K, IM pit A certain degree of high integration is being carried out. As the number of bits of memory increases, problems such as storage capacity decreases and soft errors due to alpha rays are more likely to occur are becoming more and more serious in practical use.

The configuration of the conventional example and its problems will be explained below with reference to the drawings. Figure 1 shows unit components of a memory cell, 1
2 is a word line, 2 is a switching transistor, 3 is a data line (bit line), 4 is a storage capacitor, and 6 is a plate.

Figures 2a, b and c show some embodiments showing cross-sectional views of the structure of memory cells. In d of the same figure, the data line 3 is formed using an aluminum electrode, and the word line 1 and the gate 6 are formed of polysilicon gates. Further, in the figure, a shows an example in which the data line 3 is formed of a polysilicon electrode, and the word line and plate are formed of polysilicon electrodes. In the figure, 6 is a P-type substrate, 7 is an n+ diffusion layer, and 8 is a p-type substrate.
sG film, 9 is LOCO5, 10 is an inversion layer. A dotted arrow line 11 indicates α rays irradiated into the P substrate. e generated by these α rays is the inversion layer 10 of the memory cell.
This causes soft errors in memory cells. Also, what about bit line 3? This is detected by the depletion layer of the diffusion layer and causes bit line soft errors. Therefore, it is necessary to increase the storage capacity to prevent soft errors, but when doing this by reducing the oxide film thickness, it is necessary to make it thin enough for practical use (~
ioo person) is difficult to do. Also, n+ of bit line 3
Although it is possible to reduce the depletion layer of the diffusion layer by fine patterning, it is difficult to reduce the size to a large extent. In any case, with conventional memory cell configurations, it has not been possible to completely eliminate or significantly reduce α-ray soft errors.

OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide a semiconductor memory element having a structure in which soft errors occurring in conventional semiconductor memory elements can be theoretically eliminated or greatly reduced.

Structure of the Invention In order to achieve this object, in the semiconductor memory element of the present invention, a switching transistor, which is a component of a memory cell, is formed on a silicon film on an insulating layer.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 3 shows a cross-sectional structure of an embodiment of the present invention. 1
is a word line, 2 is a switching transistor, 3 is a bit line made of aluminum electrode, 5 is a plate, 6 is a P-type substrate, 7 is an n+ diffusion region, 8 is a PSG film, 9 is LOcO
311o is an inversion layer, 11 is an irradiated α ray, and 12 is an insulating layer.
1 conductor on inductor
) structure is formed. This structure is, for example, an insulating layer 12
It can be obtained by annealing the polysilicon film laminated thereon to form a single crystal. n formed on S○work
Since the + diffusion region is diffused to the top of the Sol insulating film, there is no depletion layer in principle. However, only a slight depletion layer is formed in the silicon and n+ diffusion layer below the gate electrode 1. Therefore, in the conventional drain that does not use Sol, a depletion layer is inevitably formed, whereas in the structure of this example, there is no depletion layer formed in the gate electrode 1 and the n+ diffusion region. Depletion layers can be eliminated. Therefore, bit line lift errors due to α rays cannot occur in principle at all. Furthermore, the n+ region depletion layer can be removed, the spit line capacitance can be greatly reduced, and the access time can be greatly improved. Furthermore, since the inversion layer forming the storage capacitor can also be formed on Sol, it is clear that soft errors in memory cells can be greatly reduced. This is because the insulating film for forming Sol prevents e generated by α rays from collecting in the inversion layer.

Effects of the Invention As described above, the semiconductor memory element of the present invention can theoretically eliminate or greatly reduce α-ray soft errors, and can also greatly improve access time, and its practical effects are extremely large. There is something.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory cell, and FIG. 2 a and b. C is a cross-sectional structural diagram showing a conventional memory cell, and FIG. 3 is a cross-sectional structural diagram showing an embodiment of the present invention. 1... Bit line, 2... Switching transistor, 3... Forming the bit line!
Electrode, 5...Plate, 6...P-type substrate, 7...n+ diffusion region, 8...PS
G film, 9...-LOCO5, 10...Inversion layer, 11...α ray, 12...Insulating layer film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] 1. A semiconductor memory element comprising a storage capacitor, a switching transistor, a bit line, a write circuit, and a read circuit forming a memory array, and wherein the switching transistor is formed on a silicon film on an insulating layer.