JPS6372150A - Dynamic ram - Google Patents

Abstract

PURPOSE:To realize the high integration without reducing the size of a device by a method wherein an insulated-gate type transistor and a capacitor are formed inside a hole which is made on the main surface of a semiconductor substrate. CONSTITUTION:A source (or a drain) region 22 of an n-channel insulated-gate type transistor is formed on the surface of a P-type semiconductor substrate 21, and a hole 23 which pierced this source region 22 is made inside the P-type semiconductor substrate 21. A drain (or a source) region 24 of an insulated-gate type transistor is formed at the bottom of the hole 23. In addition, a gate insulating film 25 of the insulated-gate type transistor,a gate electrode 26, an interlayer insulating film 27, the first electrode 28 of a capacitor, a capacitor insulating film 29 and the second electrode 30 of the capacitor are laminated in succession along the side wall of the hole 23, and the first electrode 28 is connected to the drain region 24 which is formed at the bottom of the hole 23. Through this constitution, it is possible to raise the integration density without reducing the size of a device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dynamic RAM (hereinafter referred to as D (referred to as RAM).

Among conventional semiconductor memory devices, so-called RAM (Random A
(access memory) devices have various structures, but if the primary purpose is to increase capacity, it is possible to store 1 bit of information with one insulated gate transistor and one capacitor. A so-called one-transistor type DRAM is optimal.

A cell for one bit of this one-transistor type DRAM can be represented by a circuit as shown in FIG. That is, the transistor 1 for reading and writing information
has its gate connected to the word line 2 and its source (or drain) connected to the bit gland 3, the drain (or source) of the read/write transistor 1 connected to one electrode of the charge storage capacitor 4, and further, The other electrode of charge storage capacitor 4 is connected to constant potential point 5 . A suitable structure for a curved DRAM is
For example, it is described in Kazuo Maeda (t!!m, r Ultra LSI Device Handbook JP 292.1893).

A DRAM with this structure is shown in FIG. Figure 4(a)
shows a cross-sectional view of one bit of a conventional DRAM, and the fourth
Figure (b) shows a plan view of the DRAM,
Description will be given with reference to these drawings.

In this DRAM, a source (or drain) region 7 and a drain (or source) region 8 are formed in a P-type semiconductor substrate 6, and a gate insulating film 9 is formed on the semiconductor substrate 6 between the source region 7 and the drain region 8. is formed, a gate electrode 10 is formed on the gate insulating film 9, and a semiconductor substrate 6 is formed.
An insulating film 11 for element isolation is selectively formed thereon, an insulating film 12 for a capacitor is formed between the drain region 8 and the insulating film 11 for element isolation, and the insulating film 12 for a capacitor is formed on the insulating film 12 for a capacitor. 1 electrode 13 is formed, and an interlayer insulating film 14 is formed on the gate electrode and the first electrode 13 of the capacitor.
is formed, and a contact window 1 is formed on this interlayer insulating film 14.
This structure has a bit line 16 connected to the source region 7 through the bit line 5 .

Note that the second electrode 17 of the capacitor is connected to the P-type semiconductor substrate 6.
The capacitor insulating film 12 is formed directly under the capacitor insulating film 12 by making the part directly under the capacitor insulating film 12 a depression type. Further, the gate electrode 10 functions as a word line.

Problems to be Solved by the Invention In the conventional DRAM as described above, an insulated gate transistor and a charge storage capacitor are formed in a positional relationship parallel to the main surface of a semiconductor substrate. Under such a structure, if you try to increase the number of cells mounted on the same semiconductor substrate and increase the storage capacity, you will have to increase the area of the semiconductor substrate (because there is a limit to it, it will be proportionally reduced). As a result, the dimensions of each part must be miniaturized.In this case, the gate length of insulated gate transistors will inevitably become shorter.
Also, the area of the charge storage capacitor becomes smaller. When the gate length of an insulated gate transistor becomes short, the threshold voltage decreases due to the so-called short channel effect, and the leakage current increases in the off-state, causing the charge stored in the charge storage capacitor, that is, the attenuation of stored information. Another problem arises: when the gate length of an insulated gate transistor becomes short, the punch-through voltage between the source and drain decreases, making it impossible to increase the voltage amplitude of the bit line during writing. Furthermore, as the area of the charge storage capacitor becomes smaller, the amount of charge that can be stored decreases, leading to errors during readout, and when information is retained, the content of the information is reversed due to the influence of radiation, so-called software problems.・High probability of error (
The problem also arises.

Means for Solving the Problems The DRA of the present invention for solving the above problems
M is a semiconductor substrate in which a first diffusion region serving as a source or drain region is formed along the surface, a hole penetrating the first diffusion region is formed, and a drain or source region is formed at the bottom of the hole. A second diffusion region is formed, and a gate insulating film, a gate electrode, an interlayer insulating film, a first electrode of a capacitor, an insulating film of a capacitor, and a second electrode of a capacitor are sequentially laminated along the side wall of the hole. and one of the first and second electrodes of the capacitor is connected to the second diffusion region.

Function: In the DRAM of the present invention, the gate length of the insulated gate transistor and the area of the charge storage capacitor can be sufficiently ensured, and the area of the storage portion per one bit can be reduced.

Embodiment An embodiment of the DRAM of the present invention is shown in FIGS. 1 and 2, and will be described with reference to these. FIG. 1(a) is a sectional view taken along the line A-A' parallel to the bit line of the plan view shown in FIG.
FIG. 1(b) is a sectional view taken along line BB', which is perpendicular to the bit line in FIG.

As shown in the figure, a source (or drain) region 22 of an n-channel insulated gate transistor is formed on the surface of a P-type semiconductor substrate 21, and a hole 23 is formed in the P-type semiconductor substrate 21 through the source region 22. It is provided.

A drain (or source) region 24 of an insulated gate transistor is formed at the bottom of the hole 23.

Further, along the side wall of the hole 23, a gate insulating film 25, a gate electrode 26, an interlayer insulating film 27, a first electrode 28, a capacitor insulating film 29, and a second electrode 30 of the insulated gate transistor are formed. The first electrode 28 is sequentially laminated, and the first electrode 28 is connected to the drain region 24 formed at the bottom of the hole 23 .

Note that the channel region 31 of the insulated gate transistor is formed in a portion along the sidewall of the hole 23 in the P-type semiconductor substrate 21.

Further, the source region 22 corresponds to a bit line and is electrically isolated from the adjacent bit line 221 by an element isolation insulating film 32 and a channel stopper region 33. Also,
Gate electrode 26 corresponds to a word line.

In this DRAM structure, the gate length of the insulated gate transistor and the area of the charge storage capacitor are determined by the depth of the hole 23. Therefore, the degree of integration can be increased without reducing the size of the device.

FIG. 2 is a plan view showing an arrangement example in which a plurality of the above DRAM cells are integrated on the same semiconductor substrate. Although the second electrode 30 of the capacitor is present on almost the entire surface, it has been omitted. There is a word line 26, that is, a gate electrode 6, which is also formed in a parallel line and is perpendicular to the bit line 22, that is, the source region 22, which is formed in a parallel line.
It has a structure in which a memory element portion is formed in the inner part 3.

By the way, there is an insulating film 32 for element isolation between the bit lines 22.
are present, and the bit lines 22 are separated from each other.

In the embodiment shown in FIG. 2, the planar shape of the hole is depicted as a square, but this may be any shape such as a circle, an ellipse, or a hexagon. Further, when a plurality of semiconductor devices are integrated on the same semiconductor substrate, the arrangement does not need to follow FIG. 2.

Further, in the embodiment shown in FIG. 1, an example is shown in which the drain region 24 on the bottom surface of the hole 23 is connected to the first electrode of the capacitor, but the invention is not limited to this, and the drain region 24 is connected to the second electrode of the capacitor. It may be connected to an electrode.

Furthermore, in the examples, for convenience of explanation, an n-channel isolated gate transistor on a P-type semiconductor substrate was used, but the same effect can be achieved by using a P-channel insulated gate transistor on an n-type semiconductor substrate. can get.

Effects of the Invention Since the DRAM of the present invention is composed of an insulated gate transistor and a capacitor formed inside a hole drilled on the main surface of a semiconductor substrate, the gate length of the insulated gate transistor and the charge storage capacitor are The area of the hole is determined by the depth rather than the surface area of the hole. As a result,
It is possible to provide a high-performance DRAM that can be highly integrated and the size of the element does not become small.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are cross-sectional views showing embodiments of the DRAM of the present invention, FIG. 2 is a plan view showing an example of the arrangement of the DRAM of the present invention, and FIG. 3 is a cross-sectional view of a one-transistor type DRAM. 1
The circuit diagram of the bit cell, FIGS. 4(a) and 4(b), is a sectional view and a plan view showing a conventional DRAM. 21... P-type semiconductor substrate, 22... Source (or drain) region (bit line), 23...
... Hole, 24 ... Drain (or source region), 25 ... Gate oxide film, 26 ...
... Gate electrode (word line), 27 ... Interlayer insulating film, 28 ... First electrode of capacitor, 2
9... Insulating film of capacitor, 30...
Second electrode of capacitor, 31... Channel region, 32... Insulating film for element isolation, 33...
...Channel stopper area. Name of agent: Patent attorney Toshio Nakao and one other person 21-P
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Claims (1)

[Claims] The first region along the surface serves as the source or drain region.
A hole penetrating the first diffusion region is formed in the semiconductor substrate having a diffusion region formed therein, a second diffusion region serving as a drain or source region is formed at the bottom of the hole, and a second diffusion region is formed on the side wall of the hole. A gate insulating film, a gate electrode, an interlayer insulating film, a first electrode of a capacitor, an insulating film of a capacitor, and a second electrode of a capacitor are sequentially laminated along the first or second electrode of the capacitor. A dynamic RAM characterized in that either one of them is connected to the second diffusion region.