JPS61287162A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS61287162A
JPS61287162A JP60128837A JP12883785A JPS61287162A JP S61287162 A JPS61287162 A JP S61287162A JP 60128837 A JP60128837 A JP 60128837A JP 12883785 A JP12883785 A JP 12883785A JP S61287162 A JPS61287162 A JP S61287162A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
groove
channel transistor
memory device
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60128837A
Other languages
Japanese (ja)
Inventor
Kenichi Yasuda
憲一 安田
Hiroshi Miyamoto
博司 宮本
Kazutami Arimoto
和民 有本
Koichiro Masuko
益子　耕一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60128837A priority Critical patent/JPS61287162A/en
Publication of JPS61287162A publication Critical patent/JPS61287162A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To isolate a P channel transistor and an N channel transistor, and to prevent a latch-up effectively by a small area by cutting a groove to the surface of a semiconductor substrate. CONSTITUTION:An insulating film 18 is buried and formed into a groove 15 cut onto a semiconductor substrate 14. In such constitution, an N-P-N type transistor faultily shaped by an N<+> diffusion layer 8, the P-type semiconductor substrate 14 and an N-well 11 is isolated by the groove 15. Accordingly, a latch-up can be prevented without requiring a large area.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体記憶装置、特にダイナミックメモリ
のメモリセルに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a memory cell of a dynamic memory.

〔従来の技術） 第４図はトランスファゲートにＣＭＯＳトランジスタを
用いたメモリセルの回路図であり、１はビット線、２．
３はワード線、４はｎチャンネルトランジスタ、５はｐ
チャンネルトランジスタ、２０は両トランジスタ４．５
からなるトランスファゲート、６はメモリキャパシタで
ある。[Prior Art] FIG. 4 is a circuit diagram of a memory cell using a CMOS transistor as a transfer gate, in which 1 is a bit line, 2.
3 is a word line, 4 is an n-channel transistor, and 5 is a p
Channel transistor, 20 is both transistor 4.5
6 is a memory capacitor.

第３図は第４図の回路を半導体基板上に形成した例の断
面図である。７．８はｎ十拡散層、９゜１０はｐ十拡散
層、１１はｎ−ウェル、１２゜ｌ３はポリシリコン等で
形成される導電層、１８は絶縁膜、１４はｐ形半導体基
板である。FIG. 3 is a sectional view of an example in which the circuit of FIG. 4 is formed on a semiconductor substrate. 7.8 is an n-10 diffusion layer, 9.10 is a p-10 diffusion layer, 11 is an n-well, 12.13 is a conductive layer formed of polysilicon, etc., 18 is an insulating film, and 14 is a p-type semiconductor substrate. be.

このうち上記２．７．８は上記トランジスタ４を形成す
るものであり、上記３，９．１０は上記トランジスタ５
を形成するものであり、また上記１２．１３は上記メモ
リキャパシタ６を形成するものである。Of these, the above 2.7.8 forms the above transistor 4, and the above 3, 9.10 form the above transistor 5.
12 and 13 form the memory capacitor 6.

次に動作について説明する。ワード線２．３には常に相
反する電圧が印加されており、メモリセルが選択される
と、ワード線２にＨ”、ワード線３に“Ｌ”の信号が印
加される。するとトランジスタ４，５がオンするのでビ
ット線１とメモリキャパシタ６が接続され、情報の書き
込み、読み出しを行なうことができる。情報が“Ｈ”の
場合は、ｐチャンネルトランジスタ５が、′Ｌ３の場合
はｎチャンネルトランジスタ４がそれぞれ効果的に作用
するので、トランジスタ４．５のしきい値電圧による情
報量の減少なしに書き込み、読み出しができる。Next, the operation will be explained. Opposite voltages are always applied to the word lines 2 and 3, and when a memory cell is selected, an H" signal is applied to the word line 2 and an "L" signal is applied to the word line 3. Then, the transistor 4, 5 is turned on, the bit line 1 and the memory capacitor 6 are connected, and information can be written and read.When the information is "H", the p-channel transistor 5 is turned on, and when the information is 'L3, the n-channel transistor 5 is turned on. Since the transistors 4 and 4 act effectively, writing and reading can be performed without reducing the amount of information due to the threshold voltage of the transistors 4 and 5.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、この従来の構成では、ｎ上拡散層８．　
　ｐ型半導体基板１４．ｎ−ウェル１１によってｎｐｎ
型トランジスタが擬似的に形成され、これによって０Ｍ
Ｏ３）ランジスタ部分においてラッチアンプが起こる可
能性があった。そのためｎ−ウェル１１とｎ十拡散層７
．８の距離を大きくとるなどの必要があり、レイアウト
上不利であった。However, in this conventional configuration, the n-top diffusion layer 8.
p-type semiconductor substrate 14. npn by n-well 11
type transistor is formed in a pseudo manner, thereby 0M
O3) There was a possibility that latch amplifier would occur in the transistor part. Therefore, the n-well 11 and the n-well diffusion layer 7
．． It was necessary to increase the distance between the 8 and 8, which was disadvantageous in terms of layout.

この発明は上記のような問題点を解消するためになされ
たもので、大きな面積を用いずにｐチャンネルトランジ
スタとｎチャンネルトランジスタの分離を効果的に行な
うことのできる半導体記憶装置を提供することを目的と
する。This invention was made to solve the above problems, and aims to provide a semiconductor memory device that can effectively separate a p-channel transistor and an n-channel transistor without using a large area. purpose.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体記憶装置は、半導体基板上に溝を
堀り、ｐチャンネルトランジスタとｎチャンネルトラン
ジスタをこの溝により分離したものである。In the semiconductor memory device according to the present invention, a trench is dug on a semiconductor substrate, and a p-channel transistor and an n-channel transistor are separated by the trench.

〔作用〕[Effect]

この発明においては、溝を堀ることによって、少ない面
積で効果的にｐチャンネルトランジスタとｎチャンネル
トランジスタを分離でき、ランチアンプを防止すること
ができる。In this invention, by digging the groove, the p-channel transistor and the n-channel transistor can be effectively separated with a small area, and launch amplifiers can be prevented.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図において、第３図と同一符号は同一部分を示し、１５
は半導体基板１４上に堀られた溝であり、溝１５の内部
には絶縁１ｒｉｓが埋め込み形成されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals as in Fig. 3 indicate the same parts, and 15
is a groove dug on the semiconductor substrate 14, and an insulating layer 1ris is embedded inside the groove 15.

このような構成においては、従来例で見られるようなｎ
上拡散層８．ｐ形半導体基板１４．ｎ−ウェル１１によ
って擬似的に形成されるｎｐｎ形トランジスタが溝１５
によって分離されるため、大きな面積を必要とすること
なく、ラッチアップを防止することができる。In such a configuration, n
Upper diffusion layer 8. p-type semiconductor substrate 14. An npn type transistor formed pseudo-by the n-well 11 is connected to the trench 15.
Because they are separated by a large area, latch-up can be prevented without requiring a large area.

第２図は本発明の他の実施例を示す。図において、８．
９はその一部が溝１５の側面部分にまで及ぶよう形成さ
れたｎ十拡散層及びｐ十拡散層、１６は半導体基板１４
上に絶縁膜１８を介してその一部が溝１５の内部まで延
びるように形成された導電層であり、ポリシリコン等に
より形成される。１７７はｎ上拡散層８とｐ十拡散層９
を接続するアル文ニウム線である。FIG. 2 shows another embodiment of the invention. In the figure, 8.
Reference numeral 9 indicates an n+ diffusion layer and a p+ diffusion layer, which are formed so as to partially extend to the side surface of the groove 15, and 16 indicates a semiconductor substrate 14.
This is a conductive layer formed on top with an insulating film 18 interposed therebetween so that a portion thereof extends into the groove 15, and is made of polysilicon or the like. 177 is the n upper diffusion layer 8 and the p upper diffusion layer 9
This is the aluminum wire that connects the.

この実施例においては、メモリキャパシタは、導電層１
６と”ｊ　　ｐ＋拡散層８，９間に形成され、このメモ
リセルにおいては、溝１５によってラッチアップが防止
されるのみならず、溝１５の側面をメモリキャパシタに
使用することにより、少ない面積でキャパシタの容量を
増加することができる。In this embodiment, the memory capacitor includes conductive layer 1
In this memory cell, the groove 15 not only prevents latch-up, but also uses the side surface of the groove 15 for the memory capacitor, which allows the memory cell to be formed with a small area. Capacity of the capacitor can be increased.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、半導体基板表面に溝
を堀ることにより、ｐチャンネルトランジスタとｎチャ
ンネルトランジスタを分離したので、ラッチアップの防
止を少ない面積で効果的に行なうことができる効果があ
る。As described above, according to the present invention, since the p-channel transistor and the n-channel transistor are separated by digging a groove in the surface of the semiconductor substrate, latch-up can be effectively prevented with a small area. There is.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例によるメモリセルの断面図
、第２図はこの発明の他の実施例によるメモリセルの断
面図、第３図は従来のメモリセルの断面図、第４図はメ
モリセルの回路図である。 図において、１はビット線、２．３はワード線、４はｎ
チャンネルトランジスタ、５はｐチャンネルトランジス
タ、２０はトランスファゲート、６はメモリキャパシタ
、７．８はｎ十拡散層、９゜１０はｐ十拡散層、１１は
ｎウェル、１２．１３はポリシリコン、１４はｐ形半導
体基板、１８は絶縁膜である。 なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view of a memory cell according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of a memory cell according to another embodiment of the present invention, FIG. 3 is a cross-sectional view of a conventional memory cell, and FIG. is a circuit diagram of a memory cell. In the figure, 1 is a bit line, 2.3 is a word line, and 4 is n
Channel transistor, 5 is a p-channel transistor, 20 is a transfer gate, 6 is a memory capacitor, 7.8 is an n+ diffusion layer, 9°10 is a p+ diffusion layer, 11 is an n-well, 12.13 is polysilicon, 14 1 is a p-type semiconductor substrate, and 18 is an insulating film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板上にマトリックス状に配置され、情報
を蓄積するキャパシタとデータをアクセスするトランス
ファゲートより構成されるメモリセルを有する半導体記
憶装置において、 上記トランスファゲートはｐチャンネルトランジスタと
ｎチャンネルトランジスタにより構成され、 上記ｐチャンネルトランジスタとｎチャンネルトランジ
スタは上記半導体基板上に堀られた溝により分離されて
いることを特徴とする半導体記憶装置。(1) In a semiconductor memory device having memory cells arranged in a matrix on a semiconductor substrate and consisting of capacitors for storing information and transfer gates for accessing data, the transfer gates are composed of p-channel transistors and n-channel transistors. A semiconductor memory device comprising: the p-channel transistor and the n-channel transistor are separated by a trench dug on the semiconductor substrate. （２）上記キャパシタは上記半導体基板上に絶縁膜を介
して形成された第１及び第２の導電層により構成されて
いることを特徴とする特許請求の範囲第１項記載の半導
体記憶装置。(2) The semiconductor memory device according to claim 1, wherein the capacitor is constituted by first and second conductive layers formed on the semiconductor substrate with an insulating film interposed therebetween. （３）上記キャパシタは上記半導体基板内にその一部が
溝の側面部分にまで及ぶよう形成されたｎ＋拡散層及び
ｐ＋拡散層と、上記半導体基板上に絶縁層を介してその
一部が溝の内部にまで及ぶよう形成された導電層とによ
り構成されていることを特徴とする特許請求の範囲第１
項記載の半導体記憶装置。(3) The capacitor includes an n+ diffusion layer and a p+ diffusion layer formed in the semiconductor substrate so that a part thereof extends to the side surface of the groove, and a part of the capacitor formed in the groove on the semiconductor substrate through an insulating layer. and a conductive layer formed to extend into the interior of the claim 1.
The semiconductor storage device described in 1.
JP60128837A 1985-06-13 1985-06-13 Semiconductor memory device Pending JPS61287162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60128837A JPS61287162A (en) 1985-06-13 1985-06-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60128837A JPS61287162A (en) 1985-06-13 1985-06-13 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS61287162A true JPS61287162A (en) 1986-12-17

Family

ID=14994620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60128837A Pending JPS61287162A (en) 1985-06-13 1985-06-13 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS61287162A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001003190A1 (en) * 1999-06-30 2001-01-11 Hitachi, Ltd. Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001003190A1 (en) * 1999-06-30 2001-01-11 Hitachi, Ltd. Semiconductor integrated circuit device

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