US20020005537A1 - DRAM with vertical transistors and deep trench capacitors - Google Patents
DRAM with vertical transistors and deep trench capacitors Download PDFInfo
- Publication number
- US20020005537A1 US20020005537A1 US09/826,014 US82601401A US2002005537A1 US 20020005537 A1 US20020005537 A1 US 20020005537A1 US 82601401 A US82601401 A US 82601401A US 2002005537 A1 US2002005537 A1 US 2002005537A1
- Authority
- US
- United States
- Prior art keywords
- disposed
- deep trench
- gate
- wordlines
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims description 15
- 238000003860 storage Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000005520 cutting process Methods 0.000 description 10
- 230000010354 integration Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
Definitions
- the present invention relates to a dynamic random access memory (DRAM).
- DRAM dynamic random access memory
- the present invention relates to a DRAM with vertical transistors and deep trench capacitors.
- DRAM is such an important semiconductor device in the information and electronics industry.
- One of the most used DRAM cell array is an open bitline structure, in which each memory cell is arrayed with a matrix.
- Each memory cell using label 10 as an example, comprises a transistor 12 , a storage capacitor 14 , a bitline 22 , a wordline 18 and a passing wordline 20 .
- a transistor 12 When an approproate voltage is applied to the bitline 22 and the wordline 18 , data can be written into or read from the capacitor 14 .
- bitlines 22 and 24 are switched to differential sense amplifier.
- FIG. 10 is a cross-sectional view of the memory cell 10 in FIG. 9.
- the wordline 18 is also used as a gate of the transistor 12 .
- the passing wordline 20 is located over the thick oxide layer 36 , and works no function for operation of the memory cell 10 .
- the bitline 22 is connected to a source 40 of the transistor 12 through a contact window 38 .
- a drain 42 of the transistor 12 is connected to the deep trench capacitor 44 through a buried strap 41 .
- An object of the present invention is to provide a DRAM cell array with a vertical transistor and a deep trench capacitor, so as to release the limitation from the wordline to deep trench to increase the integration of the DRAM.
- Another object of the present invention is to provide an open bitline DRAM with a vertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
- Another object of the present invention is to provide a folder bitline DRAM with avertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
- Another object of the present invention is to provide a folder bitline DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window, so as to increase the integration of the DRAM.
- the present invention provides a DRAM cell with a vertical transistor and a deep trench capacitor.
- a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode is desposed in a substrate; a gate of the vertical transistor is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and the upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer of the vertical transistor is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region.
- a shallow trench isolation is disposed on another sidewall of the ion doped layer.
- the present invention provides an open bitline DRAM with straight wordlines, wherein each DRAM cell is as mentioned above, the deep trench capacitors are arranged in a matrix in the substrate.
- the present invention provides an open bitline DRAM with zigzag wordlines, wherein each DRAM cell is as mentioned above.
- the deep trench capacitors belonging to different rows are arranged with a shift.
- the present invention provides a folder bitline DRAM, wherein each DRAM cell is as mentioned above.
- the present invention provides a folder bitline DRAM with borderless bitline contact window, wherein each DRAM cell is as mentioned above.
- FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor in accordance with first and second embodiments of the present invention
- FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;
- FIG. 3 is a layout diagram of another open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;
- FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor in accordance with a third embodiment of the present invention.
- FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is showed in FIG. 4, and the cross-sectional view of the cutting line V-V is showed in FIG. 5;
- FIG. 7 is a cross-sectional diagram of a DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window in accordance with a fourth embodiment of the present invention.
- FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, wherein the cross-sectional view of the cutting line VII-VII is showed in FIG. 7;
- FIG. 9 is a layout diagram of a conventional and most used folder bitline DRAM.
- FIG. 10 is a cross-sectional view of the memory cell in FIG. 9.
- the four embodiments include DRAM cell arrays with an open bitline and a folded bitline, a folder bitline DRAM cell array, and a folder bitline DRAM cell array with borderless bitline contact window.
- FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor of the present invention.
- FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1.
- the deep trench capacitors 102 arranged in a matrix are formed in the substrate 100 .
- Each of the deep trench capacitors 102 comprises an upper electrode 102 a , an insulating film 102 b and a storage electrode 102 c .
- a vertical transistor 104 comprising a gate 104 a , a gate insulating layer 104 b , a source 104 c and a common drain 104 d is disposed over each deep trench capacitor 102 .
- the gate 104 a comprises an upper portion, which is not embedded in the substrate 100 , and a lower portion, which is embedded in the substrate 100 .
- the gate-insulating layer 104 b is disposed on the sidewall of the lower portion of the gate 104 a .
- a vertical region between the source 104 c and the common drain 104 d is a channel region 109 .
- An insulating layer 108 and an ion-doped layer 106 are disposed between the gate 104 a and the upper electrode 102 a of the capacitor 102 .
- the source 104 c is disposed on the sidewall of the ion-doped layer 106 .
- a shallow trench isolation 110 is disposed at least on another sidewall of the ion doped layer 106 .
- the insulating layer 108 is disposed between the gate 104 a and the ion doped layer 106 , so as to isolate the gate 104 a and the ion doped layer 106 with each other.
- Wordlines 118 a , 118 b , 118 c and 118 d are also functioned as gates 104 a of the transistors 104 . Moreover, two adjacent wordlines 118 a and 118 b , or 118 c and 118 d share a common drain 104 d in an active region 112 . The region outside the active region 112 is the shallow trench isolation 110 . The bitlines 6 116 a and 116 b perpendicular to the wordline 118 a , 118 b , 118 c and 118 d are connected with the common drains 104 d through contact windows 114 in different rows respectively.
- Second Embodiment a DRAM Cell Array with a Folded Bitline
- FIG. 3 is a layout diagram of an open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is as showed in FIG. 1.
- the deep trench capacitors 102 substantially corresponding to the adjacent bitlines 116 a and 116 b are arranged with a shift. That is, the deep trench capacitor 102 corresponding to the bitline 116 b is opposite to the common drain 104 d corresponding to the bitline 116 a . Under the above-mentioned layout, the isolation between the deep trench capacitor 102 corresponding to the bitline 116 a and the deep trench capacitor 102 corresponding to the bitline 116 b are enhanced. Moreover, the wordlines 118 a , 118 b , 118 c and 118 d run zigzag and are parallel with each other.
- FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor.
- FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is shown in FIG. 4, and the cross-sectional view of the cutting line V-V is shown in FIG. 5.
- the structures of a deep trench capacitor 402 and a vertical transistor 404 are the same as the first and second embodiments substantially.
- the deep trench capacitor 402 comprises an upper electrode 402 a , an insulating film 402 b , and a storage electrode 402 c .
- a vertical transistor 404 comprising a gate 404 a , a gate insulating layer 404 b , a source 404 c and a common drain 404 d is disposed over each deep trench capacitor 402 .
- the gate-insulating layer 404 b is disposed on a sidewall of the lower portion of the gate 404 a .
- a vertical region between the source 404 c and the common drain 404 d is a channel region 409 .
- An insulating layer 408 and an ion-doped layer 406 are disposed between the gate 404 a and the upper electrode 402 a of the capacitor 402 .
- the source 404 c is disposed on the sidewall of the ion-doped layer 406 .
- a shallow trench isolation 410 is disposed at least on another sidewall of the ion doped layer 406 .
- the insulating layer 408 is disposed between the gate 404 a and the ion doped layer 406 so as to isolate the gate 404 a and the ion doped layer 406 with each other.
- each active region 412 such as corresponding to the bitline 416 a , comprises two deep trench capacitors 402 , two wordlines 418 a and 418 d corresponding to the two deep trench capacitors 402 , and two passing wordlines 418 b and 418 c disposed between the two wordlines 418 a and 418 d .
- the wordlines 418 a and 418 d corresponding to the active region 412 below the bitline 416 a are functioned as gates 404 a of the transistors 404 .
- the deep trench capacitors 402 are under the gates 404 a .
- the region outside the active region 412 is the shallow trench isolation 410 .
- contact windows 414 are disposed between the gates 404 a and the passing wordlines 418 b and 418 c and connected with the bitline 416 .
- the bitline 416 is substantially parallel with the active region 412 and perpendicular with the wordlines 418 a and 418 d and the passing wordlines 418 b and 418 c.
- FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, and the cross-sectional view of the cutting line VII-VII is shown in FIG. 7.
- the deep trench capacitors 702 arranged in rows and columns are formed in the substrate 700 .
- the deep trench capacitors 702 belonging to different rows are arranged with a shift.
- Each of the deep trench capacitors 702 comprises an upper electrode 702 a , an insulating film 702 b and a storage electrode 702 c .
- a vertical transistor 704 comprising a gate 704 a , a gate insulating layer 704 b , a source 704 c and a common drain 704 d is disposed over each deep trench capacitor 702 .
- the gate-insulating layer 704 b is disposed on a sidewall of the lower portion of the gate 704 a .
- a vertical region between the source 704 c and the common drain 704 d is a channel region 709 .
- An insulating layer 708 and an ion-doped layer 706 are disposed between the gate 704 a and the upper electrode 702 a of the capacitor 702 .
- the source 704 c is disposed on the sidewall of the ion-doped layer 706 .
- a shallow trench isolation 710 is disposed on at least one other sidewall of the ion doped layer 706 .
- the insulating layer 708 is disposed between the gate 704 a and the ion doped layer 706 , so as to isolate the gate 704 a and the ion doped layer 706 with each other.
- the gate 704 a and the passing wordline are disposed over each deep trench capacitor 702 .
- a part of the shallow trench isolation 710 is expanded to cover a part of the deep trench capacitor 702 , and the passing wordline is disposed on the part of the shallow trench isolation 710 .
- each active region 712 such as corresponding to the bitline 716 b and the wordlines 718 a ′′ and 718 b ′, comprises two deep trench capacitor 702 , two wordlines 718 a ′′ and 718 b ′ corresponding to the two deep trench capacitors 702 , and a common drain 704 d between the wordlines 718 a ′′ and 718 b ′.
- Two passing wordlines 718 a ′ and 718 b ′′ are disposed outside the two wordlines 718 a ′′ and 718 b ′.
- the wordlines 718 a ′′ and 718 b ′ corresponding to the active region 712 below the bitline 716 b are functioned as gates 704 a of the transistors 704 .
- the region outside the active region 712 is a shallow trench isolation 710 .
- bitlines 716 a , 716 b , 716 c and 716 d are connected with the common drain 704 d through contact windows 714 .
- the bitlines 716 are perpendicular to the wordlines (or passing wordlines) 718 a ′, 718 a ′′, 718 b ′, 718 b ′′, 718 c ′, 718 c ′′, 718 d ′ and 718 d ′′.
- the contact window 714 cannot meet with the common drain 704 d , even if misalignment happens in the photolithography process. Therefore, no short circuit happens.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is desposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folder bitline DRAM, and a foler bitline DRAM with bordless bitline contact window.
Description
- 1. Field of the Invention
- The present invention relates to a dynamic random access memory (DRAM). In particular, the present invention relates to a DRAM with vertical transistors and deep trench capacitors.
- 2. Description of the Related Art
- With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. DRAM is such an important semiconductor device in the information and electronics industry.
- Most of the DRAMs nowadays have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 64 megabits, and can even reach 256 megabits. Therefore, under the increasing of the integration it is needed to shrink the size of the memory cell and the transistor so as to manufacture the DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure itself can reduce its occupation area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 64 megabits and above. Referring to a traditional plane transistor, it covers quite a few areas of the semiconductor substrate and cannot satisfy the request of high integration. Therefore, a vertical transistor which can save space is a trend of fabrication of a memory unit.
- One of the most used DRAM cell array is an open bitline structure, in which each memory cell is arrayed with a matrix.
- Another frequently used DRAM cell array is a folded bitline structure, as shown in FIG. 9. Each memory cell, using
label 10 as an example, comprises atransistor 12, astorage capacitor 14, abitline 22, awordline 18 and apassing wordline 20. When an approproate voltage is applied to thebitline 22 and thewordline 18, data can be written into or read from thecapacitor 14. When an output volage is applied to thememory cell 10 covering the connectingwordline 18 and thepassing wordline 20,bitlines - FIG. 10 is a cross-sectional view of the
memory cell 10 in FIG. 9. Thewordline 18 is also used as a gate of thetransistor 12. Thepassing wordline 20 is located over thethick oxide layer 36, and works no function for operation of thememory cell 10. Thebitline 22 is connected to asource 40 of thetransistor 12 through acontact window 38. Adrain 42 of thetransistor 12 is connected to thedeep trench capacitor 44 through a buriedstrap 41. - However, such structure of the
memory cell 10 has some challenges as described below. The outdiffusion of the dopants contained in the buriedstrap 41 may induce the short channel effect. Therefore, it is impossible to decrease the distance between thewordline 18 anddeep trench capacitor 44 to increase the integration of the DRAM. - With the enhancement of the memory capacity, a DRAM with more compact transistors and deep trench capacitors is needed to satisfy the requirements of memory capacity.
- An object of the present invention is to provide a DRAM cell array with a vertical transistor and a deep trench capacitor, so as to release the limitation from the wordline to deep trench to increase the integration of the DRAM.
- Another object of the present invention is to provide an open bitline DRAM with a vertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
- Another object of the present invention is to provide a folder bitline DRAM with avertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
- Another object of the present invention is to provide a folder bitline DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window, so as to increase the integration of the DRAM.
- The present invention provides a DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode is desposed in a substrate; a gate of the vertical transistor is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and the upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer of the vertical transistor is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. Moreover, a shallow trench isolation is disposed on another sidewall of the ion doped layer.
- The present invention provides an open bitline DRAM with straight wordlines, wherein each DRAM cell is as mentioned above, the deep trench capacitors are arranged in a matrix in the substrate.
- The present invention provides an open bitline DRAM with zigzag wordlines, wherein each DRAM cell is as mentioned above. The deep trench capacitors belonging to different rows are arranged with a shift.
- The present invention provides a folder bitline DRAM, wherein each DRAM cell is as mentioned above.
- The present invention provides a folder bitline DRAM with borderless bitline contact window, wherein each DRAM cell is as mentioned above.
- The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:
- FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor in accordance with first and second embodiments of the present invention;
- FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;
- FIG. 3 is a layout diagram of another open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1;
- FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor in accordance with a third embodiment of the present invention;
- FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is showed in FIG. 4, and the cross-sectional view of the cutting line V-V is showed in FIG. 5;
- FIG. 7 is a cross-sectional diagram of a DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window in accordance with a fourth embodiment of the present invention;
- FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, wherein the cross-sectional view of the cutting line VII-VII is showed in FIG. 7;
- FIG. 9 is a layout diagram of a conventional and most used folder bitline DRAM; and
- FIG. 10 is a cross-sectional view of the memory cell in FIG. 9.
- Detailed descriptions of DRAMs with vertical transistors and deep trench capacitors are given hereafter, by the accompanying four embodiments. The four embodiments include DRAM cell arrays with an open bitline and a folded bitline, a folder bitline DRAM cell array, and a folder bitline DRAM cell array with borderless bitline contact window.
- First Embodiment: a DRAM Cell Array with an Open Bitline
- FIG. 1 is a cross-sectional diagram of a DRAM with a vertical transistor and a deep trench capacitor of the present invention. FIG. 2 is a layout diagram of an open bitline DRAM in accordance with the first embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is showed in FIG. 1.
- The
deep trench capacitors 102 arranged in a matrix are formed in thesubstrate 100. Each of thedeep trench capacitors 102 comprises anupper electrode 102 a, aninsulating film 102 b and astorage electrode 102 c. Avertical transistor 104 comprising agate 104 a, agate insulating layer 104 b, asource 104 c and acommon drain 104 d is disposed over eachdeep trench capacitor 102. Thegate 104 a comprises an upper portion, which is not embedded in thesubstrate 100, and a lower portion, which is embedded in thesubstrate 100. The gate-insulatinglayer 104 b is disposed on the sidewall of the lower portion of thegate 104 a. A vertical region between thesource 104 c and thecommon drain 104 d is achannel region 109. - An insulating
layer 108 and an ion-dopedlayer 106 are disposed between thegate 104 a and theupper electrode 102 a of thecapacitor 102. Thesource 104 c is disposed on the sidewall of the ion-dopedlayer 106. Ashallow trench isolation 110 is disposed at least on another sidewall of the ion dopedlayer 106. The insulatinglayer 108 is disposed between thegate 104 a and the ion dopedlayer 106, so as to isolate thegate 104 a and the ion dopedlayer 106 with each other. - Wordlines118 a, 118 b, 118 c and 118 d are also functioned as
gates 104 a of thetransistors 104. Moreover, twoadjacent wordlines common drain 104 d in anactive region 112. The region outside theactive region 112 is theshallow trench isolation 110. The bitlines 6 116 a and 116 b perpendicular to thewordline common drains 104 d throughcontact windows 114 in different rows respectively. - Second Embodiment: a DRAM Cell Array with a Folded Bitline
- FIG. 3 is a layout diagram of an open bitline DRAM in accordance with the second embodiment of the present invention, wherein the cross-sectional view of the cutting line I-I is as showed in FIG. 1.
- The
deep trench capacitors 102 substantially corresponding to theadjacent bitlines deep trench capacitor 102 corresponding to thebitline 116 b is opposite to thecommon drain 104 d corresponding to the bitline 116 a. Under the above-mentioned layout, the isolation between thedeep trench capacitor 102 corresponding to the bitline 116 a and thedeep trench capacitor 102 corresponding to thebitline 116 b are enhanced. Moreover, thewordlines - Third Embodiment: a Folder Bitline DRAM Cell Array
- FIGS. 4 and 5 are cross-sectional diagrams of a DRAM with a vertical transistor and a deep trench capacitor. FIG. 6 is a layout diagram of a folder bitline DRAM in accordance with the third embodiment of the present invention, wherein the cross-sectional view of the cutting line IV-IV is shown in FIG. 4, and the cross-sectional view of the cutting line V-V is shown in FIG. 5.
- The structures of a
deep trench capacitor 402 and avertical transistor 404 are the same as the first and second embodiments substantially. Thedeep trench capacitor 402 comprises anupper electrode 402 a, an insulatingfilm 402 b, and astorage electrode 402 c. Avertical transistor 404 comprising agate 404 a, agate insulating layer 404 b, asource 404 c and acommon drain 404 d is disposed over eachdeep trench capacitor 402. The gate-insulatinglayer 404 b is disposed on a sidewall of the lower portion of thegate 404 a. A vertical region between thesource 404 c and thecommon drain 404 d is achannel region 409. - An insulating
layer 408 and an ion-dopedlayer 406 are disposed between thegate 404 a and theupper electrode 402 a of thecapacitor 402. Thesource 404 c is disposed on the sidewall of the ion-dopedlayer 406. Ashallow trench isolation 410 is disposed at least on another sidewall of the ion dopedlayer 406. The insulatinglayer 408 is disposed between thegate 404 a and the ion dopedlayer 406 so as to isolate thegate 404 a and the ion dopedlayer 406 with each other. - In this embodiment, each
active region 412, such as corresponding to the bitline 416 a, comprises twodeep trench capacitors 402, twowordlines deep trench capacitors 402, and two passingwordlines wordlines wordlines active region 412 below the bitline 416 a are functioned asgates 404 a of thetransistors 404. Thedeep trench capacitors 402 are under thegates 404 a. The region outside theactive region 412 is theshallow trench isolation 410. - Furthermore,
contact windows 414 are disposed between thegates 404 a and the passing wordlines 418 b and 418 c and connected with thebitline 416. Thebitline 416 is substantially parallel with theactive region 412 and perpendicular with thewordlines - Fourth Embodiment: a Folder Bitline DRAM Cell Array with Borderless Bitline Contact Window
- FIG. 8 is a layout diagram of a folder bitline DRAM with a borderless bitline contact window in accordance with the fourth embodiment of the present invention, and the cross-sectional view of the cutting line VII-VII is shown in FIG. 7.
- The
deep trench capacitors 702 arranged in rows and columns are formed in thesubstrate 700. Thedeep trench capacitors 702 belonging to different rows are arranged with a shift. Each of thedeep trench capacitors 702 comprises anupper electrode 702 a, an insulatingfilm 702 b and astorage electrode 702 c. Avertical transistor 704 comprising agate 704 a, agate insulating layer 704 b, asource 704 c and acommon drain 704 d is disposed over eachdeep trench capacitor 702. The gate-insulatinglayer 704 b is disposed on a sidewall of the lower portion of thegate 704 a. A vertical region between thesource 704 c and thecommon drain 704 d is achannel region 709. - An insulating layer708 and an ion-doped
layer 706 are disposed between thegate 704 a and theupper electrode 702 a of thecapacitor 702. Thesource 704 c is disposed on the sidewall of the ion-dopedlayer 706. Ashallow trench isolation 710 is disposed on at least one other sidewall of the ion dopedlayer 706. The insulating layer 708 is disposed between thegate 704 a and the ion dopedlayer 706, so as to isolate thegate 704 a and the ion dopedlayer 706 with each other. - The
gate 704 a and the passing wordline are disposed over eachdeep trench capacitor 702. A part of theshallow trench isolation 710 is expanded to cover a part of thedeep trench capacitor 702, and the passing wordline is disposed on the part of theshallow trench isolation 710. - In this embodiment, each
active region 712, such as corresponding to thebitline 716 b and thewordlines 718 a″ and 718 b′, comprises twodeep trench capacitor 702, twowordlines 718 a″ and 718 b′ corresponding to the twodeep trench capacitors 702, and acommon drain 704 d between thewordlines 718 a″ and 718 b′. Two passingwordlines 718 a′ and 718 b″ are disposed outside the twowordlines 718 a″ and 718 b′. Thewordlines 718 a″ and 718 b′ corresponding to theactive region 712 below thebitline 716 b are functioned asgates 704 a of thetransistors 704. The region outside theactive region 712 is ashallow trench isolation 710. - Furthermore, the
bitlines common drain 704 d throughcontact windows 714. Thebitlines 716 are perpendicular to the wordlines (or passing wordlines) 718 a′, 718 a″, 718 b′, 718 b″, 718 c′, 718 c″, 718 d′ and 718 d″. Because the surface of the wordlines (or passing wordlines) 718 a′, 718 a″, 718 b′, 718 b″, 718 c′, 718 c′, 718 d′ and 718 d″ are covered by the insulatinglayer 720, thecontact window 714 cannot meet with thecommon drain 704 d, even if misalignment happens in the photolithography process. Therefore, no short circuit happens. - Finally, while the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (6)
1. A DRAM cell with a vertical transistor and a deep trench capacitor, comprising:
a substrate;
a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode desposed in the substrate;
a gate of a vertical transistor disposed over the deep trench capacitor;
an ion doped layer disposed between the gate and the upper electrode of the capacitor;
an insulating layer disposed between the gate and the ion doped layer;
a gate insulating layer of the vertical transistor disposed on a sidewall of the gate;
a channel region located beside the gate insulating layer in the substrate;
a source disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and
a common drain disposed on the other side of the vertical channel region.
2. The DRAM cell with a vertical transistor and a deep trench capacitor of claim 1 , further comprising a shallow trench isolation at least disposed on one other sidewall of the ion doped layer.
3. An open bitline DRAM with vertical transistors and deep trench capacitors, comprising:
a substrate;
a plurality of deep trench capacitors arranged with matrix in the substrate;
a plurality of wordlines paralleled with each other and disposed on the deep trench capacitors, wherein the wordlines substantially corresponding to the deep trench capacitors are functioned as gates, a lower portion of each gate disposed in the substrate;
an insulating layer disposed between each gate and each deep trench capacitor;
an ion doped layer disposed between each insulating layer and each deep trench capacitor;
a source disposed on a sidewall of each ion doped layer in the substrate;
a gate insulating layer disposed on a lower sidewall of each gate, wherein the source is located on one side of the gate insulating layer;
a common drain disposed between each two adjacent wordlines in the substrate, wherein the common drain is located on the other side of the gate insulating layer;
an active region disposed between each common drain and two lower gates beside the common drain;
a shallow trench isolation disposed outside the active region; and
a plurality of bitlines paralleled with each other, disposed on the common drains, and connected with the common drains.
4. An open bitline DRAM with vertical transistors and deep trench capacitors, comprising:
a substrate;
a plurality of deep trench capacitors located in the substrate, wherein the deep trench capacitors belonging to different rows are arranged with a shift;
a plurality of zigzag wordlines paralleled with each other and disposed on the deep trench capacitors, wherein the wordlines substantially corresponding to the deep trench capacitors are functioned as gates, a lower portion of each gate disposed in the substrate;
an insulating layer disposed between each gate and each deep trench capacitor;
an ion doped layer disposed between each insulating layer and each deep trench capacitor;
a source disposed on a sidewall of each ion doped layer in the substrate;
a gate insulating layer disposed on a lower sidewall of each gate, wherein the source is located on one side of the gate insulating layer;
a common drain disposed between each two adjacent wordlines in the substrate, wherein the common drain is located on the other side of the gate insulating layer;
an active region disposed between each common drain and two lower gates beside the common drain;
a shallow trench isolation disposed outside the active region; and
a plurality of bitlines paralleling with each other disposed on the common drains and connected with the common drains.
5. A folder bitline DRAM with vertical transistors and deep trench capacitors, comprising:
a substrate;
a plurality of wordlines disposed on the substrate;
a plurality of bitlines disposed over the wordlines and perpendicular to the wordlines;
each active region corresponding to the bitlines and comprising four adjacent wordlines, wherein the two outside wordlines are functioned as gates, the two inside wordlines are passing wordlines, wherein each two adjacent active regions corresponding to two adjacent bitlines are arranged with a shift;
a common drain disposed between the two gates belonging to the two outside wordlines;
a deep trench capacitor disposed below each gate;
an insulating layer disposed between each gate and each deep trench capacitor;
a contact window disposed between each passing wordline and each gate to connect the common drain and bitline;
an ion doped layer disposed between each insulating layer and each deep trench capacitor;
a source disposed on a sidewall of each ion doped layer in the substrate;
a gate insulating layer disposed on a sidewall of a lower portion of each gate, wherein the source is located on one side of the gate insulating layer; and
a shallow trench isolation disposed outside the active region.
6. A folder bitline DRAM with vertical transistors, deep trench capacitors and borderless bitline contact windows, comprising:
a substrate;
a plurality of wordlines disposed on the substrate;
a plurality of deep trench capacitors disposed in the substrate, wherein the deep trench capacitors belonging to different rows are arranged with a shift, and two wordlines leap over each deep trench capacitor;
a plurality of bitlines disposed over the wordlines and perpendicular to the wordlines;
each active region corresponding to the bitlines and comprising two wordlines which leap different deep trench capacitors and functioned as gates, wherein each two adjacent active regions corresponding to two adjacent bitlines are arranged with a shift;
an insulating layer disposed between each gate and each deep trench capacitor;
a common drain disposed between the two gates belonging to the two wordlines which leap over different deep trench capacitors;
a deep trench capacitor disposed below each gate;
a contact window connected to the common drain and bitline;
an ion doped layer disposed between each insulating layer and each deep trench capacitor;
a source disposed on a sidewall of each ion doped layer in the substrate;
a gate insulating layer disposed on a sidewall of a portion of each gate, wherein the source is located on one side of the gate insulating layer; and
a shallow trench isolation disposed outside the active region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/453,502 US6781181B2 (en) | 2000-07-13 | 2003-06-04 | Layout of a folded bitline DRAM with a borderless bitline |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW89113956 | 2000-07-13 | ||
TW089113956A TW449885B (en) | 2000-07-13 | 2000-07-13 | Arrangement of DRAM cells with vertical transistors and deep trench capacitors |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/453,502 Division US6781181B2 (en) | 2000-07-13 | 2003-06-04 | Layout of a folded bitline DRAM with a borderless bitline |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020005537A1 true US20020005537A1 (en) | 2002-01-17 |
Family
ID=21660381
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/826,014 Abandoned US20020005537A1 (en) | 2000-07-13 | 2001-04-05 | DRAM with vertical transistors and deep trench capacitors |
US10/453,502 Expired - Lifetime US6781181B2 (en) | 2000-07-13 | 2003-06-04 | Layout of a folded bitline DRAM with a borderless bitline |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/453,502 Expired - Lifetime US6781181B2 (en) | 2000-07-13 | 2003-06-04 | Layout of a folded bitline DRAM with a borderless bitline |
Country Status (2)
Country | Link |
---|---|
US (2) | US20020005537A1 (en) |
TW (1) | TW449885B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100416837C (en) * | 2004-09-21 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Memory cell and mfg. method |
US20090024771A1 (en) * | 2006-03-30 | 2009-01-22 | Fujitsu Limited | Information processing apparatus, managing method, computer-readable recoding medium storing managing program therein, and electronic apparatus |
US20130264635A1 (en) * | 2005-12-28 | 2013-10-10 | SK Hynix Inc. | Semiconductor device having vertical-type channel |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI223442B (en) * | 2003-09-02 | 2004-11-01 | Nanya Technology Corp | DRAM cell array and its manufacturing method |
DE102004052141B4 (en) * | 2004-10-22 | 2007-10-18 | Infineon Technologies Ag | Method for producing a semiconductor structure |
US20070221976A1 (en) * | 2006-03-23 | 2007-09-27 | Richard Lee | Trench capacitor and fabrication method thereof |
JP5758729B2 (en) * | 2011-07-27 | 2015-08-05 | ローム株式会社 | Semiconductor device |
KR20140017272A (en) * | 2012-07-31 | 2014-02-11 | 에스케이하이닉스 주식회사 | Semiconductor device and method of fabricating the same |
KR102171258B1 (en) | 2014-05-21 | 2020-10-28 | 삼성전자 주식회사 | Semiconductor device |
US10032777B1 (en) | 2017-06-05 | 2018-07-24 | United Microelectronics Corp. | Array of dynamic random access memory cells |
CN111640744A (en) * | 2019-07-22 | 2020-09-08 | 福建省晋华集成电路有限公司 | Memory device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61110459A (en) | 1984-11-02 | 1986-05-28 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory |
US5831301A (en) * | 1998-01-28 | 1998-11-03 | International Business Machines Corp. | Trench storage dram cell including a step transfer device |
US6034879A (en) * | 1998-02-19 | 2000-03-07 | University Of Pittsburgh | Twisted line techniques for multi-gigabit dynamic random access memories |
US6339239B1 (en) * | 2000-06-23 | 2002-01-15 | International Business Machines Corporation | DRAM cell layout for node capacitance enhancement |
-
2000
- 2000-07-13 TW TW089113956A patent/TW449885B/en not_active IP Right Cessation
-
2001
- 2001-04-05 US US09/826,014 patent/US20020005537A1/en not_active Abandoned
-
2003
- 2003-06-04 US US10/453,502 patent/US6781181B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100416837C (en) * | 2004-09-21 | 2008-09-03 | 台湾积体电路制造股份有限公司 | Memory cell and mfg. method |
US20130264635A1 (en) * | 2005-12-28 | 2013-10-10 | SK Hynix Inc. | Semiconductor device having vertical-type channel |
US8981467B2 (en) * | 2005-12-28 | 2015-03-17 | SK Hynix Inc. | Semiconductor device having vertical-type channel |
US20090024771A1 (en) * | 2006-03-30 | 2009-01-22 | Fujitsu Limited | Information processing apparatus, managing method, computer-readable recoding medium storing managing program therein, and electronic apparatus |
Also Published As
Publication number | Publication date |
---|---|
US6781181B2 (en) | 2004-08-24 |
US20030201481A1 (en) | 2003-10-30 |
TW449885B (en) | 2001-08-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4559728B2 (en) | Semiconductor memory device | |
US7034351B2 (en) | Memory cell and method for forming the same | |
US7297996B2 (en) | Semiconductor memory device for storing data in memory cells as complementary information | |
US7042047B2 (en) | Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same | |
US20140239384A1 (en) | Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system | |
US5936271A (en) | Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers | |
JP2009088134A (en) | Semiconductor device, method of manufacturing the same, and data processing system | |
JP2002093924A (en) | Semiconductor storage device | |
US6396096B1 (en) | Design layout for a dense memory cell structure | |
US6291335B1 (en) | Locally folded split level bitline wiring | |
US6781181B2 (en) | Layout of a folded bitline DRAM with a borderless bitline | |
US20020135022A1 (en) | A semiconductor device with a well wherein a scaling down of the layout is achieved | |
JP3397499B2 (en) | Semiconductor storage device | |
US8508982B2 (en) | Semiconductor device | |
US6597599B2 (en) | Semiconductor memory | |
US6362501B1 (en) | DRAM cell array not requiring a device isolation layer between cells | |
US6317358B1 (en) | Efficient dual port DRAM cell using SOI technology | |
US7208789B2 (en) | DRAM cell structure with buried surrounding capacitor and process for manufacturing the same | |
US6916671B2 (en) | Gate oxide measurement apparatus | |
US6875653B2 (en) | DRAM cell structure with buried surrounding capacitor and process for manufacturing the same | |
US6590237B2 (en) | Layout structure for dynamic random access memory | |
CN117715410A (en) | Dynamic random access memory structure | |
JPH06216337A (en) | Semiconductor storage device | |
JPH11251541A (en) | Dynamic semiconductor storage device | |
JP2001168292A (en) | Ferroelectric memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NANYA TECHNOLOGY CORPORATION, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HEO, KUEN-CHY;LIN, JENG-PING;REEL/FRAME:011687/0536;SIGNING DATES FROM 20001222 TO 20001226 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |