JPH03225954A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the disconnection from a word line by only etching the periphery of a recessed part a little by a method wherein a gate electrode is formed on sidewalls of the recessed part and in the periphery at an opening part of the recessed part. CONSTITUTION:A gate insulating film 28 is formed on the surface of a recessed part 24 and on the surface of a semiconductor substrate 21 surrounded by a LOCOS film 22. A gate electrode 29 is formed, via the gate insulating film 28, on sidewalls of the recessed part 24, in the periphery of the bottom adjacent to the sidewalls and in the periphery of an opening part of the recessed part 24. The gate electrode 29 is formed of a polysilicon film, and phosphorus is diffused to it. About the half of an element region 23 surrounded by the LOCOS film 22 is covered with the gate electrode 29; the electrode is extended in the upward and downward directions and forms a structure united to a word line. As a method to form the gate electrode 29, the recessed part 24 is first filled completely with polysilicon, and an etching-back operation is executed. In succession, the polysilicon is laminated again in the horizontal direction. After that, the outside of a region to be used as a guard is removed by an etching operation; then, the recessed part in the center is formed by an etching operation. Consequently, the electrode can be formed without a fear that it is disconnected from the word line.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to stacked capacitor DRAMs.

(B) Prior Art Conventionally, stacked capacitor DRAMs have been required to have smaller cell sizes as integration has improved.

Various structures have been considered to achieve this reduction. For example, Japanese Patent Application Laid-Open No. 1-119055 is one of these various structures, in which the capacitor part is not formed horizontally,
It is formed in a recess formed in a semiconductor substrate.

In addition, the gate electrode is formed on the side wall to reduce the cell size and the level difference of the gate electrode.

The specific configuration is as shown in FIG. 3, where (1) is a semiconductor substrate made of Si, for example, (2) is an element isolation insulating film made of, for example, 5 IOP, and (3) is a concave portion embodied as a trench. , (4) is a substrate diffusion region as a source/drain electrode, (5) is a gate insulating film made of, for example, Sin, and (6) is a gate electrode made of, for example, poly-Si.
(7) is an insulating film made of, for example, a Si sail; (8) is a polycrystalline semiconductor layer made of, for example, doped poly-Si as a capacitor lower electrode; (9) is a capacitive part made of, for example, Sin as a dielectric film; (10) is a polycrystalline semiconductor layer made of doped polySi, for example, as a capacitor upper electrode, and (11) is, for example, SiO doped with P.
, (PSG), <12) is a contact region, and (13) is, for example, an AN as a bit line.
(14) is a MISI transistor forming a switching transistor.

With the above configuration, the transistor (14) and the capacitor are buried in the recess (3), and large scale integration can be achieved.

(c) Problems to be Solved by the Invention However, since the gate electrode (6) is completely buried in the recess, there is a problem in that this method of contacting the word line becomes extremely difficult. In other words, the gate electrode (6
) becomes thinner due to etching, and depending on the control conditions this word line may break.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and the gate electrode (29
) is provided on the side wall of the recess (24) and around the side hole of the recess (24).

(E) Function Since the gate electrode (29) is provided horizontally around the side hole of the recess (24), that is, on the semiconductor substrate (21), a thick layer of polysilicon is formed around the recess (24). has been done. That is, first, the entire concave portion (24) is filled with polysilicon and then etched back. Then, polysilicon is formed again in the horizontal direction. Thereafter, the outside of the region that will become the collar is removed by etching, and then the central recess is etched. Therefore, the disconnection of the word line can be prevented by only slightly etching the area around the recess.

Kube) Example The present invention will be explained in detail below.

First, as shown in Figure 1, there is a P-type semiconductor substrate (21),
On this semiconductor substrate (21), there is an L for the purpose of element isolation.
An OCOS film (22) is formed.

This LOCOS film (22) surrounds an element region (23), as shown by the short diagonal line in FIG. It is formed. In FIG. 2, it is indicated by a broken line.

In addition, the semiconductor substrate (21) corresponding to the bottom surface (25) of this recess <24), and the semiconductor substrate (21) from the opening of this recess (24) to the LOCOS film (22),
N" type diffusion regions (26) and (27) are formed.

Here, the first region (26) becomes a source region or a drain region, and the second region (27) becomes a drain region or a source region. Also, the impurity is arsenic, for example 60
KeV, 5 x 1016 cm-'' ion implantation conditions. However, in order to adjust the threshold voltage Vt, boron ions are implanted at 150 KeV.

It is injected under the condition of "IX 10 IQcm-".

Next, the surface of the recess (24) and the LOCO8 film (
There is a gate insulating film (28) formed on the surface of the semiconductor substrate 21) surrounded by 22). This gate insulating film (
28) is achieved for example by thermal oxidation at a thickness of approximately 170 mm.

Further, the concave portion (28) is
4), a gate electrode (29) formed on the semiconductor substrate (21) around the bottom surface adjacent to the side wall, and around the side hole of the recess (24).

This gate electrode (29) is made of a polysilicon film,
Phosphorus is diffused. Furthermore, as is clear from the dashed line in FIG. 2, the gate electrode (29) covers about half of the device region (23) surrounded by the LO=7 CO8 film 22) and extends in the vertical direction. , has an integrated structure with the word line.

Here, the method for forming this gate electrode (29) is to first bury the recess (24) entirely with polysilicon and etch back. Next, polysilicon is layered again in the horizontal direction. Then, by etching, the outside of the area that will become the flange is etched. remove the
Next, a central recess is etched. Therefore, word lines can be formed without worrying about disconnection.

Subsequently, a thermal oxide film (30) is formed to a thickness of approximately 2,000 nm so as to completely cover the gate electrode (29). This thermal oxide film (30) is etched by, for example, the RIE method, and in FIG. 1, it is etched so that it terminates near the periphery of the LOCO8 film (22> on the left) and at the - part of the diffusion region (27> on the right). has been done.

Further, one electrode (31) is sequentially placed on this thermal oxide film <30>.
), a dielectric film (32), and a second electrode (33>) are laminated.

The first electrode <31) is made of polysilicon and has a thickness of 8- It is formed by 1,000 people and becomes the lower layer electrode of the capacitor section.

Further, this first electrode (31) is in contact with a diffusion region (26) which becomes a first region exposed in the recess (24).

Further, the dielectric film (32) is substantially composed of about 120 Si, N, and films, but some Si and N films are formed on this 5isN4 film by an oxidation process.

Further, the second electrode (33) is made of about 3000 polysilicon. The second electrode is connected to a region (a rectangular region (3
5)) It is formed on the entire surface except for.

Furthermore, an insulating film (36) for planarization, such as a BPSG film, is formed to a thickness of about 8000 nm over the entire surface of the semiconductor substrate (21).

Finally, a contact hole 37) is formed to contact the second region (27), and a third electrode (34) is formed through this hole (37).

This third electrode (34) is made of a laminate of approximately 2,500-thick Bosilicon film and approximately 2,500-thick WSiz film.

The feature of the present invention lies in the gate electrode (29). This gate electrode (29) is provided in a flange shape on all sides on the semiconductor substrate (21).
9) and the word line This connection is very simple. In other words, since polysilicon is formed thickly around the side hole of the recess, the first region (26) can be etched without considering etching accuracy.
Even if a groove is cut or notched to expose the word line, this disconnection will not occur.

(G) Effects of the Invention As is clear from the above explanation, the gate electrode is formed in the shape of a flange up to the side wall of the recess and the periphery of the side hole of the recess. It can be formed without considering etching accuracy.

Moreover, since it is formed in a brim shape around the side hole, the wiring resistance of the word line can be lowered.

Therefore, memory cells with good characteristics and high yield can be highly integrated.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor memory device of the present invention, FIG. 2 is a plan view of a semiconductor memory device of the present invention, and FIG. 3 is a sectional view of a conventional semiconductor memory device.

Claims (3)

[Claims] (1) An isolation region formed on a semiconductor substrate, a recess formed in a part of the element region surrounded by this isolation region, and a first region that becomes a source or drain region formed on the bottom of this recess. a second region forming a drain region or a source region formed around the opening of the recess; a gate electrode formed on the sidewall of the recess and around the opening of the recess with an insulating film interposed therebetween; formed on the gate electrode with an insulating film interposed therebetween;
a first electrode of the capacitive part in contact with the region; a second electrode of the capacitive part formed via a dielectric film formed on the first electrode; and a second electrode in contact with a part of the second region. A semiconductor memory device characterized by comprising three electrodes. (2) the gate electrode is formed integrally with a word line;
2. The semiconductor memory device according to claim 1, wherein the third electrode is a bit line. (3) A LOCOS film formed on a semiconductor substrate, a recess formed in a part of the element region surrounded by this LOCOS film, and a source region or drain formed on the semiconductor substrate corresponding to the bottom of this recess. a second region formed in the semiconductor substrate corresponding to the periphery of the side hole of the recess and serving as a drain or source region; a side wall of the recess and a periphery of the bottom adjacent to the side wall; and a gate electrode formed on the semiconductor substrate around the opening of the recess via an insulating film and integrally formed with the word line formed on the semiconductor substrate, and a gate electrode formed on the gate electrode. a first electrode of a capacitive part formed via an insulating film and in contact with the first region from the bottom surface of the recess; a dielectric film of the capacitive part formed on the first electrode; and the dielectric film. a second electrode of the capacitor portion formed on the semiconductor substrate and extending onto the semiconductor substrate; an insulating film for planarization formed on the entire surface of the semiconductor substrate; A semiconductor memory device comprising: a third electrode serving as a bit line in contact with the second region.