JPS63257263A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent a punchthrough between adjacent memory cells by a method wherein a charge accumulation region is formed at the inside of two grooves inside a memory cell and a device isolation region to isolate the adjacent memory cells is formed at the inside of both grooves at a boundary part of the adjacent memory cells. CONSTITUTION:First grooves 21 and second grooves 22 are formed on a substrate for purposes of charge accumulation and device isolation. Thick selective oxide films 261 are formed in the center of the bottom of the grooves 22 and at side parts interlinked with the center, and isolate adjacent memory cells. On the other hand, thick selective oxide films 262 are formed on the bottom and at the side parts of the grooves 21 corresponding to a boundary part between the individual memory cells in order to isolate the memory cells which are adjacent in the longitudinal direction. By this setup, the grooves 21 and 22 which pass through regions where a punchthrough phenomenon is caused between the adjacent memory cells are formed; the selective oxide films 261, 262 are formed on the bottom and on the side parts of the individual grooves corresponding to said regions; accordingly, the punchthrough phenomenon is not caused in said regions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device including a MOS (Metal Oxide S) having a Mizohori memory cell.
em1conductor) Dynamic RAM
(Random AccessMemory).

[Conventional technology]

Conventionally, in this type of semiconductor memory device, for example, in 1984,
International Electron of the year
Device Me-eting (IEDM '8
4) Trench type memory cell (trench cell) of MOS dynamic RAM as shown in lecture number 9.6
It has been known.

FIG. 2 is a cross-sectional view showing the structure of such a conventional trench cell, and FIG. 3 is a structural diagram of a semiconductor memory device in which the trench cells are arranged in an array for a folded bit line. , FIG. 3 (fat) is a plan view, and FIG.

In these figures, 1 is a p-type silicon substrate. A large number of trench cells are formed in this p-type silicon substrate 1, of which the A region is the region where the first memory cell is formed, and the BjiJt region is the region where the second memory cell adjacent to the first memory cell is formed. The area where cells are formed is extracted and shown.

Since the configuration of each memory cell is the same, here A j
The configuration of a memory cell formed in the Jl area will be described as a representative example.

A of p-type silicon substrate 1! There is a groove 2 in the area. Along the inner surface of the groove 2I, there is a groove consisting of an n'' region 3 in which storage information (charge) is stored, a capacitor insulating film 4, and a cell plate electrode 5 made of a first polysilicon layer. type capacitor is formed.Ql is a switching transistor region for accessing the above-mentioned trench type capacitor, and includes an n' region (drain) 6., an n'' region source) 79. Channel part 8. is composed of
n + region (drain)6. is the n' head area 3 of the trench type capacitor. are formed continuously.

Adjacent memory cells formed in region B have a similar configuration, and corresponding parts are indicated by the same reference numerals (subscript 2).

Between adjacent memory cells is a trench 2. ．． 2! They are separated by a thick selective oxide film 9 formed between them. In addition, the channel portions 81 and 82 of each memory cell are connected by a word &'
7I and 7t are connected by a focus line 11.

In the trench cell described above, a negative potential (approximately -3V) is normally set on the p-type silicon substrate 1, and storage information rQ, , r1 to be written is stored in the n"fii region 35.3□, which serves as a charge storage node. A potential of approximately 5V or Ov is applied corresponding to .

In this way, the conventional semiconductor memory device can store charge within a small area by providing a charge storage capacitor (a space between the n'' region 3. and the cell plate electrode 51) in the groove formed in the semiconductor substrate. By realizing a large charge storage capacity, semiconductor memory devices are highly integrated, and furthermore, soft error resistance against alpha rays and other noise resistance is improved.

[Problem that the invention seeks to solve]

However, in conventional semiconductor memory devices, the nl & Ji region 33.3, which serves as a charge storage node for higher integration,
If the distance t (see FIG. 2) is too small, for example, OV in n" region 3., OV in n" region 3. 5v
The depletion layer 12. formed when written. ．． 12□
This type of punch-through phenomenon between adjacent memory cells causes a so-called bunch-through phenomenon in which the adjacent memory cells are connected, resulting in leakage between adjacent memory cells and destruction of stored information. This has been a major obstacle to higher integration of devices.

Therefore, in order to avoid such a problem, it is conceivable to form a highly concentrated p-well layer in the p-type silicon substrate 1 and create a trench cell therein to suppress the spread of the depletion layer. The use of such a highly doped p-well layer causes a different problem in that the breakdown voltage between the memory cell and the substrate decreases.

It is also possible to use an epitaxial substrate as the semiconductor substrate, but since the epitaxial substrate is inexpensive, this is inconvenient as it goes against the cost reduction required for this type of semiconductor memory device.

This invention was made to solve these problems, and it is possible to suppress the punch-through phenomenon between adjacent memory cells without increasing the concentration of the substrate (well) or using an epitaxial substrate. It is an object of the present invention to provide a semiconductor memory device that can achieve high a#A.

[Means for solving problems]

A semiconductor memory device according to the present invention includes a first trench and a second trench connected to an adjacent memory cell in a MOS dynamic memory cell, and a first trench and a second trench in the memory cell. A charge storage region of the memory cell is formed on the inner surface of the memory cell, and an element isolation head for separating the adjacent memory cells is formed on the inner surface of the first trench and the second trench at the boundary between the adjacent memory cells. were formed respectively.

[Effect]

In this invention, the element isolation region formed on the inner surface of the first groove and the second groove at the boundary between adjacent memory cells prevents punch-through occurring between adjacent memory cells. A sufficiently large charge storage capacity is ensured by the charge storage regions formed on the inner surfaces of the first trench and the second trench within the memory cell.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory/equipment device according to an embodiment of the present invention, in which memory cells according to the embodiment are arranged in 7 lays for folded bit lines. In particular, Figure 1 t8) is a plan view,
Figure [bl is a sectional view taken along line I-1 in the figure fat.

In this figure, the same reference numerals as those in the conventional example shown in FIGS. 2 and 3 indicate the same parts, so a description thereof will be omitted here.

In FIG. 1, 21 and 22 are a first trench and a second trench formed in the p-type silicon substrate 1 for charge storage and element isolation.

The first groove portion 21 is formed so as to penetrate through a plurality of memory cells arranged in the vertical direction in FIG. 1 fal. On the other hand, the second groove portion 22 is formed to connect adjacent memory cells arranged in the horizontal direction in FIG. 1 [al].

As shown in FIG. 1 (bl), the first groove portion 21 in the area where each memory cell is formed, for example, the area Ag shown in the same figure.
A continuous n' region 23, a capacitor insulation v24, and a cell plate electrode 25 made of a first polysilicon layer are formed along the inner surface of the second groove 22,
These constitute the charge storage region of one memory cell.

One end of the n'' head area 23 is connected to the n of the switching transistor as in the conventional example explained in FIGS.
It is connected to the (area drain) 61. And the second
A thick selective oxide film 26. are formed to isolate adjacent memory cells. On the other hand, in order to isolate memory cells adjacent in the vertical direction in FIG. There is. The element isolation region in which these selective oxide films 261.26z are formed corresponds to the hatched region in FIG. 1+I11.

In the embodiment described above, the first groove 21 and the second groove 22 are formed so as to pass through the region where the punch-through phenomenon occurs between adjacent memory cells.
A selective oxide film 26. , 22 is formed on the bottom and side surfaces of the trenches. ．． 26□
are formed respectively, so no punch-through phenomenon occurs in the above-mentioned regions.

Further, since the first groove portion 21 and the second groove portion 22 have independent groove structures that do not communicate with each other, the charge storage area becomes large and a sufficiently large charge storage capacity can be secured.

Moreover, if the first groove part 21 and the second groove part 22 shown in FIG. In the example, since both the grooves 21 and 22 are made independent, the distance related to the punch-through phenomenon is as follows.Obviously, since the distance is longer than the distance L2, both the grooves 21 and 22 are made to be independent. This is also advantageous in terms of preventing punch-through phenomenon.

Note that in the above embodiment, a fold bit line (fold
Although the explanation has been given by taking as an example the case where the memory cell according to the present invention is used for an open bit line (ed bit 1ine), the present invention is not limited to this.
bit 1ine), the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, a first trench and a second trench connected to an adjacent memory cell are formed in a MOS Guinaminok type memory cell, and charges are accumulated on the inner surfaces of both trenches within the memory cell. At the boundary between adjacent memory cells, an element isolation region is formed on the inner surface of both trenches to separate adjacent memory cells. Punch-through can be prevented, and the charge storage capacity can be made sufficiently large by the charge storage regions formed in the first trench and the second trench in one memory cell, resulting in high density and high reliability. Accordingly, a semiconductor memory device with high performance can be obtained.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of a semiconductor memory device in which memory cells according to an embodiment of the present invention are arranged in an array for folded bit lines, FIG. 2 is a sectional view showing the structure of a conventional memory cell, and FIG. FIG. 2 is a structural diagram of a semiconductor memory device in which the conventional memory cells are arranged in an array for folded bit lines. In the figure, 1 is a p-type silicon substrate, lO is a word line,
11 is a bit line, 21 is a first trench, 22 is a second trench, 23 is an n' region 24 is a capacitor insulating film, 25 is a cell plate electrode, and 261°26□ is a selective oxide film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a semiconductor memory device including a MOS dynamic memory cell in which the inner surface of a groove formed in a semiconductor substrate is used as a charge storage region, the memory cell has a first groove connected to an adjacent memory cell and a first groove connected to an adjacent memory cell. In the memory cell, a charge storage region of the memory cell is formed on the inner surface of the first trench and the second trench, and at a boundary between the adjacent memory cells, a first trench is formed. A semiconductor memory device characterized in that element isolation regions for separating the adjacent memory cells are formed on the inner surfaces of the trench portion and the second trench portion.