JPS63172455A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress punch-through between trench memory cells and to implement high integration density, by providing an isolating groove in an isolating region between grooves of neighboring trench memory cells, and forming an insulating film on the inner surface of the isolating groove. CONSTITUTION:A plurality of memory cells 2 and an isolating oxide film 3 are formed on the surface of a P-type semiconductor substrate 1. Grooves parts 8 are formed in the surface of the semiconductor substrate 1 corresponding to charge storing regions 4. N<+> layers 41 are formed on the bottom surface parts and the side surface parts of the groove parts 8. A cell plate 42 comprising polysilicon is arranged on the upper part thereof. An isolating groove part 80 is formed between the groove part 8 of the memory cell 2 and the groove parts 8 of the neighboring memory cell 2. The groove parts 8 and 8 in the neighboring memory cells 2 and 2 are linked. The groove parts 8 and 80 are formed in the surface of the semiconductor substrate in a network pattern. The isolating oxide film 3a is formed on the bottom surface part and the side surface part of the isolating groove part 80. The N<+> layer 41 in the groove part 8 of the memory cell 2 is completely isolated from the N<+> layer 41 in the neighboring memory cell 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device comprising trench memory cells.

[Prior Art] FIG. 2A shows an M memory cell comprising a conventional trench memory cell (grooved memory cell) arranged for a folded bit line system.
FIG. 2B is a plan view of the OS dynamic RAM, and FIG. 2B is a sectional view taken along the line X-Y in FIG. 2A.

This trench memory cell is, for example, a 1984 In
ternatlonal Electron Devi
ce Meeting (IEDM'84), lecture number 9.6.

In the figure, a plurality of memory cells 2 are formed on the surface of a p-type semiconductor substrate 1, and an isolation oxide film 3 is formed between each memory cell 2. Each memory cell 2 includes a charge storage region 4 where charges are stored, a transfer gate region 5,
and an n-type impurity diffusion region δ connected to the bit line BL
It consists of The charge storage region 4 forms a groove 8 (a region surrounded by a thick solid line in FIG. 2A) on the surface of the semiconductor substrate 1, and the bottom surface of the groove 8 and
・An n+1 layer 1 is formed on the side surface, and this n middle layer 4 is formed.
A cell plate 42 made of polysilicon is disposed on top of the n-layer 41, and charges are stored in the n-middle layer 41.

The transfer gate region 5 has a word line WL made of polysilicon arranged on a channel region 51 between the impurity diffusion region 6 and the n-type intermediate layer 41 in the trench portion 8,
When a predetermined potential is applied to the word line WL, an inversion layer is formed in the channel region 51, and information on the bit line BL is transferred to the charge storage region 4 via the channel region 51.

In this way, a charge storage capacitor (n1 layer 41
By providing a capacitance between the cell plate 42 and the cell plate 42, a large charge storage capacity can be obtained in a small area, and the degree of integration is increased. is realized.

[Problems to be Solved by the Invention] In the above-described conventional MOS dynamic RAM consisting of trench memory cells, the p-type semiconductor substrate 1 is normally set at a negative potential (approximately -3V), and the charge A potential of approximately 5V or approximately Ov is applied to the n+10 layer 1, which serves as a storage node, in accordance with the information of rlJ and rOJ.

FIG. 3 is an enlarged cross-sectional view of the trench portions of two adjacent memory cells shown in FIG. 2B.

In FIG. 3, for example, if the n+10 layer 1a in the trench 8a of one memory cell 2a becomes Ov and the n middle layer 41b in the trench 8b of the other memory cell 2b becomes 5V, then the n middle layer 41a and the n+ Depletion regions 9a and 9b are formed on the semiconductor substrate 1 side of the ten layer 1b.

Therefore, if the adjacent trenches 11a and 13b are formed close to each other, the depletion regions 9a and 9b will come into contact with each other, resulting in punch-through between the memory cells 2a and 2b.

Therefore, the distances a, b(
(See Figure 2A) could not be shortened, which was a major obstacle to higher integration.

In order to avoid this, methods have been proposed, such as forming a trench memory cell in the high concentration p-well to suppress the expansion of the depletion regions 9a and 9b, and using an epitaxial substrate. This method has disadvantages in that it lowers the breakdown voltage between the memory cell and the semiconductor substrate, and the epitaxial substrate is expensive.

This invention was made to solve the above-mentioned problems, and it is possible to suppress punch-through between trench memory cells and achieve high integration without increasing the impurity concentration of the semiconductor substrate or using an epitaxial substrate. The object of the present invention is to obtain a semiconductor memory device that enables.

[Means for Solving the Problems] A semiconductor memory device according to the present invention is provided by forming an isolation trench integrated with the trenches of adjacent trench memory cells in the isolation region between the trenches, and An insulating film is formed on the inner surface of the isolation groove, and charge storage regions formed in adjacent grooves are separated from each other by the insulating film.

[Operation] In the semiconductor memory device according to the present invention, an isolation trench connecting adjacent trenches is formed in the isolation region between the trenches of adjacent memory cells. The charge storage regions formed in adjacent trenches are separated from each other by an insulating film formed in the isolation trench. That is, the charge storage regions formed at the bottoms of adjacent trenches are separated by an insulating film formed at the bottom of the isolation trench that connects the trenches. Further, the charge storage regions formed on the side surfaces of adjacent trenches are separated by an insulating film formed on the side surface of the isolation trench that connects the trenches.

The charge storage regions formed on the bottoms of adjacent trenches are both on the same plane, and the charge storage regions formed on the bottoms of adjacent trenches are both on the same plane, so their charges The depletion regions formed on the semiconductor substrate side of the accumulation region are also on the same plane. Therefore, even if the distance between adjacent grooves is narrowed, punch-through will not occur.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view of a MOS dynamic RAM according to the present invention comprising a plurality of trench memory cells arranged for a folded bit line scheme, and FIG. 1B is a cross-sectional view taken along the line X--Y of FIG. 1A.

In the figure, a plurality of memory cells 2 are formed on the surface of a p-type semiconductor substrate 1, and an isolation oxide film 3 is formed between each memory cell 2. Each memory cell 2 includes a charge storage region 4 where charges are stored, a transfer gate region 5,
and an n-type impurity diffusion region 6 connected to the bit line BL.
It consists of The charge storage region 4 is formed by forming a groove 8 on the surface of the semiconductor substrate 1, forming an n+ layer 41 on the bottom and side surfaces of the groove 8, and further forming the n+ layer 41 on the bottom and side surfaces of the groove 8.
A cell plate 42 made of polysilicon is placed on top of the n+ layer 41, and charges are stored in the n+ layer 41. In the transfer gate region 5, a word line WL made of polysilicon is formed on a channel region 51 between an impurity diffusion region 6 and an n layer 41 in a groove portion 8. When a potential is applied, an inversion layer is formed in the channel region 51, and information on the bit line BL is transferred to the charge storage region 4 via the channel region 51.

An isolation groove 80 is formed between the groove 8 of each memory cell 2 and the groove 8 of the adjacent memory cell 2, and this isolation groove 80 allows the groove 8 of the adjacent memory cells 2, 2 to .8 are connected, and the area shown by the thick solid line in FIG.
Grooves 8° 80 are formed in the shape of a mesh on the surface.

An isolation oxide film 3a is formed on the bottom and side surfaces of the isolation trench 80.

The n+ layer 41 in the trench 8 of the memory cell 2 is protected by the insulating film 3a in the isolation trench 80 integrated with the trench 8.
It is completely separated from the n+ layer 41 in the trench 8 of the adjacent memory cell 2. That is, as shown in the mlB diagram,
n+ layer 41 formed on the bottom part of the adjacent groove part 8.8
, 41 are separated by an isolation oxide film 3a formed on the bottom of an isolation groove 80 connecting the grooves 8, 8. Similarly, the n+ layers 41.41 formed on the side surfaces of the adjacent grooves 8, 8 are
They are separated by the isolation oxide film 3a formed on the side surface of the isolation groove 80 that connects the two.

Therefore, the n+ layers 41 . jl are on the same plane, and the n1 layers 41.41 formed on the side surfaces of the adjacent trenches 8.8 are on the same plane, so that the n+ layers 41, 41 are formed on the semiconductor substrate 1 side. The depletion regions are also on the same plane. Therefore, the distance between adjacent grooves 8.8 is narrowed (
However, no punch-through will occur.

Further, since there is no need to provide a well with a high concentration or use an epitaxial substrate, the problem of a decrease in breakdown voltage is also avoided.

Therefore, the semiconductor memory device can be highly integrated.

Although the above embodiment shows a case in which memory cells are arranged for a folded bit line method, the present invention can also be applied to a semiconductor memory device using an oven bit line method, and the same method as in the above embodiment can be applied. be effective.

[Effects of the Invention] As described above, according to the present invention, isolation grooves integrated with the grooves of memory cells are also formed in the punch-through regions between the grooves of adjacent memory cells, and the inner surfaces of the adjacent grooves are formed. Since the formed charge storage regions are separated by an insulating film formed on the inner surface of the isolation groove, adjacent memories can be separated without increasing the impurity concentration of the substrate or using an epitaxial substrate. Punch-through between cells is prevented, and a semiconductor memory device that can be highly integrated and has high reliability can be obtained.

[Brief explanation of the drawing]

FIG. 1A is a plan view showing an embodiment of the present invention, FIG. 1B is a sectional view of the same embodiment, and FIG. 2A is a plan view showing a conventional semiconductor memory device. FIG. 2B is a sectional view of the semiconductor memory device of FIG. 2A, and FIG. 3 is an enlarged sectional view of a memory cell for explaining the operation of the conventional semiconductor memory device. In the figure, 1 is a semiconductor substrate, 2 is a memory cell, 3.3
a is an isolation oxide film, 4 is a charge storage region, 8 is a groove portion, 80
is a groove for separation. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A semiconductor memory device in which a plurality of memory cells are arranged at intervals, the device comprising: a semiconductor substrate; a plurality of grooves formed on the semiconductor substrate corresponding to the plurality of memory cells; A charge storage region of a memory cell formed on an inner surface, an isolation region made of an insulating film formed between the plurality of memory cells, and an isolation region formed integrally with the trench in the isolation region between the adjacent trenches. A semiconductor memory device comprising: a trench; and an insulating film formed on an inner surface of the isolation trench.