JPH08167698A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE: To eliminate junction-leakage and achieve information holding for a long time by forming a transistor, for functioning as a switch of a memory cell, and a capacitor, for storing electric charge, from a semiconductor film provided on a main surface of a semiconductor substrate with an insulating film being disposed therebetween. CONSTITUTION: A memory cell is constructed of a transistor, for functioning as a switch of a memory cell, and a stack-type capacitor, for storing electric charge. An insulating film 20 made of silicon oxide is formed on a silicon substrate 1, and the memory cell is provided on a polysilicon film 21 formed on the insulating film 20. Therefore, the memory cell is separated from the substrate 1 by the insulating film 20, and has no PN junction in a node part which has caused leakage in a conventional DRAM cell. The stack-type capacitor is formed also on the insulating film 20, and has no junction with the substrate 1. Thus, junction-leakage in the memory cell is eliminated so that information can be held for a long time period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a memory cell, and more particularly to a DRAM (Dynamic Random Memory).
ccess memory) and effective technology.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional DRAM memory cell. The memory cell is composed of a capacitor C for accumulating charges and a transfer transistor T for switching, and information "0" and "1" are stored depending on whether or not charges are accumulated in the capacitor C. The capacitor C is connected to the bit line BL via the transfer MIS transistor T, and the bit line BL is connected to the data read circuit and the data write circuit. At the time of reading or writing, the transistor T is turned on by applying a voltage to the gate connected to the word line WL, the bit line BL and the capacitor C are electrically connected, and reading or writing is performed.

FIG. 3 is a longitudinal sectional view illustrating the structure of the conventional DRAM memory cell shown in FIG.

In the figure, reference numeral 1 is a semiconductor substrate of P-type single crystal silicon, and an element isolation insulating film 2 is provided on the main surface of the inactive region of the semiconductor substrate 1. Below the element isolation insulating film 2, a P + type channel stopper region 3 is provided. The memory cell of FIG. 3 has its periphery defined by the element isolation insulating film 2.

The memory cell is composed of a transistor and a capacitor, and the transfer MIS transistor is a gate insulating film 4 provided on the main surface of the silicon semiconductor substrate 1, a gate electrode 5 provided on the gate insulating film 4, and this gate. It has a pair of N + type semiconductor regions 6 and 6 provided on the main surface of the semiconductor substrate 1 on the side of the electrode 5. Spacers 7 are provided on the upper and side walls of the gate electrode 5.

The N + type semiconductor regions 6 and 6 are N + diffusion layers serving as sources and drains, and the gate electrode 5 is composed of polysilicon, polycide, refractory metal or the like.

The capacitor is of a stack type and comprises a first electrode 9, an interlayer film 11 and a second electrode 10. The interlayer film 11 is an insulating film made of SiO ₂ or SiN. The semiconductor region 6 serving as the drain of the transfer MIS transistor has a first wiring layer 8 serving as a bit line.
, The gate electrode 5 is connected to the word line, the semiconductor region 6 serving as the source is connected to the first electrode 9 of the capacitor, and the upper electrode 10 of the capacitor is connected to the reference potential.

In the figure, reference numerals 12 and 13 denote interlayer insulating films for preventing electrical continuity between each element and wiring or between wirings, 14 denotes a second wiring layer forming a circuit, and 15 denotes It is a protective insulating film.

[0009]

The present inventor has found the following problems as a result of examining the above prior art.

The DRAM memory cell stores information "0" and "1" depending on the presence / absence of electric charge accumulated in the capacitor. However, the electric charge accumulated in the capacitor gradually decreases due to a minute leak, and as time elapses. The stored information in the memory cell is lost. Therefore, in the DRAM, a refresh operation of periodically reading and rewriting the memory cell information is necessary before the stored information in the memory cell is lost. While this refresh operation is being performed, the normal read / write operation is prohibited, so that the read / write efficiency of the memory system using the DRAM is lowered.

The DRAM has a self-refresh function for automatically refreshing the RAM itself.
The power consumed for such a refresh operation increases the power consumption of the DRAM.

If the stored information in the memory cell can be retained for a longer time, the power consumption required for self-refreshing can be reduced by extending the time interval for consuming the refresh current, which accounts for most of the power consumption during self-refreshing. It becomes possible. Therefore, it is necessary to reduce the minute leak of the memory cell and hold the stored information of the memory cell for a longer time.

In the transfer MIS transistor,
The diffusion layers serving as the source and drain are, for example, N-type, and the silicon substrate is, for example, P-type, so that the boundary between the two becomes a PN junction, and the accumulated charge decreases due to the junction leak of the PN junction.

An object of the present invention is to eliminate the junction leak, which is the largest cause of the minute leak of DRAM memory cells,
It is an object of the present invention to provide a technique capable of holding stored charges, that is, holding information for a longer time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

A semiconductor film is formed on the main surface of the semiconductor substrate via an insulating film, and the semiconductor film electrically insulated from the semiconductor substrate causes a transistor functioning as a switch of a memory cell and a capacitor storing charges. To form.

As a technique for forming a semiconductor element on an insulator, solid state technology (Solid St
ATE Technology) January 1991, pages 26 to 32, SOI (Silicon On Insulato)
A technique called r) is known, but this technique is intended to form a high-speed transistor by using single crystal silicon formed on an insulator for the purpose of reducing junction capacitance or operating at high speed. The memory cell is not formed on the insulating film by paying attention to the junction leak as in the present invention.

[0019]

According to the above-mentioned means, the memory cell of the semiconductor memory device of the present invention is separated from the semiconductor substrate by the insulating film such as SiO ₂ , and the node which has caused the leakage in the conventional DRAM memory cell. There is no partial PN junction. The capacitor is also a stack type capacitor, which is formed on the insulating film and has no junction with the semiconductor substrate. For this reason, junction leakage due to the PN junction does not occur, so that the information retention time of the memory cell is significantly extended as compared with the conventional memory cell.

The structure of the present invention will be described below together with embodiments.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0022]

【Example】

(Embodiment 1) FIG. 1 is a vertical sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention.

The memory cell of this embodiment comprises a transistor and a capacitor. An insulating film 20 of silicon oxide is formed on a P-type single crystal silicon semiconductor substrate 1, and a polysilicon film 21 formed on this insulating film. It is provided in.

The transfer MIS transistor is provided on the gate insulating film 4 provided on the polysilicon film 21, the gate electrode 5 provided on the gate insulating film 4, and the polysilicon film 21 on the side of the gate electrode 5. A pair of N +
The semiconductor regions 6 and 6 are provided. Spacers 7 are provided on the upper and side walls of the gate electrode 5.

The N + type semiconductor regions 6 and 6 are N + diffusion layers serving as sources and drains, and the gate electrode 5 is composed of polysilicon, polycide, refractory metal or the like.

The capacitor is a stack type and the first electrode 9
And the interlayer film 11 and the second electrode 10. The interlayer film 11 is an insulating film made of SiO ₂ or SiN.

The semiconductor region 6 serving as the drain of the transfer MIS transistor has a first wiring layer 8 serving as a bit line.
, The gate electrode 5 is connected to the word line, the semiconductor region 6 serving as the source is connected to the first electrode 9 of the capacitor, and the second electrode 10 of the capacitor is connected to the reference potential.

In the figure, 12 and 13 are interlayer insulating films for preventing electrical conduction between each element and wiring or between each wiring and wiring, 14 is a second wiring layer constituting a circuit, and 15 is a second wiring layer. It is a protective insulating film.

A method of manufacturing the memory cell of the semiconductor memory device of this embodiment will be described with reference to FIGS. 4 to 9 and FIG.

First, the insulating film 20 is deposited in the memory cell formation region on the main surface of the P-type silicon semiconductor substrate 1. This state is shown in FIG.

Next, the polysilicon film 2 is formed on the insulating film 20.
1 is deposited by the CVD (Chemical Vapor Deposition) method and processed into a predetermined shape. This state is shown in FIG.

Next, the surface of the polysilicon film 21 is thermally oxidized to form an oxide film, and then a polysilicon film is deposited on the main surface of the silicon semiconductor substrate by the CVD method, and this laminated film is processed into a predetermined shape. The gate insulating film and the gate electrode 5
To form. This state is shown in FIG.

Next, N-type impurities are ion-implanted into the polysilicon film 21 by using the gate electrode 5 as a mask, and N
The type semiconductor regions 6 and 6 are formed.

Next, CVD is performed on the upper portion and side wall of the gate electrode 5.
A spacer 7 is formed by the method, and arsenic is ion-implanted using the gate electrode 5 and the spacer 7 as a mask, and the regions 6 serving as the source and drain are made N +. Next, polysilicon to be the first electrode of the stack type capacitor is deposited, and the first electrode 9 is formed into a required shape by photolithography. Impurities are introduced into polysilicon in order to ensure conductivity. This state is shown in FIG.

Next, the surface of the first electrode 9 is thermally oxidized to form the interlayer film 11 of the capacitor, polysilicon to be the second electrode of the capacitor is deposited, and the second electrode 10 is formed into a required shape by photolithography. Form. Impurities are introduced into polysilicon in order to ensure conductivity. This state is shown in FIG.

Next, a silicon dioxide film is deposited as an interlayer insulating film 12 by a CVD method, an opening of the wiring 8 is formed by a photolithography technique and a dry etching technique, an aluminum alloy which is a conductive film is deposited, and a photolithography technique is used. Then, the first wiring layer 8 is formed by processing into a predetermined shape by dry etching technique. This state is shown in FIG.

After that, the interlayer insulating film 13 and the second wiring layer 1 are formed.
4, a silicon dioxide film and a silicon nitride film are deposited as a protective film insulating film 15 on the upper layer by a plasma CVD method to form a memory cell of the semiconductor memory device of this embodiment. This state is shown in Figure 1.
Shown in

Although omitted in the above process, DR
Other MISFETs used in AM peripheral circuits, etc.
It is formed in parallel with the above steps by a known method.

(Embodiment 2) FIG. 10 is a vertical sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention.

The memory cell of this embodiment is composed of a transistor and a capacitor. An insulating film 20 of silicon oxide is formed on a P-type single crystal silicon semiconductor substrate 1, and a polysilicon film 21 formed on this insulating film is formed. It is provided.

In this embodiment, unlike the above-described embodiments, the polysilicon film 21 forming the source and drain of the transfer MIS transistor is the first capacitor.
It also serves as the electrode 22. The capacitor includes a first electrode 22 made of the polysilicon film 21, an insulating film 23, and a second electrode 2
4 and 4.

A method of manufacturing the memory cell of the semiconductor memory device of this embodiment will be described below.

First, the insulating film 20 is deposited in the memory cell formation region on the main surface of the P-type silicon semiconductor substrate 1.

Next, a polysilicon film to be the second electrode 24 of the capacitor is deposited on the insulating film 20 by the CVD method, and after being formed into a predetermined shape, the surface of the second electrode 24 is thermally oxidized to form the capacitor. The insulating film 23 is formed.

Next, the transfer M is formed on the insulating film 20.
A polysilicon film 21 to be the semiconductor region of the IS transistor and the first electrode 22 of the capacitor is deposited by the CVD method and processed into a predetermined shape. A portion of the polysilicon film, which will be the first electrode 22 of the capacitor, is formed so as to cover the second electrode 24.

Next, the surface of the polysilicon film 21 is thermally oxidized to form an oxide film, and then a polysilicon film is deposited on the main surface of the silicon semiconductor substrate by the CVD method, and this laminated film is processed into a predetermined shape. Then, the gate insulating film 4 and the gate electrode 5 are formed.

Next, N-type impurities are ion-implanted into the polysilicon film 21 by using the gate electrode 5 as a mask, and N
The + type semiconductor regions 6 and 6 are formed.

Next, CVD is performed on the upper part and the side wall of the gate electrode 5.
A spacer 7 is formed by the method, and arsenic is ion-implanted using the gate electrode 5 and the spacer 7 as a mask, and the regions 6 serving as the source and drain are made N +.

Next, a silicon dioxide film is deposited as an interlayer insulating film 11 by a CVD method, an opening of the wiring 8 is formed by a photolithography technique and a dry etching technique, an aluminum alloy which is a conductive film is deposited, and a photolithography technique is performed. Then, the wiring layer 8 is formed by processing into a predetermined shape by the dry etching technique.

After that, the interlayer insulating film 13 and the second wiring 14 are formed.
A silicon dioxide film and a silicon nitride film are deposited as a protective insulating film 15 on the layer above by a plasma CVD method to form a memory cell of the semiconductor memory device of this embodiment. This state is shown in FIG.

Although the first electrode of the capacitor is formed on the second electrode in the present embodiment, the second electrode of the capacitor may be formed on the first electrode. .

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0053]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, by providing the memory cell on the insulating film, it is possible to eliminate the junction leak from the capacitor.

(2) According to the present invention, due to the above effect (1), there is an effect that the information holding time of the memory cell can be made longer.

(3) According to the present invention, due to the above effect (2), there is an effect that the time interval for performing the refresh operation can be extended.

(4) According to the present invention, due to the above effect (3), there is an effect that the time for interrupting the normal read / write operation due to the refresh operation can be reduced.

(5) According to the present invention, the above effect (3) has the effect of reducing the average power consumption during self-refresh.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a memory cell of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional DRAM memory cell.

FIG. 3 is a vertical sectional view showing a conventional DRAM memory cell.

FIG. 4 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device which is an embodiment of the present invention.

FIG. 5 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a vertical cross-sectional view showing the manufacturing process of the memory cell of the semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a vertical cross-sectional view showing a memory cell of a semiconductor memory device according to another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Channel stopper, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Semiconductor region, 7 ... Spacer, 8 ... 1st wiring layer, 9, 22 ...
First electrode, 10, 24 ... Second electrode, 11, 23 ... Interlayer film, 12, 13 ... Interlayer insulating film, 14 ... Second wiring layer, 15
... Protective insulating film, 20 ... Insulating film, 21 ... Polysilicon film.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/266

Claims (6)

[Claims] 1. A semiconductor memory device having a memory cell composed of a transistor functioning as a switch and a capacitor for accumulating charges, wherein the semiconductor memory device is formed on a main surface of a semiconductor substrate via an insulating film and electrically insulated from the semiconductor substrate. The semiconductor memory device, wherein the transistor and the capacitor are formed by a conductive film that is formed. 2. The semiconductor memory device according to claim 1, wherein the conductor film is polysilicon. 3. The semiconductor memory device according to claim 1, wherein the capacitor is a stack type. 4. A method of manufacturing a semiconductor memory device having a memory cell including a transistor functioning as a switch and a capacitor storing electric charge, the method comprising: forming an insulating film on a semiconductor substrate; and forming a semiconductor film on the insulating film. A step of forming a gate electrode on the semiconductor film via an insulating film, a step of introducing impurities into the semiconductor film using the gate electrode as a mask, and a step of forming a first electrode of a capacitor. And a step of forming an interlayer film of a capacitor, and a step of forming a second electrode of the capacitor, a method of manufacturing a semiconductor memory device. 5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the semiconductor film is polysilicon. 6. The method of manufacturing a semiconductor memory device according to claim 4, wherein the capacitor is a stack type.