JPH1116344A - 3-transistor dram memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a through current and reduce power consumption by setting the number of data read nodes and data write nodes of a memory cell connected to one data line of the data line pair equal to the number of data read nodes and data write nodes of the memory cell connected to the other data line. SOLUTION: A pair of data lines B00, B01 of the same column are connected to one differential amplifier and two MOS transistors for write switch and two MOS transistors for read switch are respectively connected to the data lines B00, B01. A memory cell is arranged so that the MOS transistor for write switch and MOS transistor for read switch are alternately connected to one data line to reduce the area of memory array. Moreover, a through current preventing circuit 31 prevents generation of a through current flowing between the power source voltage and grounding voltage during the write and read operation to the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a three-transistor DRAM memory device, and more particularly to a three-transistor DRAM device.
The present invention relates to a data line (bit line) structure of a RAM memory device.

[0002]

2. Description of the Related Art Due to the rapid development of semiconductor technology in recent years, high integration of semiconductor memory devices is rapidly progressing.
In particular, dynamic RAM (Dynamic Random Access Me
(Mory; DRAM) memory devices are being highly integrated at a remarkable rate. The memory cell is 1-4 kbit
s DRAM was a three-transistor cell using three transistors, but from 4 kbits DRAM onwards, by using a special DRAM process for high integration, the one-transistor cell with the least number of elements and wiring is currently available. Has been adopted all the time.

In recent years, without increasing production costs,
Attempts have been made to simultaneously realize the high integration of the DRAM and the high speed of the LOGIC. As a method, 1 to 4 transistors are used without using the current mainstream one-transistor cell.
There has been proposed a method of constructing a three-transistor cell used in DRAMs up to kbits on a LOGIC process. This is because, with a one-transistor cell, it is possible to obtain a DRAM with the highest degree of integration, but since the device structure is complicated, the total number of manufacturing steps becomes very large. There is also a problem that the manufacturing cost increases. On the other hand, if three-transistor cells are used, the manufacturing process is exactly the same as the logic process, so that the number of manufacturing steps is shorter than that of one-transistor cells, and the manufacturing cost can be reduced.

As described above, the ASIC (Application Spec)
ific Integrated Circuit) For embedded DRAM,
Three-transistor DRAM using three-transistor cells
Is being considered, but a three-transistor DRAM
For example, the following is a basic configuration of the memory device.

FIG. 5 shows a conventional three-transistor DRAM.
FIG. 3 is a block diagram illustrating a configuration example of a memory device. As shown in FIG. 5, the three-transistor DRAM memory device has a memory cell array 1a (here, two columns (columns) and four rows (rows)) in which three transistor cells are arranged in a matrix. ), A reference level output circuit (hereinafter referred to as “dummy cell”) 3, a differential amplifier 5, and a row decoder 7. RW
0 to RW3 are read word lines, WW0 to WW3 are write word lines, RB0 and RB1 are read data lines (bit lines), WB0 and WB1 are write data lines (bit lines), and DW0 and DW1 are dummy cells 3.
Is a dummy word line for selecting. The row decoder 7 stores memory cells (including the dummy cells 3) in the row direction of the memory cell array 1a in RW0 to RW3 and WW0 to WW.
3. Select according to DW0 and DW1. Although not shown in FIG. 5, the column decoder RBs the memory cells (including the dummy cells 3) in the column direction of the memory cell array 1a.
0, RB1, WB0, WB1. The differential amplifier 5 compares an output signal read from a selected memory cell to one read data line (for example, RB0) with a reference voltage, and amplifies the difference. As the reference voltage, a read signal from the dummy cell 3 connected to another read data line (for example, RB1) is used.

In the memory device having such a configuration, no memory cell is arranged in the memory cell array 1a, and a region (only a hatched region in the drawing, hereinafter referred to as WTA) through which only the word line passes occurs. As a result, the area occupied by the memory cell array 1a with respect to the entire memory device may increase, which may hinder high integration.

FIG. 6 shows the memory device shown in FIG. 5 without the region WTA through which only the word lines pass. That is, the two data lines connected to the differential amplifier 5 are used as a read data line and a write data line of the same column, and the dummy cell 3 is connected to the write data line, so that the intersection of the word line and the data line is formed. The memory cells are arranged in all of them.

However, when information is read from the memory cells by the differential signal between the read data line and the write data line in the same column, the two data lines connected to the differential amplifier are read out. Balance becomes a problem on the contrary. Usually, in order to improve the sensitivity of a differential amplifier, a pair of data lines connected to it must be well balanced. However, in the configuration as shown in FIG. 6, only the read MOS transistor (the MOS transistor indicated by A in the figure) is connected to the read data line, and the write MOS transistor (the MOS transistor indicated by B in the figure) is connected to the write data line. Transistors) are connected, but the read MOS transistor and the write MOS transistor have different transistor sizes (gate length, gate width), so that a difference occurs between the two data line capacitances. This difference in capacitance becomes noise of the differential amplifier, thereby lowering the sensitivity.

FIG. 7 is a diagram showing a specific circuit configuration of a dummy cell, a memory cell arranged in a memory cell array, and a differential amplifier in the memory device shown in FIG. The dummy cell 3 outputs the reference voltage input to the differential amplifier as described above. Its configuration is made up of three transistors, like the memory cell 9, and its output voltage is usually set so as to have a predetermined relationship with the high-level signal and the low-level signal of the memory cell 9. The differential amplifier 5 is basically a flip-flop type differential amplifier, as described above, compares the output signal from the memory cell with the reference voltage which is the output signal from the dummy cell, and amplifies the difference. .

For example, data is read from the memory cell 9 as follows (assuming that the memory cell 9 stores the H level). The row decoder 7 supplies an H level to the read word line RW1, and the M level of the memory cell 9
The OS transistor F is turned on. Since the memory cell 9 stores the H level (the capacitor O holds the H level), the MOS transistor H also becomes conductive, whereby the L level is output to the read data line RB1 and the differential amplifier 5 is input. On the other hand, in the dummy cell 3, the dummy word line D
H level is supplied to WR and DWW, and both the MOS transistor C and the MOS transistor E become conductive. If the write data line WB0 is at the H level, the H level is input to the gate of the MOS transistor D via the MOS transistor E, so that the MOS transistor D is also turned on. Therefore, a predetermined reference voltage is output to the read data line RB0. The differential amplifier 5 has a differential amplifier activation control circuit 11 for controlling its operation.
The control signal SPLG is set to L level, and the control signal SNLG is set to H level.
By setting the level, the state is activated, and the difference between the signals output to the two data lines is amplified and output.

In such a circuit configuration, there is a problem that a through current flows between the power supply voltage and the ground voltage at the time of writing and reading operations to and from a memory cell.
That is, when data is read from the memory cell 9 described above, the gate of the MOS transistor L forming the differential amplifier 5 is connected to the ground voltage P-MOS transistor H-MO.
The L level is supplied through the path of the S transistor F and the read data line RB1, so that the p-type MOS transistor L is turned on. Therefore, the power supply voltage Q and the ground voltage R are different from the MOS transistor I-MO
It is connected via the S transistor L-read data line RB0-MOS transistor C-MOS transistor D, and a through current flows. This may lead to an increase in power consumption. In addition, this defect is shown in FIG.
This can occur in the memory device shown in FIG.

[0012]

As described above,
In the three-transistor DRAM memory device shown in FIG. 5, it was difficult to improve the degree of integration due to an increase in the area of the memory cell array.

On the other hand, a three-transistor type DRA shown in FIG.
In the M memory device, the balance of a pair of data lines connected to the differential amplifier is poor, and therefore, the sensitivity of the differential amplifier may be reduced.

In both the three-transistor DRAM memory devices of FIGS. 5 and 6, there is a problem that power consumption is large because a through current flows between a power supply voltage and a ground voltage at the time of writing and reading. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to improve the electrical symmetry of a pair of data lines connected to a differential amplifier without increasing the area of a memory cell array. Accordingly, it is an object of the present invention to provide a three-transistor type DRAM memory device which can realize high noise immunity.

Another object of the present invention is to provide a three-transistor DRAM memory device which can prevent a through current from flowing between a power supply voltage and a ground voltage at the time of writing and reading and can reduce power consumption. It is in.

[0017]

In order to achieve the above object, a first feature of the present invention is that a memory cell array 1c in which a plurality of 3-transistor DRAM memory cells are arranged in a matrix as shown in FIG. And the memory cell array 1c
And a plurality of differential amplifiers 5 connected to the data pairs B00 and B01, B10 and B11, respectively, and the other side of the differential amplifier 5 across the data pairs B00 and B01 and B10 and B11. And the data pair B
00 and B01, and a three-transistor DRAM having at least a plurality of reference level output circuits 3 for outputting a reference voltage to one of the data lines B10 and B11.
In the memory device, the data pairs B00 and B01,
B10 and B11 are the number of data read nodes and data write nodes of the memory cells connected to the one data line, and the number of data read nodes and data write nodes of the memory cells connected to the other data line. That is, it is configured to be equal to the number.

According to the first feature of the present invention, the number of data read nodes and data write nodes of the memory cells connected to the respective data lines of the data pair line connected to one differential amplifier are equal. By doing so, the capacity difference between the two data lines can be reduced, and imbalance of the data lines can be eliminated. Therefore, since the data pair connected to one differential amplifier is well balanced, the sensitivity of the differential amplifier is improved. Thereby,
It is possible to connect two data lines in the same column to the same differential amplifier. Therefore, it is possible to eliminate the area WTA through which only the word line passes, which is a conventional problem, and to reduce the area of the memory cell array. .

Here, since one data line is connected to both the data read node and the data write node of the memory cell, during the read operation, the data of the memory cell selected for that data line is read. When a read node is connected, a read signal is output from the memory cell to the data line. On the other hand, when a data write node of a selected memory cell is connected to the data line, a read signal (reference voltage) from a reference level output circuit (dummy cell) is output to the data line. become.

The first feature of the present invention is realized when the number of data read nodes and data write nodes of the memory cells connected to each data line of the data pair line is equal. If the data read node and the data write node of the cell are alternately connected to the one data line for each row of the memory cell array, the area of the memory cell array can be further reduced. That is, at a position where the data read node and the data write node of the memory cell connected to the one data line are close to each other (see FIG. 3A),
As shown in FIG. 3B, a layout pattern is formed such that the write switch MOS transistor T1 and the read switch MOS transistor T2 of the memory cell share the contact 41 with the one data line 47. Because you can do it. By doing so, each of the contacts requires only １ ／ of the contacts, and the area is reduced accordingly.

A second feature of the present invention is that, as shown in FIG. 2, a memory cell array 1c in which a plurality of three-transistor DRAM memory cells are arranged in a matrix, and a plurality of data pairs B00 of the memory cell array 1c. B01, B10
Differential Amplifiers 5 Connected to Each and B11
Is connected to the other side of the differential amplifier 5 with the data pair lines B00 and B01 and B10 and B11 therebetween, and a reference voltage is applied to one of the data pair lines B00 and B01 and B10 and B11. In the three-transistor DRAM memory device having at least a plurality of reference level output circuits 3 for outputting the data, the reference level output circuit 3 and the data pairs B00, B01, B1
A means for controlling the conduction state between 0 and B11 is provided.

According to the second feature of the present invention, a problem that a through current flows between a power supply voltage and a ground voltage at the time of writing and reading operations to a memory cell, which is a conventional problem, is solved by a predetermined problem. By making the reference level output circuit and the data pair line non-conductive during the period,
The path of the through current is cut off, thereby preventing generation of the through current and reducing power consumption.

Here, the means for controlling the conduction state can be realized, for example, by connecting a MOS transistor between an output line of the reference level output circuit and the data pair line, Further, it is sufficient that the respective signals of the data pair lines input to the differential amplifier are changed from the conductive state to the non-conductive state after being amplified.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

Before describing the embodiment of the present invention, the operation of a general three-transistor DRAM memory cell will be described with reference to FIG. In the figure, a three-transistor type DRAM memory cell includes a switching (writing switch) MOS transistor 13, a switching (reading switch) MOS transistor 15,
It comprises a read data line drive MOS transistor 17, a write word line 21, a write data line 23, a read word line 25, and a read data line 27. The gate input capacitance of the MOS transistor 17 mainly fulfills the role of the capacitor 19 for storing charges. Normally, the MOS transistors are all constituted by n-type MOS transistors in terms of the operation speed. Note that the write switch MOS transistor 13
The connection point between the read data line 23 and the read data line 27 is called a write node, and the connection point between the read switch MOS transistor 15 and the read data line 27 is called a write node.

The write operation is performed by setting the write word line 21 to the H level, turning on the MOS transistor 13, and writing the H level to the capacitor 19 via the write data line 23. On the other hand, when the write word line 21 is at the L level, the MOS transistor 1
3 is in a non-conducting state, so that the previously written data is held in the capacitor 19 as it is.

In the read operation, first, the read data line 27 is set to the H level (pull-up), and then the read word line 25 is set to the H level to set the MOS transistor 15
Is made conductive. Here, when the H level is stored in the capacitor 19, the MOS transistor 17 is turned on, and when the L level is stored, the MOS transistor 17 is turned off. Therefore, when the MOS transistor 15 is turned on, if the MOS transistor 17 is turned on, H
The read data line 27 set to the level
The transistor 15 and the MOS transistor 17 are connected to the ground potential via the MOS transistor 17 and pulled down to the L level. On the other hand, M
When the OS transistor 17 is off, the read data line 27 holds the H level. Reading is performed by detecting a change in the potential of the read data line 27.

Next, a three-transistor DRAM memory device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows a three-transistor type D according to the present embodiment.
FIG. 2 is a diagram illustrating a configuration of a RAM memory device. The same parts as those in the related art are denoted by the same reference numerals.

Referring to FIG.
The AM memory device includes a memory cell array 1c in which three transistor cells are arranged in a matrix (again, a case of two columns and four rows is shown as in the related art), a dummy cell (reference level output circuit) 3, and Differential amplifier 5
And a row decoder 7. And RW
0 to RW3 are read word lines, WW0 to WW3 are write word lines, B00, B01, B10 and B11 are data lines (bit lines), and the row decoder 7 stores the memory cells in the row direction of the memory cell array 1c in the row direction.
3. Select from WW0 to WW3. Although not shown, the column decoder stores the memory cells in the column direction of the memory cell array 1c as B00, B01, B10, B11.
Select by. On the other hand, the differential amplifier 5 compares an output signal read from a selected memory cell to one data line (for example, B00) with a reference voltage, and amplifies the difference. The reference voltage is applied to another data line (for example, B0
The output signal of the dummy cell 3 read in 1) is used.

Here, the feature of the present invention is that, first, the write switch MOS transistor 13 and the read switch MOS transistor 13 shown in FIG. 1 connected to a pair of data lines of the same column connected to one differential amplifier. The point is that the number of MOS transistors 15 is equal.

In the conventional memory device shown in FIG. 6, two data lines connected to one differential amplifier are read data lines and write data lines of the same column, so that a word line and a data line are connected. The memory cells are arranged at all the intersections, thereby eliminating the region WTA through which only the word lines pass. However, due to the difference in size between the write switch MOS transistor and the read switch MOS transistor connected to the two data lines, a capacitance difference occurs between the two data lines, leading to a decrease in the sensitivity of the differential amplifier. .

Therefore, in the present invention, as described above,
By making the number of write switch MOS transistors and the number of read switch MOS transistors connected to each of the pair of data lines equal, the capacitance difference between the two data lines is eliminated. Therefore, according to the present invention, while reducing the area of the memory cell array,
It is possible to improve the electrical symmetry of a pair of data lines connected to one differential amplifier and realize high noise immunity.

For example, in the memory device according to the present embodiment shown in FIG. 2, B00 and B01 are a pair of data lines of the same column connected to one differential amplifier.
Two write switch MOS transistors and two read switch MOS transistors are connected to each of 0 and B01. B10 and B11 are also a pair of data lines of the same column connected to one differential amplifier, and these are the same as above.

Then, as shown in FIG. 2, the write switch MOS transistor and the read switch MOS transistor
If the memory cells are arranged so that the transistors and the transistors are alternately connected to one data line, the area of the memory cell array can be further reduced as compared with a case where the same number is used. FIG. 3A is a diagram showing an arrangement of two memory cells in a memory cell array. As shown in FIG. 3A, normally, a write switch MOS transistor T1 and a read switch MOS transistor T2 each store one data. Line (B10) and one contact each (35, 3
(Black dots indicated by reference numeral 7). However, the actual layout pattern is, as shown in FIG.
MOS transistors T1 and T2 can be connected by one contact.
Can be connected to one data line, and each transistor requires only one contact, instead of one contact. Here, FIG. 39 shows a transistor region, FIG. 41 shows a contact, FIG. 43 shows a write word line WW0, FIG. 45 shows a read word line RW1, and FIG. 47 shows a data line B10.

Therefore, as described above, if the memory cells are arranged such that the write switch MOS transistors and the read switch MOS transistors are alternately connected to one data line, as shown in FIG. In addition, since the write switch MOS transistor and the read switch MOS transistor are close to each other, a common contact for connecting them to one data line can be used. As a result, the number of required contacts is reduced, and the area of the memory cell array can be reduced accordingly.

The memory device shown in FIG. 2 is provided with a dummy cell control circuit 29 for controlling a dummy cell. This is because, in the present invention, if one data line is connected to a read switch MOS transistor, it becomes a read data line for that memory cell, while if a write switch MOS transistor is connected, This is because it becomes a write data line. Therefore, the dummy cell control circuit 29 selects the dummy cell 3 in the row direction of the memory cell array 1c by the dummy word lines DWR0, DWR1, and DRV, and outputs a reference voltage to which of the two data lines of the selected row. Select further.

Further, in addition to the above-described first feature, the present invention includes, as a second feature, a through current prevention circuit 31 between a pair of data lines and an output line of a dummy cell connected thereto. That is the point.

This through current prevention circuit 31 is a conventional one shown in FIG.
2 prevents the occurrence of a through current flowing between the power supply voltage and the ground voltage at the time of writing and reading operations to and from the memory cell. For example, as shown in FIG. (Here, an n-type MOS transistor). The operation is specifically performed as follows.

FIG. 4 shows the memory device shown in FIG.
5 is an example of a timing chart showing a data read operation of one memory cell. The row decoder supplies an H level to a predetermined read word line RW, and makes the read switch MOS transistor of the selected memory cell conductive. Thereby, the output signal of the memory cell is output to one data line. On the other hand, a predetermined reference voltage is output to another data line by the dummy cell. Then, the differential amplifier is activated by a differential amplifier activation control circuit that controls its operation, by setting the control signal SPLG to L level and the control signal SNLG to H level,
The two data lines are amplified to the full swing H level and L level. Here, the through current prevention circuit 31 which is a feature of the present invention is a circuit diagram after a lapse of a predetermined time after the time when the two data lines are amplified to the full swing H level and L level (time indicated by t in FIG. 4). When the through current prevention circuit control circuit 33 shown in FIG. 2 changes the control signal ICS from the H level to the L level, the state changes from the conductive state to the non-conductive state. Accordingly, the path between the power supply voltage and the ground voltage through which the through current, which has conventionally been a problem, is cut off, and the generation of the through current can be prevented. And power consumption can be reduced. In the present embodiment, the through current prevention circuit is configured by an n-type MOS transistor, but the present invention is not limited to this.
Any configuration may be used as long as it controls the conduction state between the data line and the output line of the dummy cell connected to the data line at the timing described above.

[0040]

As described above, according to the present invention, 3
The number of data read nodes and data write nodes of a memory cell connected to one data line of a data pair line connected to the same differential amplifier of a transistor type DRAM memory device is the same as that of the other, and the data line By alternately connecting the data lines for each row, it is possible to realize a folded data pair line arrangement having good electrical symmetry and excellent noise immunity without incurring a large increase in area.

The data line to which the memory cell is connected and the output line of the reference level output circuit are connected via a MOS transistor, and the conduction state is controlled, so that a through current generated at the time of reading and writing operations is obtained. Reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a general three-transistor DRAM memory cell.

FIG. 2 shows a three-transistor type D according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a RAM memory device.

3A is a diagram showing an arrangement of two memory cells in the memory cell array of FIG. 2, and FIG. 3B is a diagram showing the MOS of FIG.
FIG. 3 is a diagram showing a layout pattern of transistors T1 and T2.

FIG. 4 is an example of a timing chart showing an operation of reading data from one memory cell in the three-transistor DRAM memory device shown in FIG. 2;

FIG. 5 is a block diagram showing a configuration example of a conventional three-transistor DRAM memory device.

FIG. 6 is a block diagram showing another configuration example of a conventional three-transistor DRAM memory device.

FIG. 7 is a diagram showing a specific circuit configuration of the dummy cell of FIG. 5, a memory cell arranged in a memory cell array, and a differential amplifier.

[Explanation of symbols]

1a, 1b, 1c Memory cell array 3 Reference level output circuit (dummy cell) 5 Differential amplifier 7 Row decoder 9 3-transistor DRAM memory cell 11 Differential amplifier activation control circuit 13 Switch (write switch) MOS transistor 15 Switch ( MOS transistor for read switch 17 MOS transistor for driving read data line 19 Capacitor 21 Write word line 23 Write data line 25 Read word line 27 Read data line 29 Dummy cell control circuit 31 Through current prevention circuit 33 Through current prevention circuit control circuit 35, 37, 41 contact 39 transistor region 43 write word line WW0 45 read word line RW1 47 data line B10

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takayuki Abe 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center (72) Inventor Masahiro Kimura Ekimae Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa 25-1 Toshiba Microelectronics Corporation (72) Inventor Toshihiro Kobayashi 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Microelectronics Corporation

Claims (7)

[Claims] 1. A memory cell array in which a plurality of three-transistor type DRAM memory cells are arranged in a matrix, a plurality of differential amplifiers connected to a plurality of data pairs of the memory cell array, and the data pairs. And a plurality of reference level output circuits connected to the other side of the differential amplifier and outputting a reference voltage to one of the data pair lines.
In the RAM memory device, the data pair line includes a data read node of a memory cell connected to the one data line, and a data read node of a memory cell connected to another data line. A three-transistor DRAM memory device, wherein the number of data write nodes is equal to the number of data write nodes. 2. The reference level output circuit outputs a reference voltage to one of the data pairs connected to a data write node of a selected memory cell. 3. A three-transistor DRAM memory device according to claim 1. 3. The three-transistor DRAM according to claim 1, wherein a data read node and a data write node of the memory cell are alternately connected to the one data line for each row of the memory cell array. Memory device. 4. When the data read node and the data write node of the memory cell connected to the one data line are close to each other, the read switch MOS transistor and the write switch MOS transistor of the memory cell are connected to each other. 4. The three-transistor DRAM memory device according to claim 3, wherein the three-transistor DRAM memory device is configured to share a contact with one data line. 5. The connection between the one data line and a data read node and a data write node of the memory cell is regularly formed so as to be the same for each row and column of the memory cell array. 3. The three-transistor DRAM memory device according to claim 1, wherein: 6. A memory cell array in which a plurality of 3-transistor DRAM memory cells are arranged in a matrix, a plurality of differential amplifiers respectively connected to a plurality of data pairs of the memory cell array, and a plurality of data pairs. And a plurality of reference level output circuits connected to the other side of the differential amplifier and outputting a reference voltage to one of the data pair lines.
3. A RAM memory device, comprising: means for controlling a conduction state between the reference level output circuit and the data pair line.
Transistor type DRAM memory device. 7. The means for controlling the conduction state includes a MOS transistor connected between an output line of the reference level output circuit and the data pair line, and is input to the differential amplifier. 7. The three-transistor type DRA according to claim 6, wherein after a signal of each data pair line is amplified, the state changes from a conductive state to a non-conductive state.
M memory device.