EP1161770A1 - Dram cell arrangement and method for producing the same - Google Patents

Dram cell arrangement and method for producing the same

Info

Publication number
EP1161770A1
EP1161770A1 EP00916811A EP00916811A EP1161770A1 EP 1161770 A1 EP1161770 A1 EP 1161770A1 EP 00916811 A EP00916811 A EP 00916811A EP 00916811 A EP00916811 A EP 00916811A EP 1161770 A1 EP1161770 A1 EP 1161770A1
Authority
EP
European Patent Office
Prior art keywords
trench
substrate
word lines
insulating
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00916811A
Other languages
German (de)
French (fr)
Inventor
Josef Willer
Bernhard Sell
Till Schlösser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1161770A1 publication Critical patent/EP1161770A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the invention relates to a DRAM cell arrangement, i. H. a dynamic random access memory cell array with bit lines buried in a substrate and a method of making the same.
  • Em transistor memory cell As a memory cell of a DRAM cell arrangement, a so-called Em transistor memory cell is used almost exclusively, which comprises a transistor and a capacitor. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is driven via a word line, the charge on the capacitor can be read out via a bit line.
  • the general aim is to produce a DRAM cell arrangement that has a high packing density.
  • a DRAM cell arrangement which comprises em transistor memory cells.
  • the space required per memory cell can be 4F ⁇ , where F is the minimum structure size that can be produced using the technology used.
  • F is the minimum structure size that can be produced using the technology used.
  • To produce bit lines trenches running parallel to one another are etched in a silicon substrate. A thin insulating layer is deposited that does not fill the trenches. The trenches are filled with tungsten to produce the bit lines. The insulating layer is removed on each flank of each trench, so that the bit lines are partially exposed laterally. Source / drain areas and channel areas of vertical transistors are generated by epitaxy. The lower source / dram regions of the transistors adjoin the bit lines laterally.
  • Word lines run across the bit lines and m gra- ben, which is between mutually adjacent transistors ⁇ are arranged.
  • the invention is based on the problem to provide a DRAM cell arrangement whose memory cells each having a transistor and a capacitor, whose Bitleitun ⁇ gen in the substrate buried are and with a space requirement for each memory cell of 4F ⁇ and at the same time with as compared to the prior art smaller process costs can be produced. Furthermore, a method for the production thereof is to be specified.
  • a DRAM cell arrangement with memory cells, each of which has a transistor and a capacitor, in which a substrate has trenches which run essentially parallel to one another and in each of which a bit line is arranged.
  • the bit line is arranged in a lower part of the associated trench.
  • the lower part of the trench is provided with an insulation, which is arranged between the bit line and the substrate, except for a strip-shaped recess which runs parallel to the trench and is arranged on a first flank of the trench. Parts of the flanks of the trench arranged above the lower part of the trench and an upper surface of the bit line are provided with further insulation.
  • Word lines run across the bit line.
  • the word lines run above the substrate except for downward protuberances that reach the trenches and are arranged above the bit lines. Insulating structures and the protuberances of the word lines are arranged alternately in the trench above the bit lines.
  • the transistors of the memory cells are designed as vertical transistors. Upper source / drain regions and lower source / drain regions of the transistors are arranged between the trenches. Further insulating structures are arranged in the substrate, which separate upper source / drain regions of transistors adjacent to one another along the trench. The upper source / drain regions of the transi- disturb are connected to the capacitors of the memory cells.
  • the protuberances of the word lines act as gate electrodes of the transistors.
  • the problem is also solved by a method for producing a DRAM cell arrangement with memory cells, each having a transistor and a capacitor, in which an insulating layer is produced on a substrate. Trenches running essentially parallel to one another are produced in the substrate. Lower parts of the trenches are provided with insulation except for strip-shaped cutouts which run parallel to the trenches and are arranged on first flanks of the trench. In the lower parts of the trench depending ⁇ is wells generates a bit line. Parts of the flanks of the trench and the bit lines arranged above the lower parts of the trench are provided with further insulation. Conductive material is applied so that the trenches are filled. A protective layer is created that covers the conductive material.
  • the conductive material and the protective layer are structured in such a way that word lines covered by the protective layer are produced, which run transversely to the bit lines and have downward protrusions that reach the trenches.
  • Insulating material is deposited and, together with the insulating layer, selectively etched back to the protective layer and to the substrate until the substrate is exposed, so that insulating structures are produced in the trench which are arranged between the protuberances of the word lines and above the bit lines.
  • the substrate is selectively etched to the insulating structures so that depressions are created between the word lines and between the trenches.
  • Upper source / dram regions of transistors of memory cells are produced in the substrate between the trenches and between the depressions.
  • lower source / drain regions of the transistors are produced in the substrate, each of which ar adjoin one of the recesses. Further insulating structures are created in the depressions. Capacitors of the memory cells are generated that ren with one of the obe ⁇ each source / drain regions are connected. On the first flanks of the trenches, the word lines act as gate electrodes of the transistors and the further insulation acts as a gate dielectric.
  • the upper source / drain regions, the lower source / drain regions, the insulating structures and the further insulating structures are self-aligned to the word lines and to the trenches, so that the DRAM cell arrangement has a high packing density, ie a small one Space requirement per memory cell can have.
  • the trenches are produced with a strip-shaped mask, the strips of which run parallel to one another, and the word lines are structured with the aid of a further strip-shaped mask, the strips of which run parallel to one another and transversely to the trenches, and the strips have a width of F and a spacing of F. from each other, the space requirement of a memory cell can be 4 F " , where F is the minimum structure size that can be produced in the technology used.
  • the lower source / drain region of a transistor is arranged between the trench and an adjacent trench and is spaced apart from the adjacent trench.
  • a channel region of the transistor which is arranged between the lower source / drain region and the upper source / drain region, is electrically connected to most of the substrate.
  • at least one part of the bit line which adjoins the cutout can consist of doped polysilicon.
  • dopant diffuses out of the bit line ms substrate and forms an e-doped region there, which is arranged between the trench and the adjacent trench, adjoins the recess and is spaced apart from the adjacent trench.
  • This tempering step can be, for example, a thermal oxidation to produce a gate dielectric.
  • Parts of the doped region arranged under the upper source / dram regions act as the lower source / dram regions.
  • the doped region can be structured by the depressions, so that the lower source / dram regions of transistors which are adjacent to one another along the trench and which are separate from one another are produced from the doped region.
  • the lower source / dram regions of the transistors adjacent to one another along the trench and the further insulating structures alternately adjoin the bit line in the region of the cutout.
  • the lower source / drain region is produced by structuring a lower doped layer of the substrate.
  • the structuring is done by creating the trenches.
  • the depressions can also be produced in this case in such a way that they extend deeper than the cutouts in the insulation.
  • the upper source / Dra region can be produced by structuring an upper doped layer of the substrate.
  • the structuring takes place through the creation of the depressions and the trenches.
  • the depressions are therefore at least so deep that they cut through the upper doped layer.
  • the upper source / drain region can also be created by implantation. For example, the implantation takes place after the trenches have been created.
  • a separation of the upper source / dram regions of transistors which are adjacent along the bit line of the zueinan ⁇ takes place from one another by the production of the wells.
  • the capacitor can be connected to the upper source / dram region via a conductive structure.
  • the upper source / drain region of the transistor is covered with an insulating layer.
  • the word line runs over the insulating layer.
  • a projection of the upper source / dram region on the insulating layer overlaps a projection of the word line on the insulating layer of the ⁇ art that it is extended beyond two sides of the projection of the word line, so that projections of two parts of the upper source / dram -Limit the area around the projection of the word line and do not overlap the projection of the word line.
  • the upper source / dram area Transversely to the word line, the upper source / dram area therefore has a larger dimension than the word line.
  • Flanks of the word line are provided with insulating spacers.
  • An upper surface of the word line facing away from the upper source / dram region is provided with an insulating protective layer.
  • the conductive structure covers that
  • the capacitor is arranged on the conductive structure.
  • the conductive structure can be generated in a self-aligned manner with respect to the word line and does not increase the space requirement of the memory cell.
  • the spacers are produced, for example, before the depressions are produced by separating and scratching off insulating material.
  • conductive material is deposited to such a thickness that gaps between the word lines are not filled.
  • a mask is created that honors zonal surfaces of parts of the conductive material, which are arranged above the word line, covered.
  • the lei ⁇ tend material and the substrate are selectively etched to mask ge ⁇ . Parts of the conductive material arranged between the word lines are consequently removed.
  • the conductive structures are created from the conductive material and the depressions are created in the substrate.
  • the mask can be generated in a self-adjusted manner so that the space requirement of the memory cell is not increased.
  • One way to create the mask is to non-conformally deposit insulating material so that the insulating material is thickest over the horizontal surfaces of the portions of conductive material located above the word line.
  • the mask is produced from the insulating material by etching back the insulating material until parts of the conductive material arranged between the word lines are exposed.
  • the mask covers not only the horizontal surfaces of the parts of the conductive material which are arranged above the word line, but also transverse surfaces of the conductive material.
  • a further possibility of producing the mask consists in first depositing and etching back the auxiliary material after the conductive material containing the doped polysilicon has been deposited, until lateral faces of the conductive material are partially exposed. A thermal oxidation is then carried out so that the mask is produced on exposed parts of the conductive material. The auxiliary material is then removed.
  • tungsten is particularly suitable if the substrate consists of silicon, since silicon and tungsten approximate- have the same thermal expansion coefficient, so that mechanical tension and resulting defects in temperature changes are avoided.
  • the polysilicon of the bit line In order to prevent the metal of the bit line and the silicon of the substrate or, if provided, the polysilicon of the bit line from forming a metal silicide, which has a lower electrical conductivity, due to diffusion, it is advantageous to separate between the metal and to provide the silicon or the polysilicon with a diffusion barrier.
  • a lower part of the bit line consists of metal.
  • a diffusion bar containing nitrogen is arranged above it.
  • the polysilicon, which adjoins the cutout, is arranged on the diffusion bar.
  • Parts of the further insulation are thickened at the edges of the word lines.
  • the word lines can consist of two parts.
  • a lower part of the word lines, which comprises the protuberances, is preferably made of doped polysilicon.
  • the second parts of the word lines arranged above the first parts can e.g. B. consist of a metal silicide, such as tungsten silicide.
  • the word lines can also be made of doped polysilicon, from one arranged above, e.g. nitrogenous, diffusion bamers and from metal arranged above, e.g. Tungsten.
  • the insulating layer, the isolation, the further isolation, the isolating structures, the further isolating structures and the mask consist for example of S1O2 or from silicon nitride.
  • other insulating materials lie ⁇ gen in the context of the invention.
  • the protective layer is preferably made of silicon nitride, to allow tive to selec ⁇ etching.
  • the substrate can consist of another material that is suitable for transistors.
  • the substrate may include GaAs.
  • FIG. 1 shows a cross section through a substrate after a first insulating layer, a layer of silicon nitride, a second insulating layer, trench and isolation have been produced.
  • FIG. 2 shows the cross section from FIG. 1 after bit lines and first doped regions have been produced.
  • FIG. 3a shows the cross section from FIG. 2 after a further insulation, second doped regions, word lines, a protective layer and spacers have been produced.
  • FIG. 3b shows a cross section through the substrate parallel to the cross section from FIG. 3a after the process steps from FIG. 3a.
  • FIG. 3c shows a cross section perpendicular to the cross section from FIG. 3a through the substrate after the process steps from FIG. 3a.
  • 3d shows a parallel to the cross section of Figure 3c cross-section through the substrate after the process ⁇ steps of Figure 3a.
  • Figure 3e shows a top view of the substrate m of he ⁇ ste insulating layer, the bit lines, the iso ⁇ lation, the further insulation, the word lines and the spacers are illustrated.
  • FIG. 4a shows the cross section from FIG. 3a after insulating structures, a mask, depressions, conductive structures, further insulating structures, upper source / dram regions, channel regions and lower source / dram regions have been produced.
  • FIG. 4b shows the cross section from FIG. 3b after the process steps from FIG. 4a.
  • FIG. 4c shows the cross section from FIG. 3c after the process steps from FIG. 4a.
  • Figure 4d shows the cross section of Figure 3d after the process ⁇ steps of Figure 4a.
  • FIG. 5 shows the cross section from FIG. 4d after storage nodes, conductive spacers and a capacitor plate have been produced.
  • a substrate 1 made of monolithic silicon is provided.
  • S1O2 is deposited in a thickness of approximately 20 nm on a surface of the substrate 1, so that a first insulating one
  • Layer II is generated.
  • silicon nitride N silicon nitride with a thickness of approx. 50nm deposited.
  • S ⁇ 0 m a thickness of approximately 200 nm makesschie ⁇ (see Figure 1).
  • the second insulating layer 12 With the aid of a strip-shaped first photoresist mask whose strips are approximately lOOnm wide and have a spacing of approximately lOOnm from each other, the second insulating layer 12, the layer of silicon nitride N and the first isolate ⁇ de layer II are patterned, so that the substrate 1 is partially exposed. The first photoresist mask is then removed. With z. B. HBr, the substrate 1 is etched approximately 500 nm deep, so that trenches G are produced (see FIG. 1). The structured second insulating layer 12 acts as a mask.
  • Thermal oxidation is carried out in order to produce an insulation 13 which is approximately 10 nm thick.
  • the insulation 13 covers the flanks and the bottom of the trench G (see FIG. 1).
  • msitu doped polysilicon is deposited with a thickness of approx. 50 nm. It is polished mechanically and mechanically until the second insulating layer 12 is removed. Then the polysilicon is etched back to a depth of approx. 400 nm.
  • HF is suitable as an etchant, for example.
  • the layer of silicon nitride N protects parts of the first insulating layer II.
  • msitu-doped polysilicon is deposited in a thickness of approx. 50 nm and ground back by chemical mechanical polishing until the layer made of silicon nitride N is exposed.
  • n-doping ions 1 Dl strip-shaped first doped regions in the substrate are generated, which are located between the trench and the G SURFACE ⁇ surface of the substrate 1 are adjacent (see Figure 2).
  • the first doped areas Dl are approx. 20nm thick.
  • the doped polysilicon in the trench G forms bit lines B, which are arranged in the lower parts of the trench G.
  • the insulation 13 in the lower parts of the trenches G each has a strip-shaped recess on the first flank, in which the bit line B adjoins the substrate 1 (see FIG. 2).
  • Thermal oxidation is carried out to remove etching residues, and the S1O2 produced in this way is subsequently removed by wet etching. The layer of silicon nitride N is removed.
  • the further insulation 14 is approximately 5 nm thick and covers parts of the flanks of the trenches G and upper surfaces of the bit lines B arranged above the lower parts of the trench G (see FIGS. 3a to 3e).
  • the thermal oxidation acts as a tempering step through which the dopant diffuses from the bit line B m into the substrate 1 and forms second doped regions D2 there (see FIGS. 3a, 3b).
  • Each of the second doped regions D2 adjoins that trench G in which the bit line from which the dopant with which the second doped region D2 was produced is diffused.
  • the second doped region D2 is arranged between this trench and an adjacent trench, adjoins the recess of the trench G and is spaced apart from the adjacent trench.
  • msitu doped polysilicon with a thickness of approx. 50 nm is deposited, so that the trenches G are filled become.
  • Tungsten silicide is deposited in a thickness of approx. 80 nm.
  • S silicon nitride is deposited to a thickness of approximately 50 nm (they ⁇ he figures 3a to 3d).
  • the third photoresist mask is removed.
  • thermal oxidation is carried out so that the further insulation 14 is thickened in sections up to below the word lines W.
  • the further insulation 14 is therefore thickened in the region of edges of the word lines W. This thermal oxidation corresponds to the so-called reoxidation step in planar transistors.
  • silicon nitride is deposited to a thickness of approximately 10 nm and is etched back (see FIGS. 3a to 3e).
  • the spacers Sp cover flanks of the word lines W and parts of the insulation 13 and the further insulation 14.
  • S1O2 is deposited with a thickness of approx. 50 nm and chemically and mechanically polished until the protective layer S is exposed.
  • the S1O2 is then etched back until the substrate 1 is exposed. This creates insulating structures 15 in the trench, so that the trenches of the word lines W and the insulating structures 15 are arranged alternately in each trench G above the associated bit line B (see FIGS. 4a to 4d).
  • msitu doped polysilicon is deposited with a thickness of approximately 10 nm. The thickness is so small that gaps between the word lines W are not filled.
  • the fourth photoresist mask is removed.
  • S1O2 m is deposited at a high rate using a CVD method, so that the S1O2 grows on the horizontal surfaces of the parts of the polysilicon which are arranged above the word lines W about twice as thick, namely about 20 nm , compared to lower positions.
  • the S1O2 is then etched to a depth of approximately 10 nm, so that parts of the polysilicon arranged between the word lines W are exposed.
  • the mask M is thereby generated from the S1O2 (see FIGS. 4a to 4d).
  • the polysilicon and the substrate 1 are selectively etched to the mask M and the insulating structures 15, so that depressions V are produced between the word lines W and specifically between the trenches G (see FIGS. 4b and 4d).
  • the depressions V are approximately 450 nm deep, so that they extend deeper than the cutouts in the insulation 13.
  • the word lines act as gate electrodes of the transistors and the further insulation acts as a gate dielectric.
  • S1O2 is deposited to a thickness of approx. 100 nm and planarized by chemical-mechanical polishing. This creates additional insulating structures 16 in the depressions V (see FIGS. 4b and 4d).
  • the conductive structures L are exposed by means of a photolithographic process (see FIG. 5). Then msitu doped polysilicon is deposited with a thickness of approx. 500 nm. Tungsten silicide is deposited in a thickness of approx. 100 nm.
  • storage nodes K of capacitors are produced from the tungsten silicide and the polysilicon, which are connected to the conductive structures L (see FIG. 5).
  • a surface of the storage nodes K is enlarged by conductive spacers Sp, which are produced by depositing tungsten silicide in a thickness of approximately 20 nm and then scratching it back.
  • silicon nitride is deposited to a thickness of approximately 6 nm and oxidized to a depth of approximately 1 nm.
  • titanium nitride is deposited in a thickness of approximately 100 nm (see FIG. 5).
  • a DRAM cell arrangement is produced, with memory cells, each of which comprises one of the transistors and one of the capacitors connected to them.

Abstract

According to the invention, bit lines are arranged in the lower parts of trenches of a substrate (1). Word lines (W) are located above the substrate (1) except for protuberances which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions (S/Do) are located below the word lines (W) and between adjacent trenches. The capacitors are linked with the upper source/drain regions (S/Do). Conductive structures (L) that surround the word lines (W) from the top and the sides while being insulated from the word lines (W) and bordering on the upper source/drain regions (S/Do) can link the upper source/drain regions (S/Do) with the capacitors.

Description

Beschreibungdescription
DRAM-Zellenanordnung und Verfahren zu deren HerstellungDRAM cell arrangement and method for its production
Die Erfindung betrifft eine DRAM-Zellenanordnung, d. h. eine Speicherzellenanordnung mit dynamischem wahlfreiem Zugriff, bei der Bitleitungen in einem Substrat vergraben sind, und ein Verfahren zu deren Herstellung.The invention relates to a DRAM cell arrangement, i. H. a dynamic random access memory cell array with bit lines buried in a substrate and a method of making the same.
Als Speicherzelle einer DRAM-Zellenanordnung wird derzeit fast ausschließlich eine sogenannte Em-Transistor- Speicherzelle eingesetzt, die einen Transistor und einen Kondensator umfaßt. Die Information der Speicherzelle ist m Form einer Ladung auf dem Kondensator gespeichert. Der Kon- densator ist mit dem Transistor verbunden, so daß bei An- steuerung des Transistors über eine Wortleitung die Ladung des Kondensators über eine Bitleitung ausgelesen werden kann.As a memory cell of a DRAM cell arrangement, a so-called Em transistor memory cell is used almost exclusively, which comprises a transistor and a capacitor. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is driven via a word line, the charge on the capacitor can be read out via a bit line.
Es wird allgemein angestrebt, eine DRAM-Zellenanordnung zu erzeugen, die eine hohe Packungsdichte aufweist.The general aim is to produce a DRAM cell arrangement that has a high packing density.
In US 5 497 017 wird eine DRAM-Zellenanordnung beschrieben, die Em-Transistor-Speicherzellen umfaßt. Em Platzbedarf pro Speicherzelle kann 4F^ betragen, wobei F die minimale, m der angewendeten Technologie herstellbare Strukturgroße ist. Zur Erzeugung von Bitleitungen werden m einem Siliziumsubstrat parallel zueinander verlaufende Graben geatzt. Eine dünne isolierende Schicht wird abgeschieden, die die Graben nicht auffüllt. Zur Erzeugung der Bitleitungen werden die Graben mit Wolfram gefüllt. Jeweils an einer Flanke von jedem Graben wird die isolierende Schicht entfernt, so daß die Bitleitungen seitlich teilweise freigelegt werden. Source/Drain- Gebiete und Kanalgebiete von vertikalen Transistoren werden durch Epitaxie erzeugt. Dabei grenzen untere Source/Dram- Gebiete der Transistoren seitlich an die Bitleitungen an.In US 5 497 017 a DRAM cell arrangement is described which comprises em transistor memory cells. The space required per memory cell can be 4F ^, where F is the minimum structure size that can be produced using the technology used. To produce bit lines, trenches running parallel to one another are etched in a silicon substrate. A thin insulating layer is deposited that does not fill the trenches. The trenches are filled with tungsten to produce the bit lines. The insulating layer is removed on each flank of each trench, so that the bit lines are partially exposed laterally. Source / drain areas and channel areas of vertical transistors are generated by epitaxy. The lower source / dram regions of the transistors adjoin the bit lines laterally.
Wortleitungen verlaufen quer zu den Bitleitungen und m Gra- ben, die zwischen zueinander benachbarten Transistoren ange¬ ordnet sind.Word lines run across the bit lines and m gra- ben, which is between mutually adjacent transistors ¬ are arranged.
Der Erfindung liegt das Problem zugrunde, eine DRAM- Zellenanordnung anzugeben, deren Speicherzellen jeweils einen Transistor und einen Kondensator aufweisen, deren Bitleitun¬ gen im Substrat vergraben sind und die mit einem Platzbedarf pro Speicherzelle von 4F^ und zugleich mit im Vergleich zum Stand der Technik kleinerem Prozeßaufwand herstellbar ist. Ferner soll ein Verfahren zu deren Herstellung angegeben wer¬ den.The invention is based on the problem to provide a DRAM cell arrangement whose memory cells each having a transistor and a capacitor, whose Bitleitun ¬ gen in the substrate buried are and with a space requirement for each memory cell of 4F ^ and at the same time with as compared to the prior art smaller process costs can be produced. Furthermore, a method for the production thereof is to be specified.
Dieses Problem wird gelost durch eine DRAM-Zellenanordnung mit Speicherzellen, die jeweils einen Transistor und einen Kondensator aufweisen, bei der ein Substrat im wesentlichen parallel zueinander verlaufende Graben aufweist, m denen jeweils eine Bitleitung angeordnet ist. Die Bitleitung ist m einem unteren Teil des zugehörigen Grabens angeordnet. Der untere Teil des Grabens ist bis auf eine parallel zum Graben verlaufende an einer ersten Flanke des Grabens angeordnete streifenformige Aussparung mit einer Isolation, die zwischen der Bitleitung und dem Substrat angeordnet ist, versehen. Über dem unteren Teil des Grabens angeordnete Teile der Flanken des Grabens und eine obere Flache der Bitleitung sind mit einer weiteren Isolation versehen. Wortleitungen verlaufen quer zur Bitleitung. Die Wortleitungen verlaufen bis auf nach unten gerichtete Ausstülpungen, die m die Graben reichen und über den Bitleitungen angeordnet sind, über dem Substrat. Isolierende Strukturen und die Ausstülpungen der Wortleitun- gen sind alternierend im Graben über den Bitleitungen angeordnet. Die Transistoren der Speicherzellen sind als vertikale Transistoren ausgestaltet. Obere Source/Drain-Gebiete und untere Source/Drain-Gebiete der Transistoren sind zwischen den Graben angeordnet. Im Substrat sind weitere isolierende Strukturen angeordnet, die obere Source/Drain-Gebiete von entlang des Grabens zueinander benachbarten Transistoren voneinander trennen. Die oberen Source/Drain-Gebiete der Transi- stören sind mit den Kondensatoren der Speicherzellen verbunden.This problem is solved by a DRAM cell arrangement with memory cells, each of which has a transistor and a capacitor, in which a substrate has trenches which run essentially parallel to one another and in each of which a bit line is arranged. The bit line is arranged in a lower part of the associated trench. The lower part of the trench is provided with an insulation, which is arranged between the bit line and the substrate, except for a strip-shaped recess which runs parallel to the trench and is arranged on a first flank of the trench. Parts of the flanks of the trench arranged above the lower part of the trench and an upper surface of the bit line are provided with further insulation. Word lines run across the bit line. The word lines run above the substrate except for downward protuberances that reach the trenches and are arranged above the bit lines. Insulating structures and the protuberances of the word lines are arranged alternately in the trench above the bit lines. The transistors of the memory cells are designed as vertical transistors. Upper source / drain regions and lower source / drain regions of the transistors are arranged between the trenches. Further insulating structures are arranged in the substrate, which separate upper source / drain regions of transistors adjacent to one another along the trench. The upper source / drain regions of the transi- disturb are connected to the capacitors of the memory cells.
Die Ausstülpungen der Wortleitungen wirken als Gateelektroden der Transistoren.The protuberances of the word lines act as gate electrodes of the transistors.
Das Problem wird ferner gelost durch ein Verfahren zur Herstellung einer DRAM-Zellenanordnung mit Speicherzellen, die jeweils einen Transistor und einen Kondensator aufweisen, bei dem auf einem Substrat eine isolierende Schicht erzeugt wird. Im Substrat werden im wesentlichen parallel zueinander verlaufende Graben erzeugt. Untere Teile der Graben werden bis auf parallel zu den Graben verlaufende, an ersten Flanken der Graben angeordnete streifenfor ige Aussparungen mit einer Isolation versehen. In den unteren Teilen der Graben wird je¬ weils eine Bitleitung erzeugt. Über den unteren Teilen der Graben angeordnete Teile der Flanken der Graben und die Bitleitungen werden mit einer weiteren Isolation versehen. Leitendes Material wird aufgebracht, so daß die Graben gefüllt werden. Es wird eine Schutzschicht erzeugt, die das leitende Material bedeckt. Das leitende Material und die Schutzschicht werden so strukturiert, daß von der Schutzschicht bedeckte Wortleitungen erzeugt werden, die quer zu den Bitleitungen verlaufen und nach unten gerichtete Ausstülpungen aufweisen, die m die Graben reichen. Isolierendes Material wird abgeschieden und zusammen mit der isolierenden Schicht selektiv zur Schutzschicht und zum Substrat ruckgeatzt, bis das Substrat freigelegt wird, so daß m den Graben isolierende Strukturen erzeugt werden, die zwischen den Ausstülpungen der Wortleitungen und über den Bitleitungen angeordnet sind. Das Substrat wird selektiv zu den isolierenden Strukturen geatzt, so daß zwischen den Wortleitungen und zwischen den Graben Vertiefungen erzeugt werden. Zwischen den Graben und zwischer den Vertiefungen werden im Substrat obere Source/Dram- Gebiete von Transistoren von Speicherzellen erzeugt. Unter den oberen Source/Dram-Gebieten werden im Substrat untere Source/Drain-Gebiete der Transistoren erzeugt, die jeweils ar eine der Aussparungen angrenzen. In den Vertiefungen werden weitere isolierende Strukturen erzeugt. Kondensatoren der Speicherzellen werden erzeugt, die jeweils mit einem der obe¬ ren Source/Drain-Gebiete verbunden werden. An den ersten Flanken der Gräben wirken die Wortleitungen als Gateelektroden der Transistoren und die weitere Isolation als Gatedielektrikum.The problem is also solved by a method for producing a DRAM cell arrangement with memory cells, each having a transistor and a capacitor, in which an insulating layer is produced on a substrate. Trenches running essentially parallel to one another are produced in the substrate. Lower parts of the trenches are provided with insulation except for strip-shaped cutouts which run parallel to the trenches and are arranged on first flanks of the trench. In the lower parts of the trench depending ¬ is weils generates a bit line. Parts of the flanks of the trench and the bit lines arranged above the lower parts of the trench are provided with further insulation. Conductive material is applied so that the trenches are filled. A protective layer is created that covers the conductive material. The conductive material and the protective layer are structured in such a way that word lines covered by the protective layer are produced, which run transversely to the bit lines and have downward protrusions that reach the trenches. Insulating material is deposited and, together with the insulating layer, selectively etched back to the protective layer and to the substrate until the substrate is exposed, so that insulating structures are produced in the trench which are arranged between the protuberances of the word lines and above the bit lines. The substrate is selectively etched to the insulating structures so that depressions are created between the word lines and between the trenches. Upper source / dram regions of transistors of memory cells are produced in the substrate between the trenches and between the depressions. Under the upper source / dram regions, lower source / drain regions of the transistors are produced in the substrate, each of which ar adjoin one of the recesses. Further insulating structures are created in the depressions. Capacitors of the memory cells are generated that ren with one of the obe ¬ each source / drain regions are connected. On the first flanks of the trenches, the word lines act as gate electrodes of the transistors and the further insulation acts as a gate dielectric.
Zur Erzeugung der Source/Drain-Gebiete der Transistoren ist keine Epitaxie erforderlich, was eine Prozeßvereinfachung bedeutet .No epitaxy is required to generate the source / drain regions of the transistors, which means a process simplification.
Die oberen Source/Drain-Gebiete, die unteren Source/Drain- Gebiete, die isolierenden Strukturen und die weiteren isolie- renden Strukturen werden selbstjustiert zu den Wortleitungen und zu den Gräben erzeugt, so daß die DRAM-Zellenanordnung eine hohe Packungsdichte, d.h. einen kleinen Platzbedarf pro Speicherzelle, aufweisen kann. Werden die Gräben mit einer streifenförmigen Maske, deren Streifen parallel zueinander verlaufen, erzeugt und die Wortleitungen mit Hilfe einer weiteren streifenförmigen Maske, deren Streifen parallel zueinander und quer zu den Gräben verlaufen, strukturiert und weisen die Streifen eine Breite von F und einen Abstand von F voneinander auf, so kann der Platzbedarf einer Speicherzelle 4 F" betragen, wobei F die minimale, in der verwendeten Technologie herstellbare Strukturgröße ist.The upper source / drain regions, the lower source / drain regions, the insulating structures and the further insulating structures are self-aligned to the word lines and to the trenches, so that the DRAM cell arrangement has a high packing density, ie a small one Space requirement per memory cell can have. If the trenches are produced with a strip-shaped mask, the strips of which run parallel to one another, and the word lines are structured with the aid of a further strip-shaped mask, the strips of which run parallel to one another and transversely to the trenches, and the strips have a width of F and a spacing of F. from each other, the space requirement of a memory cell can be 4 F " , where F is the minimum structure size that can be produced in the technology used.
Zur Vermeidung von Floating-Body-Effekten ist es vorteilhaft, wenn das untere Source/Drain-Gebiet eines Transistors zwi- sehen dem Graben und einem benachbarten Graben angeordnet ist und vom benachbarten Graben beabstandet ist. In diesem Fall ist ein Kanalgebiet des Transistors, das zwischen dem unteren Source/Drain-Gebiet und dem oberen Source/Drain-Gebiet angeordnet ist, mit dem größten Teil des Substrats elektrisch verbunden. Zur Erzeugung eines solchen unteren Source/Dram-Gebiets kann mindestens em Teil der Bitleitung, der an die Aussparung angrenzt, aus dotiertem Polysilizium bestehen. Bei einem Temperschritt diffundiert Dotierstoff aus der Bitleitung ms Substrat und bildet dort e dotiertes Gebiet, das zwischen dem Graben und dem benachbarten Graben angeordnet ist, an die Aussparung angrenzt und vom benachbarten Graben beabstandet ist. Dieser Temperschritt kann z.B. eine thermische Oxidation zur Erzeugung eines Gatedielektrikums sein.To avoid floating body effects, it is advantageous if the lower source / drain region of a transistor is arranged between the trench and an adjacent trench and is spaced apart from the adjacent trench. In this case, a channel region of the transistor, which is arranged between the lower source / drain region and the upper source / drain region, is electrically connected to most of the substrate. To produce such a lower source / dram region, at least one part of the bit line which adjoins the cutout can consist of doped polysilicon. During a tempering step, dopant diffuses out of the bit line ms substrate and forms an e-doped region there, which is arranged between the trench and the adjacent trench, adjoins the recess and is spaced apart from the adjacent trench. This tempering step can be, for example, a thermal oxidation to produce a gate dielectric.
Unter den oberen Source/Dram-Gebieten angeordnete Teile des dotierten Gebiets wirken als die unteren Source/Dram- Gebiete .Parts of the doped region arranged under the upper source / dram regions act as the lower source / dram regions.
Das dotierte Gebiet kann durch die Vertiefungen strukturiert werden, so daß aus dem dotierten Gebiet die unteren Sour- ce/Dram-Gebiete von entlang des Grabens zueinander benachbarten Transistoren erzeugt werden, die getrennt voneinander sind. Die unteren Source/Dram-Gebiete der entlang des Gra- bens zueinander benachbarten Transistoren und die weiteren isolierenden Strukturen grenzen m diesem Fall alternierend im Bereich der Aussparung an die Bitleitung an.The doped region can be structured by the depressions, so that the lower source / dram regions of transistors which are adjacent to one another along the trench and which are separate from one another are produced from the doped region. In this case, the lower source / dram regions of the transistors adjacent to one another along the trench and the further insulating structures alternately adjoin the bit line in the region of the cutout.
Alternativ wird das untere Source/Drain-Gebiet durch Struktu- rierung einer unteren dotierten Schicht des Substrats erzeugt. Die Strukturierung erfolgt durch die Erzeugung der Graben. Um untere Source/Dram-Gebiete der entlang des Grabens zueinander benachbarten Transistoren voneinander zu trennen, können auch m diesem Fall die Vertiefungen so er- zeugt werden, daß sie tiefer als die Aussparungen der Isolation reichen.Alternatively, the lower source / drain region is produced by structuring a lower doped layer of the substrate. The structuring is done by creating the trenches. In order to separate lower source / dram regions of the transistors adjacent to one another along the trench, the depressions can also be produced in this case in such a way that they extend deeper than the cutouts in the insulation.
Das obere Source/Dra -Gebiet kann durch Strukturierung einer oberen dotierten Schicht des Substrats erzeugt werden. Die Strukturierung erfolgt durch die Erzeugung der Vertiefungen und der Graben. Die Vertiefungen sind also mindestens so tief, daß sie die obere dotierte Schicht durchtrennen. Das obere Source/Drain-Gebiet kann auch durch Implantation erzeugt werden. Beispielsweise erfolgt die Implantation nach Erzeugung der Graben. Eine Trennung der oberen Source/Dram- Gebiete von Transistoren, die entlang der Bitleitung zueinan¬ der benachbart sind, voneinander erfolgt durch die Erzeugung der Vertiefungen.The upper source / Dra region can be produced by structuring an upper doped layer of the substrate. The structuring takes place through the creation of the depressions and the trenches. The depressions are therefore at least so deep that they cut through the upper doped layer. The upper source / drain region can also be created by implantation. For example, the implantation takes place after the trenches have been created. A separation of the upper source / dram regions of transistors which are adjacent along the bit line of the zueinan ¬ takes place from one another by the production of the wells.
Die Verbindung des Kondensators mit dem oberen Source/Dram- Gebiet kann über eine leitende Struktur erfolgen. Dazu ist das obere Source/Drain-Gebiet des Transistors mit einer isolierenden Schicht bedeckt. Die Wortleitung verlauft über der isolierenden Schicht. Eine Projektion des oberen Sour- ce/Dram-Gebiets auf die isolierende Schicht überlappt eine Projektion der Wortleitung auf die isolierende Schicht der¬ art, daß sie jenseits zweier Seiten der Projektion der Wortleitung ausgedehnt ist, so daß Projektionen zweier Teile des oberen Source/Dram-Gebiets an die Projektion der Wortleitung angrenzen und die Projektion der Wortleitung nicht uberlap- pen. Quer zur Wortleitung weist folglich das obere Sour- ce/Dram-Gebiet eine größere Abmessung auf als die Wortleitung. Flanken der Wortleitung sind mit isolierenden Spacern versehen. Eine obere, dem oberen Source/Dram-Gebiet abgewandte Oberflache der Wortleitung ist mit einer isolierenden Schutzschicht versehen. Die leitende Struktur bedeckt dieThe capacitor can be connected to the upper source / dram region via a conductive structure. For this purpose, the upper source / drain region of the transistor is covered with an insulating layer. The word line runs over the insulating layer. A projection of the upper source / dram region on the insulating layer overlaps a projection of the word line on the insulating layer of the ¬ art that it is extended beyond two sides of the projection of the word line, so that projections of two parts of the upper source / dram -Limit the area around the projection of the word line and do not overlap the projection of the word line. Transversely to the word line, the upper source / dram area therefore has a larger dimension than the word line. Flanks of the word line are provided with insulating spacers. An upper surface of the word line facing away from the upper source / dram region is provided with an insulating protective layer. The conductive structure covers that
Schutzschicht und die Spacer und überlappt die zwei Teile des Source/Dram-Gebiets. Der Kondensator ist auf der leitenden Struktur angeordnet.Protective layer and the spacer and overlaps the two parts of the source / dram area. The capacitor is arranged on the conductive structure.
Die leitende Struktur kann selbstjustiert bezüglich der Wortleitung erzeugt werden und vergrößert den Platzbedarf der Speicherzelle nicht. Die Spacer werden beispielsweise vor Erzeugung der Vertiefungen durch Abscheiden und Ruckatzen von isolierendem Material erzeugt. Nach Erzeugung der lsolieren- den Strukturen wird leitendes Material m einer solchen Dicke abgeschieden, daß Zwischenräume zwischen den Wortleitungen nicht aufgef llt werden. Eine Maske wird erzeugt, die hon- zontale Oberflachen von Teilen des leitenden Materials, die oberhalb der Wortleitung angeordnet sind, bedeckt. Das lei¬ tende Material und das Substrat werden selektiv zur Maske ge¬ atzt. Zwischen den Wortleitungen angeordnete Teile des lei- tenden Materials werden folglich entfernt. Dabei entstehen aus dem leitenden Material die leitenden Strukturen, und im Substrat werden die Vertiefungen erzeugt.The conductive structure can be generated in a self-aligned manner with respect to the word line and does not increase the space requirement of the memory cell. The spacers are produced, for example, before the depressions are produced by separating and scratching off insulating material. After the insulating structures have been produced, conductive material is deposited to such a thickness that gaps between the word lines are not filled. A mask is created that honors zonal surfaces of parts of the conductive material, which are arranged above the word line, covered. The lei ¬ tend material and the substrate are selectively etched to mask ge ¬. Parts of the conductive material arranged between the word lines are consequently removed. The conductive structures are created from the conductive material and the depressions are created in the substrate.
Die Maske kann selbstjustiert erzeugt werden, so daß der Platzbedarf der Speicherzelle nicht vergrößert wird.The mask can be generated in a self-adjusted manner so that the space requirement of the memory cell is not increased.
Eine Möglichkeit, die Maske zu erzeugen, besteht darin, isolierendes Material nicht konform abzuscheiden, so daß das isolierende Material über den horizontalen Oberflachen der Teile des leitenden Materials, die oberhalb der Wortleitung angeordnet sind, am dicksten ist. Die Maske wird aus dem isolierenden Material erzeugt, indem das isolierende Material ruckgeatzt wird, bis zwischen den Wortleitungen angeordnete Teile des leitenden Materials freigelegt werden. In diesem Fall bedeckt die Maske neben den horizontalen Oberflachen der Teile des leitenden Materials, die oberhalb der Wortleitung angeordnet sind, auch quer dazu verlaufende Flachen des leitenden Materials.One way to create the mask is to non-conformally deposit insulating material so that the insulating material is thickest over the horizontal surfaces of the portions of conductive material located above the word line. The mask is produced from the insulating material by etching back the insulating material until parts of the conductive material arranged between the word lines are exposed. In this case, the mask covers not only the horizontal surfaces of the parts of the conductive material which are arranged above the word line, but also transverse surfaces of the conductive material.
Eine weitere Möglichkeit, die Maske zu erzeugen, besteht darin, zunächst nach Abscheiden des leitenden Materials, das dotiertes Polysilizium enthalt, em Hilfsmaterial abzuscheiden und ruckzuatzen, bis seitliche Flachen des leitenden Materials teilweise freigelegt werden. Anschließend wird eine ther- mische Oxidation durchgeführt, so daß die Maske auf freiliegenden Teilen des leitenden Materials erzeugt wird. Anschließend wird das Hilfsmaterial entfernt.A further possibility of producing the mask consists in first depositing and etching back the auxiliary material after the conductive material containing the doped polysilicon has been deposited, until lateral faces of the conductive material are partially exposed. A thermal oxidation is then carried out so that the mask is produced on exposed parts of the conductive material. The auxiliary material is then removed.
Zur Erhöhung der elektrischen Leitfähigkeit der Bitleitung, kann diese teilweise aus Metall bestehen. Neben Molybdän oαer Tantal ist Wolfram besonders geeignet, wenn das Substrat aus Silizium besteht, da Silizium und Wolfram naherungsweise die- selben thermischen Ausdehnungskoeffizienten aufweisen, so daß mechanische Verspannungen und daraus resultierende Defekte bei Temperaturveranderungen vermieden werden.To increase the electrical conductivity of the bit line, it can partially consist of metal. In addition to molybdenum or tantalum, tungsten is particularly suitable if the substrate consists of silicon, since silicon and tungsten approximate- have the same thermal expansion coefficient, so that mechanical tension and resulting defects in temperature changes are avoided.
Um zu verhindern, daß aus dem Metall der Bitleitung und dem Silizium des Substrats oder, falls vorgesehen, dem Polysili- zium der Bitleitung em Metallsilizid, das eine kleinere elektrische Leitfähigkeit aufweist, aufgrund von Diffusion gebildet wird, ist es vorteilhaft, zwischen dem Metall und dem Silizium bzw. dem Polysiliziu eine Diffusionsbarπere vorzusehen. Beispielsweise besteht em unterer Teil der Bitleitung aus Metall. Darüber ist eine Diffusionsbarπere angeordnet, die Stickstoff enthalt. Auf der Diffusionsbarπere ist das Polysilizium angeordnet, das an die Aussparung an- grenzt.In order to prevent the metal of the bit line and the silicon of the substrate or, if provided, the polysilicon of the bit line from forming a metal silicide, which has a lower electrical conductivity, due to diffusion, it is advantageous to separate between the metal and to provide the silicon or the polysilicon with a diffusion barrier. For example, a lower part of the bit line consists of metal. A diffusion bar containing nitrogen is arranged above it. The polysilicon, which adjoins the cutout, is arranged on the diffusion bar.
Zur Vermeidung von Leckstromen aufgrund von hohen elektrischen Feldern an Kanten der Wortleitungen ist es vorteilhaft, nach Erzeugung der Wortleitungen eine thermische Oxidation durchzufuhren, so daß die von den Wortleitungen bedecktenIn order to avoid leakage currents due to high electrical fields at the edges of the word lines, it is advantageous to carry out a thermal oxidation after the word lines have been generated, so that those covered by the word lines
Teile der weiteren Isolationen an den Kanten der Wortleitungen verdickt werden.Parts of the further insulation are thickened at the edges of the word lines.
Zur Erhöhung der elektrischen Leitfähigkeit der Wortleitungen können die Wortleitungen aus zwei Teilen bestehen. Em unterer Teil der Wortleitungen, der die Ausstülpungen umfaßt, besteht vorzugsweise aus dotiertem Polysilizium. Die über den ersten Teilen angeordneten zweiten Teile der Wortleitungen können z. B. aus einem Metallsilizid, wie Wolframsilizid, be- stehen. Die Wortleitungen können auch aus dotiertem Polysilizium, aus einer darüber angeordneten, z.B. stickstoffhaltigen, Diffusionsbamere und aus darüber angeordnetem Metall, z.B. Wolfram, bestehen.To increase the electrical conductivity of the word lines, the word lines can consist of two parts. A lower part of the word lines, which comprises the protuberances, is preferably made of doped polysilicon. The second parts of the word lines arranged above the first parts can e.g. B. consist of a metal silicide, such as tungsten silicide. The word lines can also be made of doped polysilicon, from one arranged above, e.g. nitrogenous, diffusion bamers and from metal arranged above, e.g. Tungsten.
Die isolierende Schicht, die Isolation, die weitere Isolation, die isolierenden Strukturen, die weiteren isolierenden Strukturen und die Maske bestehen beispielsweise aus S1O2 oder aus Siliziumnitπd. Andere isolierende Materialien lie¬ gen jedoch auch im Rahmen der Erfindung.The insulating layer, the isolation, the further isolation, the isolating structures, the further isolating structures and the mask consist for example of S1O2 or from silicon nitride. However, other insulating materials lie ¬ gen in the context of the invention.
Dasselbe gilt für die Schutzschicht und die Spacer. Besteht die isolierende Schicht beispielsweise aus S1O2, so besteht die Schutzschicht vorzugsweise aus Siliziumnitrid, um selek¬ tives Atzen zu ermöglichen.The same applies to the protective layer and the spacers. Is the insulating layer, for example, S1O2, so the protective layer is preferably made of silicon nitride, to allow tive to selec ¬ etching.
Das Substrat kann statt aus Silizium aus einem anderen Mate- rial bestehen, das für Transistoren geeignet ist. Beispiels¬ weise kann das Substrat GaAs enthalten.Instead of silicon, the substrate can consist of another material that is suitable for transistors. Example ¬, the substrate may include GaAs.
Im folgenden wird em Ausfuhrungsbeispiel der Erfindung anhand der Figuren naher erläutert.In the following, an exemplary embodiment of the invention is explained in more detail with reference to the figures.
Figur 1 zeigt einen Querschnitt durch e Substrat, nachdem eine erste isolierende Schicht, eine Schicht aus Siliziumnitrid, eine zweite isolierende Schicht, Graben und eine Isolation erzeugt wurden.FIG. 1 shows a cross section through a substrate after a first insulating layer, a layer of silicon nitride, a second insulating layer, trench and isolation have been produced.
Figur 2 zeigt den Querschnitt aus Figur 1, nachdem Bitleitungen und erste dotierte Gebiete erzeugt wurden.FIG. 2 shows the cross section from FIG. 1 after bit lines and first doped regions have been produced.
Figur 3a zeigt den Querschnitt aus Figur 2, nachdem eine wei- tere Isolation, zweite dotierte Gebiete, Wortleitungen, eine Schutzschicht und Spacer erzeugt wurden.FIG. 3a shows the cross section from FIG. 2 after a further insulation, second doped regions, word lines, a protective layer and spacers have been produced.
Figur 3b zeigt einen zum Querschnitt aus Figur 3a parallelen Querschnitt durch das Substrat nach den Prozeß- schritten aus Figur 3a.FIG. 3b shows a cross section through the substrate parallel to the cross section from FIG. 3a after the process steps from FIG. 3a.
Figur 3c zeigt einen zum Querschnitt aus Figur 3a senkrechten Querschnitt durch das Substrat nach den Prozeßschritten aus Figur 3a. Figur 3d zeigt einen zum Querschnitt aus Figur 3c parallelen Querschnitt durch das Substrat nach den Proze߬ schritten aus Figur 3a.FIG. 3c shows a cross section perpendicular to the cross section from FIG. 3a through the substrate after the process steps from FIG. 3a. 3d shows a parallel to the cross section of Figure 3c cross-section through the substrate after the process ¬ steps of Figure 3a.
Figur 3e zeigt eine Aufsicht auf das Substrat, m der die er¬ ste isolierende Schicht, die Bitleitungen, die Iso¬ lation, die weitere Isolation, die Wortleitungen und die Spacer dargestellt sind.Figure 3e shows a top view of the substrate m of he ¬ ste insulating layer, the bit lines, the iso ¬ lation, the further insulation, the word lines and the spacers are illustrated.
Figur 4a zeigt den Querschnitt aus Figur 3a, nachdem isolierende Strukturen, eine Maske, Vertiefungen, leitende Strukturen, weitere isolierende Strukturen, obere Source/Dram-Gebiete, Kanalgebiete und untere Source/Dram-Gebiete erzeugt wurden.FIG. 4a shows the cross section from FIG. 3a after insulating structures, a mask, depressions, conductive structures, further insulating structures, upper source / dram regions, channel regions and lower source / dram regions have been produced.
Figur 4b zeigt den Querschnitt aus Figur 3b nach den Prozeßschritten aus Figur 4a.FIG. 4b shows the cross section from FIG. 3b after the process steps from FIG. 4a.
Figur 4c zeigt den Querschnitt aus Figur 3c nach den Prozeß- schritten aus Figur 4a.FIG. 4c shows the cross section from FIG. 3c after the process steps from FIG. 4a.
Figur 4d zeigt den Querschnitt aus Figur 3d nach den Proze߬ schritten aus Figur 4a.Figure 4d shows the cross section of Figure 3d after the process ¬ steps of Figure 4a.
Figur 5 zeigt den Querschnitt aus Figur 4d, nachdem Speicherknoten, leitende Spacer und eine Kondensatorplatte erzeugt wurden.FIG. 5 shows the cross section from FIG. 4d after storage nodes, conductive spacers and a capacitor plate have been produced.
Die Figuren sind nicht maßstabsgerecht.The figures are not to scale.
Im Ausfuhrungsbeispiel ist em Substrat 1 aus monokπstalli- ne Silizium vorgesehen.In the exemplary embodiment, a substrate 1 made of monolithic silicon is provided.
Auf einer Oberflache des Substrats 1 wird S1O2 in einer Dicke von ca. 20nm abgeschieden, so daß eine erste isolierendeS1O2 is deposited in a thickness of approximately 20 nm on a surface of the substrate 1, so that a first insulating one
Schicht II erzeugt wird. Zur Erzeugung einer Schicht aus Si- liziumnitrid N wird Siliziumnitπd m einer Dicke von ca. 50nm abgeschieden. Zur Erzeugung einer zweiten isolierenden Schicht 12 wird Sι0 m einer Dicke von ca. 200nm abgeschie¬ den (siehe Figur 1) .Layer II is generated. To produce a layer of silicon nitride N, silicon nitride with a thickness of approx. 50nm deposited. To produce a second insulating layer 12 is Sι0 m a thickness of approximately 200 nm abgeschie ¬ (see Figure 1).
Mit Hilfe einer streifenförmigen ersten Fotolackmaske, deren Streifen ca. lOOnm breit sind und einen Abstand von ca. lOOnm voneinander aufweisen, werden die zweite isolierende Schicht 12, die Schicht aus Siliziumnitrid N und die erste isolieren¬ de Schicht II strukturiert, so daß das Substrat 1 teilweise freigelegt wird. Anschließend wird die erste Fotolackmaske entfernt. Mit z. B. HBr wird das Substrat 1 ca. 500nm tief geatzt, so daß Graben G erzeugt werden (siehe Figur 1). Die strukturierte zweite isolierende Schicht 12 wirkt dabei als Maske .With the aid of a strip-shaped first photoresist mask whose strips are approximately lOOnm wide and have a spacing of approximately lOOnm from each other, the second insulating layer 12, the layer of silicon nitride N and the first isolate ¬ de layer II are patterned, so that the substrate 1 is partially exposed. The first photoresist mask is then removed. With z. B. HBr, the substrate 1 is etched approximately 500 nm deep, so that trenches G are produced (see FIG. 1). The structured second insulating layer 12 acts as a mask.
Zur Erzeugung einer ca. 10 nm dicken Isolation 13 wird eine thermische Oxidation durchgeführt. Die Isolation 13 bedeckt Flanken und Boden der Graben G (siehe Figur 1) .Thermal oxidation is carried out in order to produce an insulation 13 which is approximately 10 nm thick. The insulation 13 covers the flanks and the bottom of the trench G (see FIG. 1).
Anschließend wird msitu dotiertes Polysilizium m einer Dik- ke von ca. 50nm abgeschieden. Es wird chemisch-mechanisch poliert, bis die zweite isolierende Schicht 12 entfernt wird. Anschließend w rd das Polysilizium ca. 400nm tief ruckgeatzt.Subsequently, msitu doped polysilicon is deposited with a thickness of approx. 50 nm. It is polished mechanically and mechanically until the second insulating layer 12 is removed. Then the polysilicon is etched back to a depth of approx. 400 nm.
Mit Hilfe einer streifenförmigen zweiten Fotolackmaske (nicht dargestellt) , deren Streifen erste Flanken der Graben G nicht bedecken, werden freiliegende Teile der Isolation 13 entfernt (siehe Figur 2). Als Atzmittel ist beispielsweise HF geeignet. Die Schicht aus Siliziumnitrid N schützt Teile der er- sten isolierenden Schicht II.With the aid of a strip-shaped second photoresist mask (not shown), the strips of which do not cover the first flanks of the trench G, exposed parts of the insulation 13 are removed (see FIG. 2). HF is suitable as an etchant, for example. The layer of silicon nitride N protects parts of the first insulating layer II.
Anschließend wird weiteres msitu dotiertes Polysilizium m einer Dicke von ca. 50 nm abgeschieden und durch chemischmechanisches Polieren zuruckgeschliffen bis die Schicht aus Siliziumnitrid N freigelegt wird. Durch eine Implantation mit n-dotierenden Ionen werden im Substrat 1 streifenformige erste dotierte Gebiete Dl erzeugt, die zwischen den Graben G angeordnet sind und an die Oberfla¬ che des Substrats 1 angrenzen (siehe Figur 2) . Die ersten do- tierten Gebiete Dl sind ca. 20nm dick.Subsequently, further msitu-doped polysilicon is deposited in a thickness of approx. 50 nm and ground back by chemical mechanical polishing until the layer made of silicon nitride N is exposed. By implantation with n-doping ions 1 Dl strip-shaped first doped regions in the substrate are generated, which are located between the trench and the G SURFACE ¬ surface of the substrate 1 are adjacent (see Figure 2). The first doped areas Dl are approx. 20nm thick.
Anschließend wird das Polysilizium ca. 330nm tief ruckgeatzt. Das dotierte Polysilizium in den Graben G bildet Bitleitungen B, die m unteren Teilen der Graben G angeordnet sind. Die Isolation 13 weist m den unteren Teilen der Graben G jeweils eine streifenformige Aussparung an der ersten Flanke auf, bei der die Bitleitung B an das Substrat 1 angrenzt (siehe Figur 2) .Then the polysilicon is etched back to a depth of approx. 330 nm. The doped polysilicon in the trench G forms bit lines B, which are arranged in the lower parts of the trench G. The insulation 13 in the lower parts of the trenches G each has a strip-shaped recess on the first flank, in which the bit line B adjoins the substrate 1 (see FIG. 2).
Zur Entfernung von Atzruckstanden wird eine thermische Oxidation durchgeführt, und das dadurch erzeugte S1O2 anschließend durch nasses Atzen entfernt. Die Schicht aus Siliziumnitrid N wird entfernt.Thermal oxidation is carried out to remove etching residues, and the S1O2 produced in this way is subsequently removed by wet etching. The layer of silicon nitride N is removed.
Zur Erzeugung einer weiteren Isolation 14 wird eine thermische Oxidation durchgeführt. Die weitere Isolation 14 ist ca. 5nm dick und bedeckt über den unteren Teilen der Graben G angeordnete Teile der Flanken der Graben G und obere Flachen der Bitleitungen B (siehe Figuren 3a bis 3e) . Die thermische Oxidation wirkt als Temperschritt, durch den Dotierstoff aus der Bitleitung B m das Substrat 1 diffundiert und dort zweite dotierte Gebiete D2 bildet (siehe Figuren 3a, 3b) . Jedes der zweiten dotierten Gebiete D2 grenzt an jenen Graben G an, m dem jene Bitleitung angeordnet ist, aus der der Dotier- stoff, mit dem das zweite dotierte Gebiet D2 erzeugt wurde, diffundiert ist. Das zweite dotierte Gebiet D2 ist zwischen diesem Graben und einem benachbarten Graben angeordnet, grenzt an die Aussparung des Grabens G an und ist vom benachbarten Graben beabstandet.Thermal oxidation is carried out to produce a further insulation 14. The further insulation 14 is approximately 5 nm thick and covers parts of the flanks of the trenches G and upper surfaces of the bit lines B arranged above the lower parts of the trench G (see FIGS. 3a to 3e). The thermal oxidation acts as a tempering step through which the dopant diffuses from the bit line B m into the substrate 1 and forms second doped regions D2 there (see FIGS. 3a, 3b). Each of the second doped regions D2 adjoins that trench G in which the bit line from which the dopant with which the second doped region D2 was produced is diffused. The second doped region D2 is arranged between this trench and an adjacent trench, adjoins the recess of the trench G and is spaced apart from the adjacent trench.
Anschließend wird msitu dotiertes Polysilizium einer Dik- ke von ca. 50 nm abgeschieden, so daß die Graben G gefüllt werden. Darüber wird Wolframsilizid m einer Dicke von ca. 80nm abgeschieden. Zur Erzeugung einer Schutzschicht S wird Siliziumnitrid in einer Dicke von ca. 50nm abgeschieden (sie¬ he Figuren 3a bis 3d) .Subsequently, msitu doped polysilicon with a thickness of approx. 50 nm is deposited, so that the trenches G are filled become. Tungsten silicide is deposited in a thickness of approx. 80 nm. In order to produce a protective layer S silicon nitride is deposited to a thickness of approximately 50 nm (they ¬ he figures 3a to 3d).
Mit Hilfe einer streifenförmigen dritten Fotolackmaske (nicht dargestellt) , deren Streifen quer zu den Streifen der ersten Fotolackmaske verlaufen, ca. lOOnm breit sind, und einen Ab¬ stand von ca. lOOnm voneinander aufweisen, wird Siliziumni- trid, Wolframsilizid und Polysilizium geatzt, bis auf den Bitleitungen B angeordnete Teile der weiteren Isolation 14 freigelegt werden. Aus dem Polysilizium und dem Wolframsilizid entstehen dadurch quer zu den Bitleitungen B verlaufende Wortleitungen W, die nach unten gerichtete Ausstülpungen auf- weisen, welche m die Graben G reichen (siehe Figuren 3a bis 3e) .With the aid of a strip-shaped third photoresist mask (not shown), whose strips run transversely to the strips of the first photoresist mask having, ca. are lOOnm wide, and a From ¬ stand of approximately lOOnm of one another, Siliziumni- is nitride, tungsten silicide and polysilicon etched, parts of the further insulation 14 arranged on the bit lines B are exposed. The polysilicon and the tungsten silicide thus result in word lines W which run transversely to the bit lines B and have downward protrusions which reach the trenches G (see FIGS. 3a to 3e).
Die dritte Fotolackmaske wird entfernt. Zur Verkleinerung von Leckstromen wird eine thermische Oxidation durchgeführt, so daß die weitere Isolation 14 abschnittsweise bis unter die Wortleitungen W verdickt werden. Im Bereich von Kanten der Wortleitungen W ist die weitere Isolation 14 also verdickt. Diese thermische Oxidation entspricht dem sogenannten Reoxi- dationsschritt bei planaren Transistoren.The third photoresist mask is removed. In order to reduce leakage currents, thermal oxidation is carried out so that the further insulation 14 is thickened in sections up to below the word lines W. The further insulation 14 is therefore thickened in the region of edges of the word lines W. This thermal oxidation corresponds to the so-called reoxidation step in planar transistors.
Zur Erzeugung von isolierenden Spacern Sp wird Siliziumnitrid m einer Dicke von ca. 10 nm abgeschieden und ruckgeatzt (siehe Figuren 3a bis 3e) . Die Spacer Sp bedecken Flanken der Wortleitungen W sowie Teile der Isolation 13 und der weiteren Isolation 14.To produce insulating spacers Sp, silicon nitride is deposited to a thickness of approximately 10 nm and is etched back (see FIGS. 3a to 3e). The spacers Sp cover flanks of the word lines W and parts of the insulation 13 and the further insulation 14.
Anschließend wird S1O2 m einer Dicke von ca. 50nm abgeschieden und chemisch-mechanisch poliert, bis die Schutzschicht S freigelegt wird. Anschließend wird das S1O2 ruckgeatzt, bis das Substrat 1 freigelegt wird. In den Graben werden dadurch isolierende Strukturen 15 erzeugt, so daß jedem Graben G über der zugehörigen Bitleitung B alternierend die Ausstülpungen der Wortleitungen W und die isolierenden Strukturen 15 angeordnet sind (siehe Figuren 4a bis 4d) .Subsequently, S1O2 is deposited with a thickness of approx. 50 nm and chemically and mechanically polished until the protective layer S is exposed. The S1O2 is then etched back until the substrate 1 is exposed. This creates insulating structures 15 in the trench, so that the trenches of the word lines W and the insulating structures 15 are arranged alternately in each trench G above the associated bit line B (see FIGS. 4a to 4d).
Anschließend wird msitu dotiertes Polysilizium m einer Dik- ke von ca. lOnm abgeschieden. Die Dicke ist so gering, daß Zwischenräume zwischen den Wortleitungen W nicht ausgefüllt werden.Subsequently, msitu doped polysilicon is deposited with a thickness of approximately 10 nm. The thickness is so small that gaps between the word lines W are not filled.
Mit Hilfe einer streifenförmigen vierten Fotolackmaske (nicht dargestellt) , die der ersten Fotolackmaske entspricht, wird Polysilizium über den Graben G entfernt.With the help of a strip-like fourth photoresist mask (not shown), which corresponds to the first photoresist mask, polysilicon is removed via the trench G.
Die vierte Fotolackmaske wird entfernt. Zur Erzeugung einer Maske M wird S1O2 m einem CVD-Verfahren mit hoher Rate abgeschieden, so daß das S1O2 auf über den horizontalen Oberflachen der Teile des Polysiliziums, die oberhalb der Wortleitungen W angeordnet sind, etwa doppelt so dick, nämlich ca. 20nm, aufwachst, im Vergleich zu weiter unter liegenden Stel- len.The fourth photoresist mask is removed. To produce a mask M, S1O2 m is deposited at a high rate using a CVD method, so that the S1O2 grows on the horizontal surfaces of the parts of the polysilicon which are arranged above the word lines W about twice as thick, namely about 20 nm , compared to lower positions.
Anschließend wird das S1O2 ca. lOn tief geatzt, so daß zwischen den Wortleitungen W angeordnete Teile des Polysiliziums freigelegt werden. Aus dem S1O2 wird dadurch die Maske M er- zeugt (siehe Figuren 4a bis 4d) .The S1O2 is then etched to a depth of approximately 10 nm, so that parts of the polysilicon arranged between the word lines W are exposed. The mask M is thereby generated from the S1O2 (see FIGS. 4a to 4d).
Mit z. B. HBr wird das Polysilizium und das Substrat 1 selektiv zur Maske M und den isolierenden Strukturen 15 geatzt, so daß zwischen den Wortleitungen W und zwar zwischen den Graben G Vertiefungen V erzeugt werden (siehe Figuren 4b und 4d) .With z. B. HBr, the polysilicon and the substrate 1 are selectively etched to the mask M and the insulating structures 15, so that depressions V are produced between the word lines W and specifically between the trenches G (see FIGS. 4b and 4d).
Die Vertiefungen V sind ca. 450nm tief, so daß sie tiefer als die Aussparungen der Isolation 13 reichen.The depressions V are approximately 450 nm deep, so that they extend deeper than the cutouts in the insulation 13.
Durch die Vertiefungen V werden aus den ersten dotierten Ge- bieten Dl obere Source/Dram-Gebiete S/Do von Transistoren erzeugt. Des weiteren werden aus dem Polysilizium leitende Strukturen L erzeugt, die mit den oberen Source/Dram- Gebieten S/Do verbunden sind. Aufgrund des vorigen Atzschrit¬ tes mit der vierten Fotolackmaske sind die leitenden Struktu¬ ren L, die entlang der Wortleitung W zueinander benachbart sind, voneinander getrennt. Durch die Vertiefungen V werden ferner aus den zweiten dotierten Gebieten D2 untere Source/Dram-Gebiete S/Du der Transistoren erzeugt (siehe Figuren 4a und 4d) . An den ersten Flanken der Graben wirken die Wortleitungen als Gateelektroden der Transistoren und die weitere Isolation als Gatedielektπkum. Teile des Substrats 1, die zwischen dem oberen Source/Drain-Gebiet S/Do und dem unteren Source/Drain-Gebiet S/Du jedes Transistors angeordnet sind, wirken als Kanalgebiete Ka der Transistoren.Through the depressions V, upper source / dram regions S / Do of transistors are generated from the first doped regions D1. Furthermore, conductive structures L are produced from the polysilicon, which structures are connected to the upper source / dram S / Th areas are connected. Due to the previous Atzschrit ¬ tes with the fourth photoresist mask, the conductive struc ¬ ren L that are adjacent along the word line W to each other, separated from each other. The recesses V also produce lower source / dram regions S / Du of the transistors from the second doped regions D2 (see FIGS. 4a and 4d). On the first flanks of the trenches, the word lines act as gate electrodes of the transistors and the further insulation acts as a gate dielectric. Parts of the substrate 1, which are arranged between the upper source / drain region S / Do and the lower source / drain region S / Du of each transistor, act as channel regions Ka of the transistors.
Anschließend wird S1O2 m einer Dicke von ca. lOOnm abge- schieden und durch chemisch-mechanisches Polieren planari- siert. In den Vertiefungen V werden dadurch weitere isolierende Strukturen 16 erzeugt (siehe Figuren 4b und 4d) .Then S1O2 is deposited to a thickness of approx. 100 nm and planarized by chemical-mechanical polishing. This creates additional insulating structures 16 in the depressions V (see FIGS. 4b and 4d).
Durch em photolithographisches Verfahren werden die leiten- den Strukturen L freigelegt (siehe Figur 5) . Anschließend wird msitu dotiertes Polysilizium m einer Dicke von ca. 500nm abgeschieden. Darüber wird Wolframsilizid m einer Dik- ke von ca. lOOnm abgeschieden. Durch em photolithographi- sches Verfahren werden aus dem Wolframsilizid und dem Polysi- lizium Speicherknoten K von Kondensatoren erzeugt, die mit den leitenden Strukturen L verbunden sind (siehe Figur 5).The conductive structures L are exposed by means of a photolithographic process (see FIG. 5). Then msitu doped polysilicon is deposited with a thickness of approx. 500 nm. Tungsten silicide is deposited in a thickness of approx. 100 nm. By means of a photolithographic method, storage nodes K of capacitors are produced from the tungsten silicide and the polysilicon, which are connected to the conductive structures L (see FIG. 5).
Eine Oberflache der Speicherknoten K wird durch leitende Spacern Sp vergrößert, die durch Abscheiden von Wolframsili- zid m einer Dicke von ca. 20nm und anschließendem Ruckatzen erzeugt werden. Zur Erzeugung eines Kondensatordielektrikums KD wird Siliziumnitrid m einer Dicke von ca. 6nm abgeschieden und ca. lnm tief aufoxidiert. Zur Erzeugung einer für die Kondensatoren gemeinsamen Kondensatorplatte P wird Titanni- trid m einer Dicke von ca. lOOnm abgeschieden (siehe Figur 5) . Im Ausführungsbeispiel wird eine DRAM-Zellenanordnung erzeugt, mit Speicherzellen, die jeweils einen der Transistoren und einen damit verbundenen der Kondensatoren umfassen.A surface of the storage nodes K is enlarged by conductive spacers Sp, which are produced by depositing tungsten silicide in a thickness of approximately 20 nm and then scratching it back. In order to produce a capacitor dielectric KD, silicon nitride is deposited to a thickness of approximately 6 nm and oxidized to a depth of approximately 1 nm. To produce a capacitor plate P common to the capacitors, titanium nitride is deposited in a thickness of approximately 100 nm (see FIG. 5). In the exemplary embodiment, a DRAM cell arrangement is produced, with memory cells, each of which comprises one of the transistors and one of the capacitors connected to them.
Es sind viele Variationen des Ausführungsbeispiels denkbar, die ebenfalls im Rahmen der Erfindung liegen. So können Abmessungen der Schichten, Gräben, Strukturen, Vertiefungen und Gebiete an die jeweiligen Erfordernisse angepaßt werden. Dasselbe gilt für die Wahl von Materialien. Many variations of the exemplary embodiment are conceivable, which are also within the scope of the invention. Dimensions of the layers, trenches, structures, depressions and areas can be adapted to the respective requirements. The same applies to the choice of materials.

Claims

Patentansprüche claims
1. DRAM-Zellenanordnung1. DRAM cell arrangement
- mit Speicherzellen, die jeweils einen vertikalen Transistor und einen Kondensator aufweisen,with memory cells, each having a vertical transistor and a capacitor,
- bei der em Substrat (1) im wesentlichen parallel zueinan¬ der verlaufende Graben (G) aufweist, m denen jeweils eine Bitleitung (B) angeordnet ist,- substantially zueinan ¬ has em in the substrate (1) parallel to the extending trench (G), m each of which a bit line (B) is disposed,
- bei der die Bitleitung (B) m einem unteren Teil des zuge- hörigen Grabens (G) angeordnet ist,in which the bit line (B) is arranged in a lower part of the associated trench (G),
- bei der der untere Teil des Grabens (G) bis auf eine parallel zum Graben (G) verlaufende, an einer ersten Flanke des Grabens (G) angeordnete, streifenformige Aussparung mit einer Isolation (13) , die zwischen der Bitleitung (B) und dem Substrat (1) angeordnet ist, versehen ist,- In which the lower part of the trench (G) except for a parallel to the trench (G), on a first flank of the trench (G) arranged, strip-shaped recess with an insulation (13) between the bit line (B) and the substrate (1) is provided,
- bei der über dem unteren Teil des Grabens (G) angeordnete Teile der Flanken des Grabens (G) und eine obere Flache der Bitleitung (B) mit einer weiteren Isolation (14) versehen sind, - bei der Wortleitungen (W) quer zur Bitleitung (B) verlaufen,- In which arranged over the lower part of the trench (G) parts of the flanks of the trench (G) and an upper surface of the bit line (B) are provided with further insulation (14), - in the word lines (W) transverse to the bit line (B) run,
- bei der die Wortleitungen (W) bis auf nach unten gerichtete Ausstülpungen, die m die Graben (G) reichen und über den Bitleitungen (B) angeordnet sind, über dem Substrat (1) verlaufen und vom Substrat (1) durch eine isolierende Schicht (II) getrennt sind,- In which the word lines (W) except for downward protuberances, which reach the trenches (G) and are arranged above the bit lines (B), run above the substrate (1) and from the substrate (1) through an insulating layer (II) are separated,
- bei der über der Bitleitung (B) im Graben (G) alternierend Ausstülpungen der Wortleitungen (W) und isolierende Strukturen (15) angeordnet sind, - bei der obere Source/Dra -Gebiete (S/Do) und untere Source/Dram-Gebiete (S/Du) der Transistoren zwischen den Graben (G) und unter den Wortleitungen (W) angeordnet sind,- in which alternate protuberances of the word lines (W) and insulating structures (15) are arranged above the bit line (B) in the trench (G), - in the upper source / drain regions (S / Do) and lower source / dram Regions (S / Du) of the transistors are arranged between the trench (G) and under the word lines (W),
- bei der im Substrat (1) weitere isolierende Strukturen (16) angeordnet sind, die obere Source/Dram-Gebiete (S/Do) von entlang des Grabens (G) zueinander benachbarten Transistoren voneinander trennen, - bei der die oberen Source/Dram-Gebiete (S/Do) der Transi¬ storen mit den Kondensatoren der Speicherzellen verbunden sind.in which further insulating structures (16) are arranged in the substrate (1) and separate the upper source / dram regions (S / Do) of transistors adjacent to one another along the trench (G), - wherein the upper source / dram regions (S / Do) of Transi ¬ interfere with the capacitors of the memory cells are connected.
2. DRAM-Zellenanordnung nach Anspruch 1,2. DRAM cell arrangement according to claim 1,
- bei der das untere Source/Drain-Gebiet (S/Du) des Transistors zwischen dem Graben (G) und einem benachbarten Graben (G) angeordnet ist und vom benachbarten Graben (G) beabstandet ist.- In which the lower source / drain region (S / Du) of the transistor between the trench (G) and an adjacent trench (G) is arranged and spaced from the adjacent trench (G).
3. DRAM-Zellenanordnung nach einem der Ansprüche 1 oder 2,3. DRAM cell arrangement according to one of claims 1 or 2,
- bei der das obere Source/Drain-Gebiet (S/Do) des Transistors einer der Speicherzellen mit der isolierenden Schicht (II) bedeckt ist, - bei der die Wortleitung (W) über der isolierenden Schicht (II) verlauft,- in which the upper source / drain region (S / Do) of the transistor of one of the memory cells is covered with the insulating layer (II), - in which the word line (W) runs over the insulating layer (II),
- bei der eine Projektion des oberen Source/Dram-Gebiets- a projection of the upper source / dram area
(S/Do) auf die isolierende Schicht (II) eine Projektion der Wortleitung (W) auf die isolierende Schicht (II) derart überlappt, daß sie jenseits zweier Seiten der Projektion der Wortleitung (W) ausgedehnt ist, so daß Projektionen zweier Teile des oberen Source/Dram-Gebiets (S/Do) an die Projektion der Wortleitung (W) angrenzen und die Projektion der Wortleitung (W) nicht überlappen, - bei der Flanken der Wortleitung (W) mit isolierenden Spacern (Sp) versehen sind,(S / Do) on the insulating layer (II) overlap a projection of the word line (W) on the insulating layer (II) such that it extends beyond two sides of the projection of the word line (W), so that projections of two parts of the border the upper source / dram area (S / Do) to the projection of the word line (W) and do not overlap the projection of the word line (W), - on the flanks of the word line (W) are provided with insulating spacers (Sp),
- bei der eine obere, dem oberen Source/Drain-Gebiet (S/Do) abgewandte Oberflache der Wortleitung (W) mit einer isolierenden Schutzschicht (S) versehen ist, - bei dem eine leitende Struktur (L) die Schutzschicht (S) und die Spacer (Sp) bedeckt und die zwei Teile des oberen Source/Dram-Gebiets (S/Do) überlappt,- In which an upper, the upper source / drain region (S / Do) facing surface of the word line (W) is provided with an insulating protective layer (S), - in which a conductive structure (L), the protective layer (S) and the spacers (Sp) are covered and the two parts of the upper source / dram area (S / Do) overlap,
- bei dem der Kondensator der Speicherzelle auf der leitenden Struktur angeordnet ist.- In which the capacitor of the memory cell is arranged on the conductive structure.
4. DRAM-Zellenanordnung nach einem der Ansprüche 1 bis 3, - bei der die weiteren isolierenden Strukturen (16) die unte¬ ren Source/Dram-Gebiete (S/Du) der entlang des Grabens (G) zueinander benachbarten Transistoren voneinander trennen,4. DRAM cell arrangement according to one of claims 1 to 3, - wherein the other insulating structures (16) ren the unte ¬ source / dram regions (S / Du) of the mutually separate along the trench (G) adjacent transistors from each other,
- bei der die unteren Source/Dram-Gebiete (S/Du) der entlang des Grabens (G) zueinander benachbarten Transistoren und die weiteren isolierenden Strukturen (16) alternierend im Bereich Aussparung an die Bitleitung (B) angrenzen.- In which the lower source / dram regions (S / Du) of the transistors adjacent to one another along the trench (G) and the further insulating structures (16) alternately adjoin the bit line (B) in the region of the recess.
5. DRAM-Zellenanordnung nach einem der Ansprüche 1 bis 4, - bei der die von den Wortleitungen (W) bedeckten Teile der weiteren Isolationen (14) an den Kanten der Wortleitungen (W) verdickt sind.5. DRAM cell arrangement according to one of claims 1 to 4, - in which the parts of the further insulations (14) covered by the word lines (W) are thickened at the edges of the word lines (W).
6. Verfahren zur Herstellung einer DRAM-Zellenanordnung, - bei dem auf einem Substrat (1) eine isolierende Schicht6. Process for producing a DRAM cell arrangement, - in which an insulating layer on a substrate (1)
(II) erzeugt wird,(II) is generated
- bei dem im Substrat (S) im wesentlichen parallel zueinander verlaufende Graben (G) erzeugt werden,in which trenches (G) which run essentially parallel to one another are produced in the substrate (S),
- bei dem untere Teile der Graben (G) bis auf parallel zu den Graben (G) verlaufende, an ersten Flanken der Graben (G) angeordnete streifenformige Aussparungen mit einer Isolati¬ on (13) versehen werden,- are provided at the lower parts of the trench (G) up to the trench (G) extending parallel, arranged on the first edges of the trench (G) strip-shaped recesses with a isolati ¬ one (13)
- bei dem m den unteren Teilen der Graben (G) jeweils eine Bitleitung (B) erzeugt wird, - bei dem über den unteren Teilen der Graben (G) angeordnete Teile der Flanken der Graben (G) und die Bitleitungen (B) mit einer weiteren Isolation (14) versehen werden,- In which m the lower parts of the trenches (G) each generate a bit line (B), - in the parts of the flanks (G) and the bit lines (B) arranged above the lower parts of the trenches (G) with one further insulation (14) can be provided,
- bei dem leitendes Material aufgebracht wird, so daß die Graben (G) gefüllt werden, - bei dem eine Schutzschicht (S) erzeugt wird, die das leitende Material bedeckt,is applied to the conductive material so that the trenches (G) are filled, in which a protective layer (S) is produced which covers the conductive material,
- bei dem das leitende Material und die Schutzschicht (S) so strukturiert werden, daß von der Schutzschicht (S) bedeckte Wortleitungen (W) erzeugt werden, die quer zu den Bitlei- tungen (B) verlaufen und nach unten gerichtete Ausstülpungen aufweisen, die m die Graben (G) reichen, - bei dem isolierendes Material abgeschieden und zusammen mit der isolierenden Schicht _(S) selektiv zur Schutzschicht (S) und zum Substrat (1) ruckgeatzt wird, bis das Substrat (1) freigelegt wird, so daß den Graben (G) isolierende Strukturen (15) erzeugt werden, die zwischen den Ausstül¬ pungen der Wortleitungen (W) und über den Bitleitungen (B) angeordnet sind,- In which the conductive material and the protective layer (S) are structured in such a way that word lines (W) covered by the protective layer (S) are produced which run transversely to the bit lines (B) and have downward protuberances which m the trenches (G) - deposited in the insulating material and, together with the insulating layer _ (S), selectively etched back to the protective layer (S) and to the substrate (1) until the substrate (1) is exposed, so that the trench (G) has insulating structures ( 15 are generated) which are ¬ pungen between the Ausstül of the word lines (W) and above the bit lines (B),
- bei dem das Substrat (1) selektiv zu den isolierenden Strukturen (15) geatzt wird, so daß zwischen den Wortlei- tungen (W) und zwischen den Graben (G) Vertiefungen (V) erzeugt werden,- in which the substrate (1) is etched selectively to the insulating structures (15), so that depressions (V) are produced between the word lines (W) and between the trenches (G),
- bei dem zwischen den Graben (G) und zwischen den Vertiefungen (V) im Substrat (1) obere Source/Dram-Gebiete (S/Do) von Transistoren von Speicherzellen erzeugt werden, - bei dem im Substrat (1) unter den oberen Source/Dram- Gebieten (S/Do) untere Source/Dram-Gebiete (S/Du) der Transistoren erzeugt werden, die jeweils an eine der Aus¬ sparungen angrenzen,- In which between the trenches (G) and between the depressions (V) in the substrate (1) upper source / dram regions (S / Do) of transistors of memory cells are generated, - in the substrate (1) under the upper source / dram regions (S / Do) lower source / dram regions (S / Du) are produced of transistors that are adjacent ¬ savings to one of the combination of either,
- bei dem m den Vertiefungen (V) weitere isolierende Struk- turen (16) erzeugt werden,- In which further insulating structures (16) are produced in the depressions (V),
- bei dem Kondensatoren der Speicherzellen erzeugt werden, die jeweils mit einem der oberen Source/Drain-Gebiete (S/Do) verbunden werden.- The capacitors of the memory cells are generated, which are each connected to one of the upper source / drain regions (S / Do).
7. Verfahren nach Anspruch 6,7. The method according to claim 6,
- bei dem mindestens em Teil der Bitleitung (B) , der an die Aussparung angrenzt, aus dotiertem Polysilizium besteht,in which at least the part of the bit line (B) which adjoins the recess consists of doped polysilicon,
- bei dem e Temperschritt durchgeführt wird, so daß Dotierstoff aus der Bitleitung (B) ms Substrat (1) diffundiert und em dotiertes Gebiet (D2) bildet, das zwischen dem Graben (G) , m dem die Bitleitung (B) angeordnet ist und einem benachbarten Graben (G) angeordnet ist, an die Aussparung angrenzt und vom benachbarten Graben (G) beabstandet- In the e tempering step is carried out so that dopant diffuses from the bit line (B) ms substrate (1) and forms an em doped region (D2) between the trench (G), with which the bit line (B) is arranged and an adjacent trench (G) is arranged, adjacent to the recess and spaced from the adjacent trench (G)
Verfahren nach Anspruch 6 oder 7, - bei dem vor Erzeugung der Vertiefungen (V) durch Abscheiden und Ruckatzen von isolierendem Material Spacer (Sp) erzeugt werden, die Flanken der Wortleitungen (W) bedecken,Method according to claim 6 or 7, in which spacers (Sp) are produced before the recesses (V) are produced by separating and scratching off insulating material, and cover the flanks of the word lines (W),
- bei dem nach Erzeugung der isolierenden Strukturen (15) leitendes Material einer solchen Dicke abgeschieden wird, daß Zwischenräume zwischen den Wortleitungen (W) nicht aufgefüllt werden,in which, after the production of the insulating structures (15), conductive material of such a thickness is deposited that gaps between the word lines (W) are not filled,
- bei dem Teile des leitenden Materials, die über den Graben (G) angeordnet sind, entfernt werden, - bei dem eine Maske (M) erzeugt wird, die horizontale Oberflachen von Teilen des leitenden Materials, die oberhalb der Wortleitung (W) angeordnet sind, bedeckt,- With the parts of the conductive material which are arranged above the trench (G) are removed, - With which a mask (M) is created, the horizontal surfaces of parts of the conductive material which are arranged above the word line (W) covered
- bei dem zur Erzeugung der Vertiefungen (V) das leitende Material und das Substrat (1) selektiv zur Maske (M) geatzt werden, so daß aus dem leitenden Material leitende Struktu¬ ren (L) entstehen, die an die oberen Source/Dram-Gebiete (S/Do) angrenzen,- wherein the conductive material and the substrate (1) are etched selectively with respect to the mask (M) to produce the recesses (V) so that conducting of the conductive material struc ¬ ren (L) are produced, which at the upper source / dram - border areas (S / Do),
- bei dem die Kondensatoren auf den leitenden Strukturen (L) erzeugt werden.- In which the capacitors are generated on the conductive structures (L).
9. Verfahren nach Anspruch 8,9. The method according to claim 8,
- bei dem zur Erzeugung der Maske (M) isolierendes Material nicht konform abgeschieden wird, so daß das isolierende Ma¬ terial über den horizontalen Oberflachen der Teile des lei- tenden Materials, die oberhalb der Wortleitung (W) angeordnet sind, am dicksten ist,- is not conformally deposited on the insulating for the generation of the mask (M) material so that the insulating Ma ¬ TERIAL, is thickest over the horizontal surfaces of the parts of the managerial material which are arranged above the word line (W),
- bei dem die Maske (M) aus dem isolierenden Material erzeugt wird, indem das isolierende Material ruckgeatzt wird, bis zwischen den Wortleitungen (W) angeordnete Teile des lei- tenden Materials freigelegt werden.- In which the mask (M) is produced from the insulating material by etching back the insulating material until parts of the conductive material arranged between the word lines (W) are exposed.
10. Verfahren nach Anspruch 8,10. The method according to claim 8,
- bei dem das leitende Material dotiertes Polysilizium enthalt, - bei dem nach Abscheiden des leitenden Materials em Hilfs- mateπal abgeschieden und ruckgeatzt wird, bis seitliche Flachen des leitenden Materials freigelegt werden, - bei dem eine thermische Oxidation durchgeführt wird, so daß die Maske auf freiliegenden Teilen des leitenden Materials erzeugt wird,- in which the conductive material contains doped polysilicon, - in which, after the conductive material has been deposited, an auxiliary material is deposited and etched back until lateral surfaces of the conductive material are exposed, in which thermal oxidation is carried out so that the mask is produced on exposed parts of the conductive material,
- bei dem das Hilfsmaterial entfernt wird.- in which the auxiliary material is removed.
11. Verfahren nach einem der Ansprüche 6 bis 10,11. The method according to any one of claims 6 to 10,
- bei dem Vertiefungen (V) so erzeugt werden, daß sie tiefer als die Aussparungen der Isolation (13) reichen.- In the recesses (V) are generated so that they extend deeper than the recesses of the insulation (13).
12. Verfahren nach einem der Ansprüche 6 bis 11,12. The method according to any one of claims 6 to 11,
- bei dem nach Erzeugung der Wortleitungen (W) eine thermische Oxidation so durchgeführt wird, daß die von den Wortleitungen (W) bedeckten Teile der weiteren Isolationen (14) an Kanten der Wortleitungen (W) verdickt werden. - In which, after generation of the word lines (W), thermal oxidation is carried out in such a way that the parts of the further insulation (14) covered by the word lines (W) are thickened at the edges of the word lines (W).
EP00916811A 1999-03-12 2000-03-10 Dram cell arrangement and method for producing the same Withdrawn EP1161770A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19911148 1999-03-12
DE19911148A DE19911148C1 (en) 1999-03-12 1999-03-12 DRAM cell array has single vertical transistor memory cells with buried bit lines and low space requirement
PCT/DE2000/000756 WO2000055904A1 (en) 1999-03-12 2000-03-10 Dram cell arrangement and method for producing the same

Publications (1)

Publication Number Publication Date
EP1161770A1 true EP1161770A1 (en) 2001-12-12

Family

ID=7900802

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00916811A Withdrawn EP1161770A1 (en) 1999-03-12 2000-03-10 Dram cell arrangement and method for producing the same

Country Status (8)

Country Link
US (1) US6504200B2 (en)
EP (1) EP1161770A1 (en)
JP (1) JP3786836B2 (en)
KR (1) KR100403442B1 (en)
CN (1) CN1150612C (en)
DE (1) DE19911148C1 (en)
TW (1) TW461086B (en)
WO (1) WO2000055904A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19914490C1 (en) 1999-03-30 2000-07-06 Siemens Ag DRAM or FRAM cell array, with single transistor memory cells, has trench conductive structures and upper source-drain regions overlapping over a large area for low contact resistance between capacitors and transistors
DE19950364A1 (en) 1999-10-19 2001-04-26 Infineon Technologies Ag Integrated circuit arrangement used as a DRAM cell arrangement comprises a capacitor with capacitor electrodes and a capacitor dielectric
DE10028424C2 (en) * 2000-06-06 2002-09-19 Infineon Technologies Ag Manufacturing process for DRAM memory cells
KR100652370B1 (en) * 2000-06-15 2006-11-30 삼성전자주식회사 Semiconductor memory device removing floating body effect and method of fabricating the same
KR100473476B1 (en) * 2002-07-04 2005-03-10 삼성전자주식회사 Semiconductor device and Method of manufacturing the same
TWI225691B (en) * 2003-03-14 2004-12-21 Nanya Technology Corp A vertical NROM cell and method for fabrication the same
DE10326330A1 (en) * 2003-06-11 2005-01-05 Infineon Technologies Ag Manufacturing semiconducting memory device involves providing protective structure in doped region to inhibit existence of leakage current path between gate conductor and doped region
KR100660880B1 (en) * 2005-10-12 2006-12-26 삼성전자주식회사 Method of fabricating a semiconductor memory device having a plurality of storage node electrodes
US7859026B2 (en) * 2006-03-16 2010-12-28 Spansion Llc Vertical semiconductor device
US20080315326A1 (en) * 2007-06-21 2008-12-25 Werner Graf Method for forming an integrated circuit having an active semiconductor device and integrated circuit
US7952138B2 (en) * 2007-07-05 2011-05-31 Qimonda Ag Memory circuit with field effect transistor and method for manufacturing a memory circuit with field effect transistor
JP2009182105A (en) * 2008-01-30 2009-08-13 Elpida Memory Inc Semiconductor device and manufacturing method thereof
KR100979240B1 (en) * 2008-04-10 2010-08-31 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8786014B2 (en) * 2011-01-18 2014-07-22 Powerchip Technology Corporation Vertical channel transistor array and manufacturing method thereof
KR101168338B1 (en) * 2011-02-28 2012-07-31 에스케이하이닉스 주식회사 Semiconductor memory device and method of manufacturing the same
FR3023647B1 (en) 2014-07-11 2017-12-29 Stmicroelectronics Rousset VERTICAL TRANSISTOR FOR RESISTIVE MEMORY
CN113497129B (en) * 2020-04-07 2023-12-01 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4824793A (en) * 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US5225697A (en) * 1984-09-27 1993-07-06 Texas Instruments, Incorporated dRAM cell and method
JPH02159058A (en) * 1988-12-13 1990-06-19 Fujitsu Ltd Semiconductor memory cell
KR940006679B1 (en) * 1991-09-26 1994-07-25 현대전자산업 주식회사 Dram cell having a vertical transistor and fabricating method thereof
US5208172A (en) * 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
KR0147584B1 (en) * 1994-03-17 1998-08-01 윤종용 Buried bit line cell manufacturing method
US5497017A (en) * 1995-01-26 1996-03-05 Micron Technology, Inc. Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors
DE19519159C2 (en) * 1995-05-24 1998-07-09 Siemens Ag DRAM cell arrangement and method for its production
ATE212149T1 (en) * 1995-09-26 2002-02-15 Infineon Technologies Ag SELF-Amplifying DRAM MEMORY CELL ARRANGEMENT
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor
US5892707A (en) * 1997-04-25 1999-04-06 Micron Technology, Inc. Memory array having a digit line buried in an isolation region and method for forming same
EP0899790A3 (en) * 1997-08-27 2006-02-08 Infineon Technologies AG DRAM cell array and method of producing the same
DE59814170D1 (en) * 1997-12-17 2008-04-03 Qimonda Ag Memory cell arrangement and method for its production
EP0945901A1 (en) * 1998-03-23 1999-09-29 Siemens Aktiengesellschaft DRAM cell array with vertical transistors and process of manufacture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0055904A1 *

Also Published As

Publication number Publication date
CN1150612C (en) 2004-05-19
CN1343371A (en) 2002-04-03
KR100403442B1 (en) 2003-10-30
TW461086B (en) 2001-10-21
US6504200B2 (en) 2003-01-07
JP2002539642A (en) 2002-11-19
JP3786836B2 (en) 2006-06-14
DE19911148C1 (en) 2000-05-18
WO2000055904A1 (en) 2000-09-21
KR20010104379A (en) 2001-11-24
US20020079527A1 (en) 2002-06-27

Similar Documents

Publication Publication Date Title
DE19519160C1 (en) DRAM cell arrangement having packing density required for specified memory
DE19928781C1 (en) DRAM cell array has deep word line trenches for increasing transistor channel length and has no fixed potential word lines separating adjacent memory cells
DE102004006520B4 (en) Method for producing a DRAM memory cell arrangement with trench capacitors and ridge field effect transistors (FinFET) and DRAM memory cell arrangement
EP1166350B1 (en) Method for producing a dram structure with buried bit lines or trench capacitors
DE102005055853A1 (en) Transistor array for semiconductor memory devices and method for fabricating a array of vertical channel transistors
DE10306281A1 (en) Arrangement of vertical transistor cells for dynamic read-write memory has active regions joining at least transistor cells adjacent in x-direction; charge transport is enabled between such cells
DE19718721C2 (en) DRAM cell arrangement and method for its production
DE19911148C1 (en) DRAM cell array has single vertical transistor memory cells with buried bit lines and low space requirement
DE19943760C1 (en) DRAM cell arrangement comprises a substrate with a recess containing a storage node of a capacitor
EP1125328B1 (en) Method for producing a dram cell arrangement
DE19811882A1 (en) DRAM cell arrangement
EP0945901A1 (en) DRAM cell array with vertical transistors and process of manufacture
DE19845004C2 (en) DRAM cell arrangement and method for its production
DE19720193C2 (en) Integrated circuit arrangement with at least two vertical MOS transistors and method for their production
WO2000033383A1 (en) Dram cell arrangement and method for the production thereof
EP1129482B1 (en) Method for producing a DRAM Cell System
EP1116270A1 (en) Integrated circuit comprising vertical transistors, and a method for the production thereof
EP0917203A2 (en) Gain cell DRAM structure and method of producing the same
DE19954867C1 (en) Dynamic random access memory (DRAM) cells arrangement, each cell having one vertical transistor and one capacitor
WO2001001481A1 (en) Mos transistor and dram cell arrangement and method for the production thereof
DE19637389C1 (en) High packing density DRAM cell array production
DE19923262C1 (en) Memory cell array, especially dynamic random access memory cell array, production comprises insulation removal from only one side wall of a recess by non-masked etching to allow adjacent cell transistor formation
DE19914490C1 (en) DRAM or FRAM cell array, with single transistor memory cells, has trench conductive structures and upper source-drain regions overlapping over a large area for low contact resistance between capacitors and transistors
EP1097471B1 (en) Integrated circuit with at least one transistor and a capacitor and corresponding production method
EP1118116B1 (en) Substrate with an indentation for an integrated circuit device and method for the production thereof

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20010813

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IE IT

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090902