ATE212149T1 - SELF-Amplifying DRAM MEMORY CELL ARRANGEMENT - Google Patents

SELF-Amplifying DRAM MEMORY CELL ARRANGEMENT

Info

Publication number
ATE212149T1
ATE212149T1 AT96113008T AT96113008T ATE212149T1 AT E212149 T1 ATE212149 T1 AT E212149T1 AT 96113008 T AT96113008 T AT 96113008T AT 96113008 T AT96113008 T AT 96113008T AT E212149 T1 ATE212149 T1 AT E212149T1
Authority
AT
Austria
Prior art keywords
doped
covered
ring
memory cell
gate
Prior art date
Application number
AT96113008T
Other languages
German (de)
Inventor
Wolfgang Dr Krautschneider
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE212149T1 publication Critical patent/ATE212149T1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

The DRAM cell arrangement includes a substrate (11) of n- doped monocrystalline silicon with a p-doped region (12), with a trough (13) which is covered with a gate dielectric (14), and around which a ring-shaped n-doped region (15) is formed. A first gate electrode (16) of n<+>-doped polysilicon is covered with a dielectric coating (17), above which a p-doped polysilicon structure (18) is formed which links up with the n-doped ring, and forms a diode with the first gate electrode. It is covered by an isolation structure (19) up to its upper edge, thus completing a storage transistor. A selector transistor is formed from similar gate electrodes, dielectric and n-doped regions (111,110,112) which are covered with an isolation layer (113) of silica, forming insulating spacers (114). The n-doped ring region forms the common gate for both transistors, to which the p-doped polysilicon structure (18) is linked via an e.g. wolfram contact (115) filled into a oxide layer (116), which is covered by a further oxide layer (117) which spans the whole structure forming a memory cell.
AT96113008T 1995-09-26 1996-08-13 SELF-Amplifying DRAM MEMORY CELL ARRANGEMENT ATE212149T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19535496 1995-09-26

Publications (1)

Publication Number Publication Date
ATE212149T1 true ATE212149T1 (en) 2002-02-15

Family

ID=7773037

Family Applications (1)

Application Number Title Priority Date Filing Date
AT96113008T ATE212149T1 (en) 1995-09-26 1996-08-13 SELF-Amplifying DRAM MEMORY CELL ARRANGEMENT

Country Status (8)

Country Link
US (1) US5854500A (en)
EP (1) EP0766312B1 (en)
JP (1) JP3737576B2 (en)
KR (1) KR100439836B1 (en)
AT (1) ATE212149T1 (en)
DE (1) DE59608588D1 (en)
HK (1) HK1003544A1 (en)
TW (1) TW382806B (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5789306A (en) * 1996-04-18 1998-08-04 Micron Technology, Inc. Dual-masked field isolation
DE19723936A1 (en) * 1997-06-06 1998-12-10 Siemens Ag DRAM cell arrangement and method for its production
DE59814170D1 (en) * 1997-12-17 2008-04-03 Qimonda Ag Memory cell arrangement and method for its production
DE19800340A1 (en) * 1998-01-07 1999-07-15 Siemens Ag Semiconductor memory device and method for its production
DE19812212A1 (en) * 1998-03-19 1999-09-23 Siemens Ag MOS transistor in a one-transistor memory cell with a locally thickened gate oxide and manufacturing method
JP4439020B2 (en) * 1998-03-26 2010-03-24 株式会社東芝 Semiconductor memory device and manufacturing method thereof
EP0973203A3 (en) * 1998-07-17 2001-02-14 Infineon Technologies AG Semiconductor layer with lateral variable doping and its method of fabrication
DE19911148C1 (en) * 1999-03-12 2000-05-18 Siemens Ag DRAM cell array has single vertical transistor memory cells with buried bit lines and low space requirement
DE19961779A1 (en) * 1999-12-21 2001-07-05 Infineon Technologies Ag Integrated dynamic memory cell with small spreading area and process for its production
US6420749B1 (en) * 2000-06-23 2002-07-16 International Business Machines Corporation Trench field shield in trench isolation
JP4236848B2 (en) * 2001-03-28 2009-03-11 セイコーインスツル株式会社 Manufacturing method of semiconductor integrated circuit device
US7224024B2 (en) 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US6838723B2 (en) * 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US6956256B2 (en) * 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
US7553740B2 (en) * 2005-05-26 2009-06-30 Fairchild Semiconductor Corporation Structure and method for forming a minimum pitch trench-gate FET with heavy body region
US7459743B2 (en) * 2005-08-24 2008-12-02 International Business Machines Corporation Dual port gain cell with side and top gated read transistor
US7859026B2 (en) * 2006-03-16 2010-12-28 Spansion Llc Vertical semiconductor device
KR100847308B1 (en) * 2007-02-12 2008-07-21 삼성전자주식회사 Semiconductor device and method for manufacturing the same
DE102007029756A1 (en) * 2007-06-27 2009-01-02 X-Fab Semiconductor Foundries Ag Semiconductor structure for producing a carrier wafer contact in trench-isolated SOI slices
JP2009094354A (en) * 2007-10-10 2009-04-30 Toshiba Corp Nonvolatile semiconductor storage device
US8878292B2 (en) * 2008-03-02 2014-11-04 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US9882049B2 (en) * 2014-10-06 2018-01-30 Alpha And Omega Semiconductor Incorporated Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method
US12062656B2 (en) * 2021-10-29 2024-08-13 Nanya Technology Corporation Semiconductor device structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2861243B2 (en) * 1990-04-27 1999-02-24 日本電気株式会社 Dynamic random access memory cell
TW199237B (en) * 1990-07-03 1993-02-01 Siemens Ag
US5571738A (en) * 1992-09-21 1996-11-05 Advanced Micro Devices, Inc. Method of making poly LDD self-aligned channel transistors
US5308783A (en) * 1992-12-16 1994-05-03 Siemens Aktiengesellschaft Process for the manufacture of a high density cell array of gain memory cells
DE4417150C2 (en) * 1994-05-17 1996-03-14 Siemens Ag Method for producing an arrangement with self-reinforcing dynamic MOS transistor memory cells
US5661322A (en) * 1995-06-02 1997-08-26 Siliconix Incorporated Bidirectional blocking accumulation-mode trench power MOSFET

Also Published As

Publication number Publication date
EP0766312A1 (en) 1997-04-02
US5854500A (en) 1998-12-29
JPH09116026A (en) 1997-05-02
JP3737576B2 (en) 2006-01-18
KR970018605A (en) 1997-04-30
DE59608588D1 (en) 2002-02-21
HK1003544A1 (en) 1998-10-30
TW382806B (en) 2000-02-21
EP0766312B1 (en) 2002-01-16
KR100439836B1 (en) 2004-12-13

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