40637C 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 5-1發明領域： 本發明係有關於動態隨機存取記憶體之製造， 特別是有關於一種形成動態隨機存取記憶體電容器的方 法，使其具有較小的接觸窗長寬比及高電容值。 5-2發明背景： 由於電子產品及電腦相關產品的普及化，使得 半導體記憶元件的需求急速增加。早期之動態隨機存取 記憶體元件是以三個P通道金氧半電晶體組合成一個單 元。之後，R. H. Dennard於美國專利號碼3，387，286標 題為，’FIELD EFFECT TRANSISTOR MEMORr 中提出一種具單 電晶體結構之動態隨機存取記憶體元件。於製造此動態 隨機存取記憶體元件時’首先’形成一接觸窗以形成電 容器節點。接著，沈積多晶矽層以形成電容器之底層極 板。當動態隨機存取記憶體之密度愈來愈高’使得其電 容的面積變小’連帶也使得其電容量變小。然而’為了 減少因為外界輻射線干擾使得記憶體讀取產生錯誤’必 須維持一定的電容量。因此’如何降低記憶體元件面積 並同時得到一高電容量之電容變成一個重要的課題。 再者，當記憶體之積集度變得愈高時，將使得 接觸窗的長寬比（aspect ratio)變大’造成製造的困難 本紙張尺度適用中國國家標準（CNS ) A4規格（210乂 297公兔） HI I I. I - I - - Ι^ί 111 —Γ κ^ml I- - ---- m ϋ— In "^、-° - (請先閱讀背面之注意事項再填寫本f ) 406376a B7 五、發明説明（） 及低產出。因此，亟需提出一種形成動態隨機存取記憶 體之方法，使其具有較小的接觸窗長寬比及高電容值。 (請先閱讀背面之注意事項再填寫本頁) 5-3發明目的及概述： 鑒於上述之發明背景中，傳統的動態隨機存取 記憶體電容器所具有的諸多缺點’本發明的主要目的在 於提出一種形成動態隨機存取記憶體電容器的方法，使 其具有較小的接觸窗長寬比及高電容值。根據本發明其 中一實施例，首先，形成第一導電層於半導體基板上， 及形成第一介電層於第一導電層上。經過微影並蝕刻第 一介電層及第一導電層後，形成第二介電層於半導體基 板及第一介電層上，並以非等向性回蝕第二介電層，以 形成第一側隙間壁於第一介電層及第一導電層之側壁 上。接著，形成第一氧化矽層於半導體基板、第一介電 層及第一侧隙間壁上，且微影並蝕刻第一氧化矽層，其 中第一側隙間壁及第一介電層係用以作為自動對準蝕刻 之用。形成第二導電層於半導體基板上，並暴露第一氧 化矽層之表面，再形成第二氧化矽層於第二導電層及第 一氧化矽層上。微影並蝕刻部份第二氧化矽層，以暴露 出部份第二導電層，因而形成電容器之接觸窗。 經濟部智慧財產局8工消費合作社印製 接著，形成第三導電層於第二氧化矽層上，且此第 三導電層填滿接觸窗，再形成第三介電層於第三導電層 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297'^釐） 經濟部智慧財產局肖工消費合作社印製 406376 Λ；7 B? —S·、發明説明（） 上。於微影並蝕刻第三介電層及第三導電層後，形成第 四介電層於第二氧化矽層上，並以非等向性回蝕第四介 電層，以形成第二側隙間壁於第三介電層及第三導電層 之侧壁上。接著，形成第三氧化矽層於第三介電層、第 二侧隙間壁及第二氧化矽層上，並且微影以蝕刻第三氧 化矽層，其中第二側隙間壁及第三介電層係用以作為自 動對準蝕刻之用。形成第四導電層於第三氧化矽層、第 三介電層、第二側隙間壁及第二導電層上，以作為電容 器的底部極板。形成犧牲層於第四導電層上，並露出部 份第四導電層之表面，再回蝕第四導電層，以暴露出第 三氧化矽層之表面。最後，於除去第三氧化矽層及該犧 牲層之後，形成第五介電層於第四導電層上，及形成第 五導電層於第五介電層上，以作為電容器的頂部極板。 5-4圈式簡單說明· 第一圖至第八圖顯示本發明實施例於形成隨機 存取記憶體體電容之接觸窗的各步驟剖面示意圖。 第九圖至第十四圖更進一步顯示本發明實施例 於形成隨機存取記憶體體電容的各步驟剖面示意圖。 5-5發明詳細說明： 參閱第一圖，於半導體基板 10及場氧化區 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公1 趁） i^n. mu I—-'I - - -- 1— τι —ί' - - -*1 - - - - jn 一OJI. . . —i . . . nn ::-- I i (諳先閱讀背面之注意事項再填寫本頁) 406376 Λ 7 Β7 五、發明説明（） (FOX) 1 2上面形成摻雜多晶矽層1 4。在本實施例中，此 多晶矽層1 4係以傳統低壓化學氣相沈積法（LPCVD )所沈 積，並摻雜填離子’其濃度約為5E20原子/ cm3。接著， 以傳統金屬矽化方法形成金屬矽化層（s i 1 i c i d e ) 1 6。通 常，金屬石夕化層1 6和多晶石夕層1 4合起來一般稱為多晶 石夕化金屬（Ρ 〇 1 y c i d e)。值得注意的是’多晶石夕化金屬可 以用單層摻雜多晶矽來代替，然而，後者通常具有較大 的阻值。於金屬石夕化層1 6上面形成一介電層1 8，例如氣 化矽。在本實施例中，此氮化矽層1 8係以傳統低壓化學 氣相沈積法（LPCVD)所沈積。 使用傳統微影技術形成光阻層2 0於氮化矽層18 上，以定義閘極區。以光阻層2 0為遮罩，蝕刻氮化矽層 1 8、金屬矽化層1 6及多晶矽層1 4，因而形成第二圖所示 的結構。在此圖式中最右邊的閘極，係作為形成週邊 (peripheral)接觸窗之用，其詳細情形將於底下說明 之。 經濟部智慧財是局Μ工消費合作社印製 *--IV 裝丨'---„---訂 (請先閱讀背面之注意事項再填寫本頁) 接著，形成一介電層2 2 (例如氮化矽）於整個半 導體基板1 〇及氮化矽層1 8上面。以非向性蝕刻法（例如 活性離子蝕刻法）回蝕介電層 2 2，因而形成側隙間壁 (spacer )22A於閘極（其係由氮化矽層18、金屬矽化層16 及多晶石夕層1 4組成）之側壁上’如第三圖所示。接著， 以傳統離子植入方法形成源極/汲極區2 4 A、2 4 B。其中’ ---$- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 406376 B7 五、發明説明（） 離子植入區2 4 A於記憶體作資料讀取時，係作為源極區， 而於資料寫入時，則作為汲極區；至於離子植入區24B 於記憶體作資料讀取時’係作為没極區’而於資料寫入 時，則作為源極區。 接著，形成一薄氧化矽層26於側隙間壁22A、 氮化矽層18及半導體基板1〇之表面’如第四圖所示。 此薄氧化矽層26可以用四已基矽酸鹽（TE0S)反應氣體及 傳統低壓化學氣相沈積法（LPCVD)所沈積。在整個薄氧化 矽層2 6上面，形成另一氧化矽層2 8。在本實施例中’由 於硼磷矽玻璃（BPSG)具有低回火（reflow)溫度，因而適 於作為氧化矽層2 8之材質。值得注意的是，氧化矽層2 8 底下的薄氧化矽層2 6主要係作為阻絕層，用以阻隔氧化 矽層 28 内的硼（B)或磷（P)向下產生自動摻雜 (autodoping)，而影像底下的半導體元件。 使用傳統回蝕刻方法或化學機械研磨法 (CMP)，除去氧化矽層28之一適當厚度，因而平坦化此 氧化石夕層2 8，如第五圖所示。 使用傳統微影技術形成光阻層3 0於氧化矽層2 8 上，以定義區域於部份閘極表面上。以光阻層3 0為遮罩’ 蝕刻氧化石夕層2 8及薄氧化矽層2 6，因而形成第六圖所示 之結構。其中，側隙間壁2 2 A及氮化矽層1 8係作為自動 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210><)97公°歷） (請先閱讀背面之注意事項再填寫本頁)40637C Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (5-1) Field of the Invention: The present invention relates to the manufacture of dynamic random access memory, and in particular to a capacitor for forming dynamic random access memory Method to make it have smaller contact window aspect ratio and high capacitance value. 5-2 Background of the Invention: Due to the popularity of electronic products and computer-related products, the demand for semiconductor memory elements has increased rapidly. Earlier dynamic random access memory devices consisted of three P-channel metal-oxide semiconductors to form a unit. Later, R. H. Dennard, in U.S. Patent No. 3,387,286, entitled, 'FIELD EFFECT TRANSISTOR MEMORr, proposed a dynamic random access memory device with a single crystal structure. When the dynamic random access memory device is manufactured, a contact window is formed 'first' to form a capacitor node. Next, a polycrystalline silicon layer is deposited to form the bottom electrode of the capacitor. As the density of the dynamic random access memory becomes higher and higher, 'making the area of its capacitance smaller', it also makes its capacitance smaller. However, 'in order to reduce memory reading errors due to external radiation interference', it is necessary to maintain a certain capacitance. Therefore, how to reduce the area of the memory element and simultaneously obtain a high-capacitance capacitor becomes an important issue. In addition, as the memory accumulation becomes higher, the aspect ratio of the contact window will increase, which will cause difficulties in manufacturing. This paper applies the Chinese National Standard (CNS) A4 specification (210 乂). 297 male rabbit) HI I I. I-I--Ι ^ ί 111 —Γ κ ^ ml I------ m ϋ— In " ^,-°-(Please read the notes on the back before filling This f) 406376a B7 V. Description of invention () and low output. Therefore, a method for forming a dynamic random access memory is urgently needed, so that it has a small contact window aspect ratio and a high capacitance value. (Please read the notes on the back before filling this page) 5-3 Purpose and summary of the invention: In view of the above-mentioned background of the invention, the traditional dynamic random access memory capacitors have many shortcomings. The main purpose of the present invention is to propose A method for forming a dynamic random access memory capacitor with a smaller contact window aspect ratio and a high capacitance value. According to one embodiment of the present invention, first, a first conductive layer is formed on a semiconductor substrate, and a first dielectric layer is formed on the first conductive layer. After lithography and etching the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer, and the second dielectric layer is anisotropically etched back to form The first side gap wall is on the side wall of the first dielectric layer and the first conductive layer. Next, a first silicon oxide layer is formed on the semiconductor substrate, the first dielectric layer, and the first side-gap wall, and the first silicon oxide layer is lithographed and etched. The first side-gap wall and the first dielectric layer are used. For automatic alignment etching. A second conductive layer is formed on the semiconductor substrate, and the surface of the first silicon oxide layer is exposed, and then a second silicon oxide layer is formed on the second conductive layer and the first silicon oxide layer. Lithography and etching a portion of the second silicon oxide layer to expose a portion of the second conductive layer, thereby forming a contact window for the capacitor. Printed by the 8th Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, a third conductive layer is formed on the second silicon oxide layer, and the third conductive layer fills the contact window, and then a third dielectric layer is formed on the third conductive layer. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 '^ centimeters) printed by Xiao Gong Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs, printed on 406376 Λ; 7 B? —S ·, Description of Invention (). After lithography and etching the third dielectric layer and the third conductive layer, a fourth dielectric layer is formed on the second silicon oxide layer, and the fourth dielectric layer is anisotropically etched back to form a second side The gap wall is on the sidewall of the third dielectric layer and the third conductive layer. Next, a third silicon oxide layer is formed on the third dielectric layer, the second spacer wall and the second silicon oxide layer, and lithography is performed to etch the third silicon oxide layer, wherein the second spacer wall and the third dielectric are etched. The layer is used for automatic alignment etching. A fourth conductive layer is formed on the third silicon oxide layer, the third dielectric layer, the second side wall and the second conductive layer to serve as a bottom plate of the capacitor. A sacrificial layer is formed on the fourth conductive layer, and a part of the surface of the fourth conductive layer is exposed, and then the fourth conductive layer is etched back to expose the surface of the third silicon oxide layer. Finally, after removing the third silicon oxide layer and the sacrificial layer, a fifth dielectric layer is formed on the fourth conductive layer, and a fifth conductive layer is formed on the fifth dielectric layer to serve as the top electrode plate of the capacitor. 5-4 circle type simple explanation · The first to eighth diagrams are schematic cross-sectional diagrams of each step of forming a contact window of a random access memory capacitor according to an embodiment of the present invention. The ninth to fourteenth diagrams further show cross-sectional schematic diagrams of steps of forming a random access memory capacitor according to an embodiment of the present invention. 5-5 Detailed description of the invention: Refer to the first figure, and apply the Chinese National Standard (CNS) A4 specification (210X297 male 1) to the paper size of the semiconductor substrate 10 and the field oxidation area. I ^ n. Mu I —- 'I- --1— τι —ί '---* 1----jn 一 OJI... —I... Nn ::-I i (谙 Please read the notes on the back before filling this page) 406376 Λ 7 Β7 V. Description of the invention () (FOX) 1 2 A doped polycrystalline silicon layer 14 is formed on the top. In this embodiment, the polycrystalline silicon layer 14 is deposited by a conventional low-pressure chemical vapor deposition (LPCVD) method, and is doped with a filling ion, and its concentration is about 5E20 atoms / cm3. Next, a metal silicide layer (s i 1 i c i d e) 16 is formed by a conventional metal silicide method. In general, the metal petrified layer 16 and the polycrystalline petrified layer 14 are collectively referred to as a polymetallic petrified metal (P 0 1 y c i d e). It is worth noting that 'polycrystalline silicon metal can be replaced with a single layer of doped polycrystalline silicon, however, the latter usually has a larger resistance value. A dielectric layer 18 is formed on the metallization layer 16 such as silicon dioxide. In this embodiment, the silicon nitride layer 18 is deposited by a conventional low pressure chemical vapor deposition (LPCVD) method. A photoresist layer 20 is formed on the silicon nitride layer 18 using a conventional lithography technique to define a gate region. With the photoresist layer 20 as a mask, the silicon nitride layer 18, the metal silicide layer 16 and the polycrystalline silicon layer 14 are etched, thereby forming the structure shown in the second figure. The gate on the far right in this figure is used to form a peripheral contact window. The details will be described below. Printed by the Ministry of Economic Affairs ’Smart Industry Consumer Cooperatives *-IV Pack 丨 '---„ --- Order (Please read the precautions on the back before filling this page) Then, form a dielectric layer 2 2 ( For example, silicon nitride) is formed on the entire semiconductor substrate 10 and the silicon nitride layer 18. The dielectric layer 22 is etched back by a non-directional etching method (such as an active ion etching method), thereby forming a spacer 22A. On the side wall of the gate electrode (which is composed of silicon nitride layer 18, metal silicide layer 16 and polycrystalline silicon layer 14) as shown in the third figure. Then, a source / Drain area 2 4 A, 2 4 B. Among them --- $-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 406376 B7 V. Description of the invention () Ion implantation area 2 4 A is used as the source region when data is read from the memory, and is used as the drain region when the data is written. As for the ion implantation region 24B, it is used as the non-polar region when the data is read from the memory. When the data is written, it serves as the source region. Next, a thin silicon oxide layer 26 is formed on the side wall 22A, the silicon nitride layer 18, and the semiconductor The surface of the body substrate 10 is shown in the fourth figure. The thin silicon oxide layer 26 can be deposited using a tetrahexyl silicate (TEOS) reaction gas and a conventional low pressure chemical vapor deposition (LPCVD) method. On top of the silicon oxide layer 26, another silicon oxide layer 28 is formed. In this embodiment, 'Since borophosphosilicate glass (BPSG) has a low reflow temperature, it is suitable as the material of the silicon oxide layer 28. It is worth noting that the thin silicon oxide layer 26 under the silicon oxide layer 2 8 is mainly used as a barrier layer to block the boron (B) or phosphorus (P) in the silicon oxide layer 28 from automatically doping downward ( autodoping), and the semiconductor element under the image. Using a conventional etch-back method or chemical mechanical polishing (CMP) method, one of the silicon oxide layers 28 is removed to an appropriate thickness, thereby planarizing the oxide layer 28, as shown in the fifth figure. The conventional photolithography technique is used to form a photoresist layer 30 on the silicon oxide layer 28 to define a region on a part of the gate surface. The photoresist layer 30 is used as a mask to etch the oxide stone layer 28 and The thin silicon oxide layer is 26, so the structure shown in Fig. 6 is formed. 2 2 A and the silicon nitride layer 18 present as an automatic paper-based Chinese National Standards applicable Scale (CNS) Λ4 specifications (210 > lt &;) 97 ° calendar well) (Read precautions and then fill the back side of this page)
，1T 經濟部智毡財產场貨工消费合作社印製 ---- 五、發明説明（ 對準接觸窗（SAC)蝕刻時之用。 參閱第七圖’形成摻雜多晶矽層32於第六圖之 結構上’並回蝕刻直到露出氧化矽層28之表面。接著， 形成多晶石夕接觸窗插塞（plug) 32於半導體基板1〇上。 '尤積氧化矽層34於多晶矽接觸窗插塞32及氧化妙 層2 8之上。在本實施例中，係使用硼磷矽玻璃作為氧化 之材質。使用傳統微影技術形成光阻層36於氧 化夕層34上，以定義接觸窗區域。以光阻層36為遮革， 蚀^氧化5夕層3 4以形成位元線（b i t - 1 i n e )接觸窗洞3 8， 其中多晶石夕接觸窗插塞32係作為終點偵測（end_ point),如第八圖所示。值得注意的是，藉由蝕刻氧化 夕廣3 4多晶石夕接觸窗插塞3 2及氮化矽層1 8，可以同 成接觸窗洞39於週邊區域。和傳統方法不同的是， 藉由本&明，位元線（b i t - U n e)接觸窗洞3 8及週邊接觸 窗洞39可以同時形成。於第八圖中，接觸窗38之深度 般大為〇. 1微米’而週邊接觸窗3 9之深度大約為〇 · 5 微米以上。當利用含CH3F/CHF3/CF4之活性電漿蝕刻 (R1E)使其具有較高S i 〇 2及S i 3 N 4之蝕刻率；但是對於 夕sa石夕及金屬矽化物（例如WS i)，其具有較高（約大於5) • I擇1± (亦即其具有較低敍刻率），因而能達成接觸 由38及週邊接觸窗39同時形成深淺不同的接觸窗之目 的。 本紙張尺侧巾 f請先閲讀背面之注意事項再填寫本頁) 裴- -訂 經濟部智毡財產局工消"合作社印製 406376 B7 五、發明説明（ 再者本發月所开》成之接觸窗洞Μ的長 (aSPeCt rati〇)較傳統結構小。傳統習知技術未使^ 塞’其接觸窗尺寸為：0〇·275微米，深"微米，】插 f靖先閑讀、背面之注意事¾再填窝本頁) 長寬比大約為3。至於本發明之接觸窗（如第八圖中=此 38所示）’其尺寸為：0〇·25微米，深〇」微米，^號 長寬比大約為0_ 4。故，本發明之長寬比確實比習知此 來得小。 技衝 參閱第九圖，於氧化矽層34及多晶矽接觸外 塞32上面形成摻雜多晶矽層114。在本實施例中，2插 晶矽層11 4係以傳統低壓化學氣相沈精法（LpcVD)所= 積，並摻雜磷離子，其濃度約為5E2〇原子/cm3。接著’ 以傳統金屬矽化方法形成金屬矽化層（s i 1丨c丨de)丨丨6。通 常，金屬矽化層116和多晶矽層114合起來一般稱為多 晶矽化金屬（polycide)。值得注意的是，多晶矽化金屬 可以用單層摻雜多晶矽來代替，然而，後者一般具有較 大的阻值。於金屬石夕化層丨丨6上面形成一介電層u 8 ’例 如氮化矽。在本實施例中，此氮化矽層11 8係以傳統低 壓化學氣相沈積法（LPCVD)所沈積。 經濟部智丛財,/i局S工消費合作社印製 使用傳統微影技術形成光阻層1 2 〇於氮化矽層 11 8上，以定義閘極區。以光阻層1 2 0為遮罩，蝕刻氮化 矽層11 8、金屬矽化層11 6及多晶矽層11 4，因而形成第 十圖所示的結構。於第十圖中，金屬矽化層116及多晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 406376 A7 B7 五、發明説明（） 矽層 1 14之導電層，係作為本發明之”位元線（1)丨1;- I 1 ne V’，並非作為一般元件中的閘極功能；至於第二圖 中，金屬矽化層16及多晶矽層14之導電層，是元件中 的閘極，在本發明中，其功能係作為”字元線0〇『(1-line)”。 接著，形成一介電層1 2 2 (例如氮化矽）於整個氧 化矽層3 4及氮化矽層11 8上面。以非向性蝕刻法（例如 活性離子蝕刻法）回蝕介電層 1 2 2 ’因而形成側隙間壁 (spacer )122A於閘極（其係由氮化矽層118、金屬矽化層 II 6及多晶石夕層11 4組成）之側壁上，如第Η--圖所示。 在整個側隙間壁1 2 2 A、氮化矽層11 8及氧化矽 層3 4上面，形成另一氧化矽層1 2 8。在本實施例中，由 於硼璃矽玻璃（BPSG)具有低回火（reflow)溫度，因而適 於作為氧化矽層1 2 8之材質。 使用傳統微影技術形成光阻層1 3 0於氧化矽層 1 2 8上以定義區域。以光阻層1 3 0為遮罩，蝕刻氧化矽層 1 28，因而形成第十二圖所示之結構。其中，側隙間壁1 22A 及氮化矽層11 8係作為自動對準接觸窗（SAC)蝕刻時之 用。 參閱第十二圖，形成摻雜多晶矽層14 0於前一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X'297d釐） (請先閱讀背面之注意事項再填寫本頁) .策- 經濟部智惡財產^肖工消費合作社印製 406376 A? B7 丘，發明説明（） 步驟所形成之結構上，以作為動態隨機存取記憶體電容 器之底部極板。於摻雜多晶石夕層140上面，以旋塗式玻 璃（S0G)技術旋塗介電層142(例如光阻材質或有機高分 子），並回蝕以露出摻雜多晶矽層140之表面，如第十三 圖所示。此介電層142也可以用蝴磷石夕玻璃（BPSG)來代 替。 回蝕摻雜多晶矽層140，直到暴露出氧化矽層 128’如第十四圖所示。於除去氧化矽層128及介電層142 之後，形成一薄介電層144於多晶矽層140上面。在本 實施例中’由於氧-氮-氧（0N0)堆疊層可以穩定的形成於 具有形狀之多晶矽表面，因此被用來作為薄介電層144 之材質。在此氧-氮-氧（0Μ0)堆疊層144中，其底層（及 氧化矽層）係由傳統熱氧化方法形成，再以低壓化學氣相 沈積法沈積氮化矽層作為中間層，最後以傳統熱氧化方 法形成頂層氧化矽。其它材質，例如T a2 〇5或其它高卩反值 材質也可以用來代替氧-氮-氧（0N0)。最後，形成一導電 層1 46於薄介電層1 44之表面，以作為動態隨機存取兮己 憶體電容器之頂層電極板。通常，係以摻雜多晶矽作為 導電層1 46之材質，其形成方法和摻雜多晶矽層i 4 成相同。 以上所述僅為本發明之較佳實施例而已，並非 用以限定本發明之申請專利範圍；凡其它未脫離本發明 本紙張尺度適用中1¾家標準（CNS ) A4規格（) -------袈 I ^---„---訂 * (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財4局段工消費合作社印契 406376 A7 B7 五、發明説明（） 所揭示之精神下所完成之等效改變或修飾，均應包含在 下述之申請專利範圍内。 (請先閱讀背面之注意事項再填寫本百； ----— 裝., 1T Printed by the Consumer Goods Cooperative of the Intellectual Property Field of the Ministry of Economic Affairs ---- V. Description of the Invention (Used for the alignment contact window (SAC) etching. Refer to Figure 7 to form the doped polycrystalline silicon layer 32 in Figure 6 Structure and etch back until the surface of the silicon oxide layer 28 is exposed. Next, a polycrystalline silicon contact window plug 32 is formed on the semiconductor substrate 10. The silicon oxide layer 34 is formed on the polycrystalline silicon contact window. Over the plug 32 and the oxidized layer 28. In this embodiment, borophosphosilicate glass is used as the material for oxidation. A photoresist layer 36 is formed on the oxidized layer 34 using a conventional lithography technique to define a contact window area The photoresist layer 36 is used as a cover, and the oxide layer 34 is etched and oxidized to form a bit line (bit-1 ine) to contact the window hole 38. The polycrystalline silicon contact window plug 32 is used as the end point detection ( end_ point), as shown in the eighth figure. It is worth noting that by etching the oxide polysilicon polysilicon contact window plug 32 and the silicon nitride layer 18, the contact hole 39 can be formed at the periphery. Area. Unlike traditional methods, with this & Ming, the bit line (bit-Une) contact window 38 and the peripheral contact window hole 39 can be formed at the same time. In the eighth figure, the depth of the contact window 38 is generally 0.1 micrometer 'and the depth of the peripheral contact window 39 is about 0.5 micrometer or more. When using CH3F / CHF3 / CF4's active plasma etching (R1E) makes it have a higher etch rate of S i 〇2 and S i 3 N 4; but it has a higher etch rate than Si Shi Xi and metal silicide (such as WS i). High (approximately greater than 5) • I choose 1 ± (that is, it has a lower engraving rate), so that it can achieve the purpose of simultaneously forming contact windows of different depths from 38 and the peripheral contact windows 39 at the same time. Please read the notes on the back before filling in this page) Bae--Ordered by the Ministry of Economic Affairs and the Intellectual Property Bureau of the Ministry of Economic Affairs & Co., Ltd. printed 406376 B7 V. Description of the invention (in addition to the contact window M opened by this month) The length (aSPeCt rati〇) is smaller than the traditional structure. The conventionally known technology does not make the plug's contact window size: 0.275 microns, deep " microns,] insert fjing first read leisurely, the attention of the back ¾ Refill this page) The aspect ratio is about 3. As for the contact window of the present invention (as shown in the eighth figure = shown in FIG. 38) ', its size is: 0. 25 microns, depth 0 "microns, and the length-to-width ratio of the caret is about 0-4. Therefore, the aspect ratio of the present invention is indeed smaller than the conventional one. Technical Reference Referring to the ninth figure, a doped polycrystalline silicon layer 114 is formed on the silicon oxide layer 34 and the polycrystalline silicon contact plug 32. In this embodiment, the two-inserted silicon layer 11 4 is a product of a conventional low-pressure chemical vapor deposition method (LpcVD) and is doped with phosphorus ions, and its concentration is about 5E20 atoms / cm3. Then, a metal silicide layer (s i 1 丨 c 丨 de) 丨 丨 6 is formed by a conventional metal silicide method. In general, the metal silicide layer 116 and the polysilicon layer 114 are collectively referred to as a polycide. It is worth noting that polycrystalline silicon silicides can be replaced by single-layer doped polycrystalline silicon. However, the latter generally has a large resistance value. A dielectric layer u 8 ′ is formed on the metallization layer 丨 6, such as silicon nitride. In this embodiment, the silicon nitride layer 118 is deposited by a conventional low pressure chemical vapor deposition (LPCVD) method. Printed by the Intellectual Property Department of the Ministry of Economic Affairs, Bureau of Industrial and Commercial Cooperatives, using traditional lithography technology to form a photoresist layer 120 on the silicon nitride layer 118 to define the gate region. With the photoresist layer 120 as a mask, the silicon nitride layer 118, the metal silicide layer 116, and the polycrystalline silicon layer 114 are etched, thereby forming the structure shown in FIG. In the tenth figure, the metal silicide layer 116 and the polycrystalline paper size are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 406376 A7 B7 V. Description of the invention () The conductive layer of the silicon layer 1 14 is used as the standard The "bit line (1) 丨 1;-I 1 ne V 'of the invention" is not a gate function in a general device; as for the second figure, the conductive layers of the metal silicide layer 16 and the polycrystalline silicon layer 14 are in the device In the present invention, the gate electrode functions as a "word line 0〇" (1-line). Next, a dielectric layer 1 2 (eg, silicon nitride) is formed on the entire silicon oxide layer 3 4 And the silicon nitride layer 11 8. The dielectric layer 1 2 2 ′ is etched back by a non-directional etching method (such as an active ion etching method), thereby forming a spacer 122A on the gate (which is made of silicon nitride Layer 118, metal silicide layer II 6 and polycrystalline silicon layer 11 4) on the side walls, as shown in Figure VII--Figure. Throughout the gap wall 1 2 2 A, silicon nitride layer 11 8 and silicon oxide Above the layer 3 4, another silicon oxide layer 1 2 8 is formed. In this embodiment, since borosilicate glass (BPSG) has a low reflow temperature, It is suitable as a material for the silicon oxide layer 1 2 8. The traditional photolithographic technique is used to form a photoresist layer 130 on the silicon oxide layer 1 2 8 to define a region. The photoresist layer 130 is used as a mask to etch and oxidize The silicon layer 1 28 forms the structure shown in Fig. 12. Among them, the side gap partition wall 1 22A and the silicon nitride layer 11 8 are used for the automatic alignment contact window (SAC) etching. See Fig. 12 The formation of a doped polycrystalline silicon layer 14 0 applies the Chinese National Standard (CNS) A4 specification (210X'297d centimeter) to the previous paper size (please read the precautions on the back before filling this page). Policy-Intellectual Property of the Ministry of Economic Affairs ^ Printed by Xiao Gong Consumer Cooperative 406376 A? B7 Yau, the structure of the invention () step is used as the bottom plate of the dynamic random access memory capacitor. On top of the doped polycrystalline silicon layer 140, Spin-on-glass (S0G) technology spin-coats a dielectric layer 142 (such as a photoresist material or an organic polymer) and etches back to expose the surface of the doped polycrystalline silicon layer 140, as shown in Figure 13. This dielectric layer 142 can also be replaced by Phosphophosphite glass (BPSG). Layer 140 until the silicon oxide layer 128 'is exposed as shown in FIG. 14. After removing the silicon oxide layer 128 and the dielectric layer 142, a thin dielectric layer 144 is formed on the polycrystalline silicon layer 140. In this embodiment 'Since the oxygen-nitrogen-oxygen (0N0) stacked layer can be formed stably on a polycrystalline silicon surface having a shape, it is used as a material of the thin dielectric layer 144. Here, the oxygen-nitrogen-oxygen (0M0) stacked layer 144 The bottom layer (and the silicon oxide layer) is formed by a conventional thermal oxidation method, and then a silicon nitride layer is deposited as an intermediate layer by a low-pressure chemical vapor deposition method, and finally a top silicon oxide is formed by the conventional thermal oxidation method. Other materials, such as T a2 05 or other high-inversion materials, can also be used instead of oxygen-nitrogen-oxygen (0N0). Finally, a conductive layer 146 is formed on the surface of the thin dielectric layer 144 as a top electrode plate of the dynamic random access memory capacitor. Generally, doped polycrystalline silicon is used as the material of the conductive layer 146, and the formation method is the same as that of the doped polycrystalline silicon layer i4. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; all other standards (CNS) A4 specifications () in the application of the paper standard of the present invention (CNS) A4 () ---- --- 袈 I ^ --- „--- Order * (Please read the precautions on the back before filling out this page) Seal of the Ministry of Economic Affairs, Smart Wealth, 4th Section, Industrial Cooperatives Cooperative Stamp 406376 A7 B7 V. Description of Invention () Equivalent changes or modifications made under the spirit of disclosure should be included in the scope of patent application below. (Please read the notes on the back before filling this one hundred;
、1T 經濟部智蒽財產局肖工消費合作社印製 用 一適 尺 張紙一本, 1T Printed by Xiao Gong Consumer Cooperative, Zhithan Property Bureau, Ministry of Economic Affairs
Ns C 一準 :標 -14 國 國 釐 公Ns C: Standard -14 countries