經濟部中央揉準局貝工消費合作社印装 2089TWF.DOC/005 A 7__4Q52M^ B7_____ 五、發明説明（丨） -， 本發明是有關於一種積體電路元件的製造方法，且特 別是有關於一種電荷儲存結構之製造方法。 在動態隨機存取記憶體(DRAM)中，一般利用半導體基 底上陣列的電容充電(charge)或放電(discharge)的型態來儲 存資料。通常，以放電形式的電容代表邏輯1，而充電形式 的電容代表邏輯〇之方式，將二進位(binary)之一獨立位元 (bit)儲存在單一電容。因此，電容中電荷的儲存量由記憶 電容之電極表面積、電極隔離的可靠度，以及在電荷儲存 電容間電容介電質的介電常數(dielectric constant)而決定。 記憶體中存取與讀寫動作，係以轉移場效電晶體(transfer FET)完成電荷儲存電容與位元線(bit line)之耦接，且藉由耦 接後電荷之移轉而執行。其中位元線與轉移FET源/汲極區 (source/drain)之一電極連接，而電荷儲存電容則與轉移FET 源/汲極區之另一電極相連接。字元線信號則供給轉移FET 之閘極，並經由轉移FET使電荷儲存電容之一電極與位元 線連接，而藉此電荷儲存電容與位元線間可有電荷轉移的 現象發生。 在單一的晶片（chip)中，爲增加資料儲存量’因此積體 電路記憶體的儲存密度亦有逐漸增加的傾向。而高密度記 憶體可提供較爲緊密的儲存結構，且對於可儲存相同量之 複數晶片而言，可以在單一晶片之高密度儲存結構上儲存 資料，勢i必較節省成本。通常，積體電路元件之密度，可 藉由減小連接線(wiring lines)、電晶體閘極Uate)的尺寸’ 或是積體電路之元件隔離區而增加。而減小電路結構元件 3 本紙張又度逋用中國國家橾丰（CNS > A4規格（210X297公釐） (請先Μ讀背面之注意事項再填寫本頁) 2089TWF.DOC/005 A7 B7 經濟部中央標準局員工消费合作社印製 五、發明説明（>) … 的尺寸一般則需依據積體電路元件製造方法逐漸縮減之設 計規則（design rules)。 在傳統的平坦化電容設計中，應用縮減的設計規則會減 少電荷儲存電容的電荷儲存量。而電容電荷量的減少會引 發一連串的問題’包括由較高的敏感度導致的位能損失而 引起的哀退機制與漏電流(leakage current)，而此高敏感度 導因之電荷損失將引起DRAM需要較爲頻繁的再補充循環 (refresh cycle) ’而再補充的步驟對於資料儲存及讀取動作 爲不良的。另外，儲存電荷逐漸縮減的位準，則需要更爲 複雜的資料處理設計或敏感度更高的電荷讀出放大器 (charge sense amplifier)。因此，現今的 DRAM 需要在 DRAM 逐漸縮減的基底表面積中增加電容値(capacitance)。而所推 出一連串複雜的電容結構，其具有三度空間電荷儲存表 面，特別是在高度量化及高產率均需兼備的條件下，欲形 成複雜電容結構之方法爲困難的。 在電荷儲存電容上形成半球顆粒複晶矽（Hemispherical grained polysilicon, HSG-Si)爲近來增進DRAM電容値的頗 常使用的方法。大部分的DRAM電容由傳統的複晶矽構成 電容的兩電極，再加上介電質而構成。而當傳統複晶矽被 製成平坦式的形狀之時，基本上下電極的表面爲平滑的。 而半球顆粒複晶矽是爲複晶矽中一種特別的形式，其具有 一粗糙的_表面，且當小心地控制沈積在電極上的HSG-Si 時，其確可增加下電極的表面積·。因此在電極上提供一 HSG-Si層，則DRAM電荷儲存電容値可增加約1·8倍。 4 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） ' " 1 J— I ij.— n - /1 裝— I— I I 訂— I— I I 1^ I -· (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印製 2089TWF.DOC/005 405259 五、發明説明ο ) 然若想在利用HSG之餘，再進一步增加電容表面積， 則必須在沈積HSG·前在基板上先形成柱狀、鰭狀(fin)或凹 槽(cavity)結構等，以增加下電極與介電質的接觸面積，藉 此增加電容値。 本寧明的主要目的，就是在提供一種電荷儲存結構，其 除了利用HSG的沈積來增加電容値外，同時更形成凹槽以 增加下電極的表面積。而凹槽的蝕刻深度，是利用沈積雙 層複晶矽層時’於雙層複晶矽層中成長的原始氧化層 (native oxide)作爲蝕刻終點(etch stopper)，加以控制凹槽的 深度。並解決習知技藝中，電荷儲存結構未具備有控制凹 槽深度的蝕刻終點，而造成沈積厚度不均的問題。 爲達上述之目的，本發明提供一種電荷儲存結構之製造 方法，其包括下列步驟：首先，在MOS基板上形成一絕緣 層，定義絕緣層形成一接觸窗，暴露出一源/汲極區中之一。 接著，形成一第一複晶矽層，覆蓋住接觸窗與絕緣層，且 與MOS基板上源/汲極區之一電性耦接。其中，在形成第 一複晶矽層後，會在第一複晶矽層表面自然生成一原始氧 化層。之後，在原始氧化層上形成一第二複晶矽層，再定 義第二複晶矽層，而在第二複晶矽層形成一凹槽。其中凹 槽位於接觸窗的上方，在此定義第二複晶矽層的步驟由微 影蝕刻法進行，而蝕刻第二複晶矽層係以原始氧化層作爲 蝕刻終點。續在第二複晶矽層與凹槽表面形成一半球顆粒 複晶矽層，接著，定義第一複晶矽層、第二複晶矽層與半 球顆粒複晶矽層，以形成電荷儲存電極結構之一下電極。 5 本紙張尺度逋用中國固家檁準（C.NS ) A4规格（2丨〇χ297公釐） <請先聞讀背面之注$項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 2089TWF.DOC/00 5 ρ^η__405259__β7 五、發明説明（詧） 在第一複晶矽層、第二複晶矽層與半球顆粒複晶矽層暴露 出的表面形成一介電層。最後，在介電層的表面上形成一 第三複晶矽層，以構成電荷儲存電容之一上電極。而本發 明中之複晶矽層，包括半球顆粒複晶矽層皆摻有雜質，以 促進複晶矽層的導電性。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1Α圖至第1D圖係顯示根據本發明較佳實施例電荷 儲存結構製造方法之流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 10 :基底 11 :場氧化層 12 :閘極氧化層 13 :閘極複晶矽層 14 :間隙壁 15、16 :源/汲極區 17 :絕緣層 19、21、25 :導電層 20 ·’原始氧化層 23 :半球顆粒複晶矽層 24 :介電層 實施例 6 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X29*7公釐） 丨.--..---^--!‘1裝丨------訂------線 (請先閲讀背面之注意事項再填寫本頁) 24&§好5>贫0 0 5 A7 B7 _ 五、發明説明（（） 第1A圖至第1D圖所示，爲根據本發明一較佳實施例 電荷儲存結構製造方法之流程剖面圖。 請參照第1A圖。首先將一矽基底1〇表面進行熱氧化 製程，例如以矽的局部氧化(LOCOS)技術來達成，因而形 成場氧化層11，其厚度例如爲3000A。接著，再將矽基底 10進行熱氧化製程，以形成一閘極氧化層12，其厚度例如 爲150A。然後，利用一化學氣相沈積法(CVD)或低壓化學 氣相沈積法(LPCVD)，在閘極氧化層12上沈積一複晶矽層 13 ’厚度例如爲2〇0〇A。爲了提高複晶矽層的導電度，可 將磷離子植入複晶矽層中。之後，利用傳統微影鈾刻 (photolithography)技術定義（pattern)複晶砂層，而形成閘 極。之後，再沈積一氧化層，經回蝕刻後，作爲保護複晶 矽層的間隙壁14。接著，例如以砷離子植入到基底中，以 形成源極/汲極區丨5、16,在此步驟中，以閘極作爲罩幕層， 而離子植入劑量約在1*1〇15 atoms/cm2，能量約爲70KeV。 再於上述步驟形成的M0S基板上形成一絕緣層17，例 如以CVD法沈積氧化物，厚度約爲2000-4000A。接著定義 絕緣層17，在絕緣層17中形成一接觸窗18，暴露出源/汲 極區15、16之一。例如以乾触刻法餓刻絕緣層，而形成接 觸窗18。 請參照第1B圖。接著’在接觸窗中18與絕緣層17表 面形成一導電層19 ’例如爲摻有雜質的複晶矽層，而導電 層19與M0S基板的源/汲極區〗5、16之一電性親接。之 後，當_電層19表面暴露在氧氣的環境下，會自然生成一 7 — 7.---：------— 1 裝—--.---訂------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央搮率局貞工消费合作社印裝 ^紙張尺^用中國#標牟(〇阳）八4規格（210父297公釐） 經濟部中央揉準局貝工消费合作社印製 2089TWF.DOC/00 5 /^η405259 Β7 五、發明説明（‘） 原始氧化層20，而原始氧化層20爲一薄膜。接著’再於原 始氧化層表面形成一導電層21 ’例如爲摻有雜質的複晶矽 層。 請參照第1C圖。定義導電層21，在導電層21形成一 凹槽22，而凹槽22位於接觸窗的上方，例如以乾蝕刻法蝕 刻導電層21，以原始氧化物爲蝕刻終點，暴露出原始氧化 層表面，形成如第1C圖所示之導電層21a。接著，並在暴 露出的原始氧化層表面與導電層21a表面形成一半球顆粒 複晶矽層23(HSG)。而半球顆粒複晶矽層18可以任何已知 的方法形成，例如以矽甲烷爲氣體來源之低壓化學氣相沈 積法沈積HSG-Si，反應溫度則控制在約550-595°C，而最 後由HSG-Si成核生長形成HSG-Si顆粒不規則表面。再經 熱擴散或離子植入的方式將雜質磷離子，趨入半球顆粒複 晶砂層23。 接著，定義導電層19、原始氧化層20、導電層22以及 半球顆粒複晶矽層23a，而形成如第1D圖所示之導電層 19a、原始氧化層20a、導電層22b以及半球顆粒複晶矽層 23a，構成本發明電荷儲存結構之下電極。 再於經定義後的下電極表面形成一介電層24,例如爲 氧化物-氮化物(NO)，氧化物-氮化物-氧化物(ΟΝΟ)，或介 電常數較高之氧化钽Ta205。之後再於介電層24上形成一 導電層25，例如爲在約620°C的溫度範圍下形成摻有磷離 子雜質的複晶矽，磷離子摻雜溫度控制在880°C，且沈積厚 度約在2000埃左右，以構成電荷儲存結構之一上電極。 t® ( cns ) A4^ ( 210Χ297^ΙΠ ~ " ~ —^ϋ m^i ^ ml· —^n V ··~ (請先聞讀背面之注意事項再填寫本頁} 2089iTM/E^DOC/005405259 A7 B7 五、發明説明（7) 本發明利用二導電層，即導電層19與導電層21形成之 間所自然生成的原始氧化物，作爲蝕刻導電層21形成凹槽 的蝕刻終點，控制凹槽的蝕刻深度，藉以增進後續步驟階 梯覆蓋與薄膜沈積的均勻度和品質。而凹槽與半球顆粒複 晶矽層的形成，提供下電極較大的表面積，而可增加電荷 儲存結構的電容値。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 1‘------------裝-7--.---訂------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐）Printed by the Central Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 2089TWF.DOC / 005 A 7__4Q52M ^ B7_____ V. Description of the Invention (丨)-, The present invention relates to a method for manufacturing integrated circuit components, and in particular to a method for manufacturing integrated circuit components Manufacturing method of charge storage structure. In a dynamic random access memory (DRAM), a capacitor charge or discharge type of an array on a semiconductor substrate is generally used to store data. Generally, a capacitor in a discharge form represents a logic 1 and a capacitor in a charge form represents a logic 0, and an independent bit of a binary is stored in a single capacitor. Therefore, the amount of charge stored in the capacitor is determined by the electrode surface area of the storage capacitor, the reliability of the electrode isolation, and the dielectric constant of the capacitor dielectric between the charge storage capacitors. The access and read / write operations in the memory are performed by using a transfer FET to complete the coupling between the charge storage capacitor and the bit line, and performed by the transfer of the charge after the coupling. The bit line is connected to one electrode of the source / drain region of the transfer FET, and the charge storage capacitor is connected to the other electrode of the source / drain region of the transfer FET. The word line signal is supplied to the gate of the transfer FET, and one of the electrodes of the charge storage capacitor is connected to the bit line through the transfer FET, so that a charge transfer between the charge storage capacitor and the bit line occurs. In a single chip, in order to increase the data storage amount ', the storage density of the integrated circuit memory also tends to gradually increase. The high-density memory can provide a more compact storage structure, and for storing multiple wafers of the same amount, data can be stored on a single-chip high-density storage structure, which is bound to save costs. Generally, the density of integrated circuit components can be increased by reducing the size of wiring lines, transistor gate Uate, or the component isolation area of the integrated circuit. And reduce the circuit structure components 3 This paper has been re-used by China National Fengfeng (CNS > A4 size (210X297 mm) (Please read the precautions on the back before filling out this page) 2089TWF.DOC / 005 A7 B7 Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 5. The size of the invention description (>) is generally based on the design rules of the integrated circuit component manufacturing method, which is gradually reduced. In the traditional flat capacitor design, the application Reduced design rules will reduce the charge storage capacity of the charge storage capacitor. The reduction of the charge capacity of the capacitor will cause a series of problems' including the retreat mechanism and the leakage current caused by the potential energy loss caused by the higher sensitivity ), And the loss of charge due to this high sensitivity will cause the DRAM to require more frequent refresh cycles (refresh cycle), and the replenishment steps are bad for data storage and read operations. In addition, the stored charge is gradually reduced Level requires more complex data processing designs or more sensitive charge sense amplifiers. Therefore, today, DRAM needs to increase the capacitance of the DRAM's shrinking substrate surface area. A series of complex capacitor structures have been introduced that have a three-degree space charge storage surface, especially under the conditions of both high quantification and high yield. It is difficult to form a complex capacitor structure. The formation of hemispherical grained polysilicon (HSG-Si) on charge storage capacitors is a commonly used method to increase the capacity of DRAM capacitors. Most DRAM capacitors are Conventional polycrystalline silicon is composed of two electrodes of a capacitor, and a dielectric is added. When the conventional polycrystalline silicon is made into a flat shape, the surface of the lower electrode is basically smooth. Hemispherical particles are polycrystalline Silicon is a special form of polycrystalline silicon, which has a rough surface, and when the HSG-Si deposited on the electrode is carefully controlled, it can indeed increase the surface area of the lower electrode. Therefore, it is provided on the electrode With an HSG-Si layer, the DRAM charge storage capacitance can be increased by about 1.8 times. 4 This paper size is applicable to China National Standard (CNS) Α4 specification (210X297 (Mm) '" 1 J— I ij.— n-/ 1 Pack — I— II Order — I— II 1 ^ I-· (Please read the notes on the back before filling this page) Printed by the Bureau Cooperative Consumer Cooperative 2089TWF.DOC / 005 405259 5. Description of the invention ο) However, if you want to further increase the surface area of the capacitor in addition to HSG, you must first form columnar and fins on the substrate before depositing HSG. Fin or cavity structure to increase the contact area between the lower electrode and the dielectric, thereby increasing the capacitance 値. The main purpose of Ben Ningming is to provide a charge storage structure that, in addition to using HSG deposition to increase the capacitance 値, also forms grooves to increase the surface area of the lower electrode. The etching depth of the grooves is controlled by controlling the depth of the grooves by using the native oxide grown in the double-layered polycrystalline silicon layer when the double-layered polycrystalline silicon layer is deposited as an etch stopper. It also solves the problem that the charge storage structure does not have an etching end point for controlling the depth of the groove in the conventional technique, which causes the uneven thickness of the deposition. To achieve the above object, the present invention provides a method for manufacturing a charge storage structure, which includes the following steps: First, an insulating layer is formed on a MOS substrate, the insulating layer is defined to form a contact window, and a source / drain region is exposed. one. Next, a first polycrystalline silicon layer is formed to cover the contact window and the insulating layer, and is electrically coupled to one of the source / drain regions on the MOS substrate. Among them, after forming the first polycrystalline silicon layer, an original oxide layer is naturally formed on the surface of the first polycrystalline silicon layer. After that, a second polycrystalline silicon layer is formed on the original oxide layer, the second polycrystalline silicon layer is defined, and a groove is formed in the second polycrystalline silicon layer. The recess is located above the contact window. Here, the step of defining the second polycrystalline silicon layer is performed by a lithographic etching method, and the etching of the second polycrystalline silicon layer uses the original oxide layer as an etching end point. Continue to form a hemispherical particle polycrystalline silicon layer on the second polycrystalline silicon layer and the groove surface, and then define a first polycrystalline silicon layer, a second polycrystalline silicon layer, and a hemispherical particle polycrystalline silicon layer to form a charge storage electrode. Structure one of the lower electrodes. 5 This paper uses China Gujia Standard (C.NS) A4 specification (2 丨 〇χ297mm) < Please read the note on the back before filling in this page) Employees' Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printed 2089TWF.DOC / 00 5 ρ ^ η__405259__β7 V. Description of the Invention (ii) A dielectric layer is formed on the exposed surfaces of the first polycrystalline silicon layer, the second polycrystalline silicon layer, and the hemispherical particle polycrystalline silicon layer. Finally, a third polycrystalline silicon layer is formed on the surface of the dielectric layer to constitute one of the upper electrodes of the charge storage capacitor. The polycrystalline silicon layer in the present invention, including the hemispherical granular polycrystalline silicon layer, is doped with impurities to promote the conductivity of the polycrystalline silicon layer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1A Figures 1 to 1D are cross-sectional views showing the flow of a method for manufacturing a charge storage structure according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 10: substrate 11: field oxide layer 12: gate oxide layer 13: gate polycrystalline silicon layer 14: barrier wall 15, 16: source / drain region 17: insulation Layers 19, 21, 25: Conductive layer 20 · 'Original oxide layer 23: Hemispherical particle polycrystalline silicon layer 24: Dielectric layer Example 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210X29 * 7 mm)丨 .--..--- ^-! '1 Pack 丨 ------ Order ------ Line (Please read the precautions on the back before filling out this page) 24 & § 好 5 > Lean 0 0 5 A7 B7 _ V. Description of the invention (() Figures 1A to 1D are cross-sectional views of a method for manufacturing a charge storage structure according to a preferred embodiment of the present invention. Please refer to Figure 1A. First The surface of a silicon substrate 10 is subjected to a thermal oxidation process, for example, by the local oxidation of silicon (LOCOS) technology, so a field oxide layer 11 is formed, whose thickness is, for example, 3000 A. Then, the silicon substrate 10 is further subjected to a thermal oxidation process. A gate oxide layer 12 is formed to a thickness of, for example, 150 A. Then, a chemical vapor deposition (CVD) method or a low pressure chemical vapor deposition method is used. (LPCVD), a polycrystalline silicon layer 13 ′ is deposited on the gate oxide layer 12 with a thickness of, for example, 2000 A. In order to improve the conductivity of the polycrystalline silicon layer, phosphorus ions can be implanted into the polycrystalline silicon layer. Then, the gate is formed by patterning a polycrystalline sand layer using a conventional photolithography technique, and then an oxide layer is deposited and etched back to serve as a spacer 14 for protecting the polycrystalline silicon layer. For example, arsenic ions are implanted into the substrate to form source / drain regions. 5,16. In this step, the gate electrode is used as the mask layer, and the ion implantation dose is about 1 * 1015 atoms. / cm2, the energy is about 70KeV. Then, an insulating layer 17 is formed on the MOS substrate formed in the above steps. For example, an oxide is deposited by CVD to a thickness of about 2000-4000 A. Then, an insulating layer 17 is defined and formed in the insulating layer 17 A contact window 18 exposes one of the source / drain regions 15, 16. For example, the insulating layer is formed by dry-contact engraving to form the contact window 18. Please refer to FIG. 1B. Then, 'the contact window 18 and the insulation A conductive layer 19 ′ is formed on the surface of the layer 17, such as a polycrystalline silicon layer doped with impurities, and conductive 19 is electrically connected to one of the source / drain regions of the M0S substrate 5 and 16. After that, when the surface of the electrical layer 19 is exposed to the environment of oxygen, a 7 — 7 .---:- ----— 1 Pack —--.--- Order ------ line (Please read the notes on the back before filling out this page) Printed by the Zhengong Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs ^ Paper ruler ^ Used in China # 标 牟 (〇 阳) 8 specifications (210 fathers 297 mm) Printed by the Central Labor Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives 2089TWF.DOC / 00 5 / ^ η405259 Β7 V. Description of the invention (') Original The oxide layer 20 is a thin film. Next, a conductive layer 21 is formed on the surface of the original oxide layer, such as a polycrystalline silicon layer doped with impurities. Please refer to Figure 1C. Defining the conductive layer 21, a groove 22 is formed in the conductive layer 21, and the groove 22 is located above the contact window. For example, the conductive layer 21 is etched by dry etching, and the original oxide is used as the end point to expose the surface of the original oxide layer. A conductive layer 21a is formed as shown in FIG. 1C. Next, a hemispherical particle polycrystalline silicon layer 23 (HSG) is formed on the surface of the exposed original oxide layer and the surface of the conductive layer 21a. The hemispherical granular polycrystalline silicon layer 18 can be formed by any known method, for example, HSG-Si is deposited by low pressure chemical vapor deposition using silicon methane as a gas source. The reaction temperature is controlled at about 550-595 ° C. HSG-Si nucleates and grows to form irregular surface of HSG-Si particles. Impurity phosphorus ions are then introduced into the hemispherical particle polycrystalline sand layer 23 by thermal diffusion or ion implantation. Next, the conductive layer 19, the original oxide layer 20, the conductive layer 22, and the hemispherical particle polycrystalline silicon layer 23a are defined to form the conductive layer 19a, the original oxide layer 20a, the conductive layer 22b, and the hemispherical particle multiple crystal as shown in FIG. 1D. The silicon layer 23a constitutes the lower electrode of the charge storage structure of the present invention. A dielectric layer 24 is further formed on the defined lower electrode surface, such as oxide-nitride (NO), oxide-nitride-oxide (ONO), or tantalum oxide Ta205 with a higher dielectric constant. Then, a conductive layer 25 is formed on the dielectric layer 24, for example, to form a polycrystalline silicon doped with phosphorus ion impurities at a temperature range of about 620 ° C, the phosphorus ion doping temperature is controlled at 880 ° C, and the deposition thickness is About 2000 angstroms to form one of the upper electrodes of the charge storage structure. t® (cns) A4 ^ (210 × 297 ^ ΙΠ ~ " ~ — ^ ϋ m ^ i ^ ml · — ^ n V ·· ~ (Please read the precautions on the back before filling in this page) 2089iTM / E ^ DOC / 005405259 A7 B7 V. Description of the invention (7) The present invention uses the two conductive layers, that is, the original oxide naturally generated between the formation of the conductive layer 19 and the conductive layer 21, as the etching end point for etching the conductive layer 21 to form a groove, and controls The depth of the groove is etched to improve the uniformity and quality of step coverage and film deposition in the subsequent steps. The formation of the polycrystalline silicon layer of the grooves and hemispherical particles provides a larger surface area of the lower electrode, which can increase the capacitance of the charge storage structure値. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. 1 '------------ Install-7 --.--- Order ------ Line (please read the notes on the back before filling this page) This paper printed scale applies China National rub quasi (CNS) A4 size (210X297 mm)