WO2000062550A1 - Video processing device and method, and medium - Google Patents
Video processing device and method, and medium Download PDFInfo
- Publication number
- WO2000062550A1 WO2000062550A1 PCT/JP2000/002406 JP0002406W WO0062550A1 WO 2000062550 A1 WO2000062550 A1 WO 2000062550A1 JP 0002406 W JP0002406 W JP 0002406W WO 0062550 A1 WO0062550 A1 WO 0062550A1
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- WO
- WIPO (PCT)
- Prior art keywords
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- video
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- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/174—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
Definitions
- the present invention relates to a video processing apparatus and method, and a medium, and more particularly, to a video processing apparatus and method suitable for decoding a compressed video signal, and a medium.
- a suitable address allocation is performed. Pretend. For example, in the frame memory shown in Fig. 1A, when one line at the top of the screen is displayed, the address of 000000 to 0719 (the data of 720 pixels) is displayed. ), It is possible to read continuously, so that the occurrence of page misses can be minimized.
- page miss refers to DRAM (Dynami c Random Access Memory) This is the time required to precharge the sense amplifiers provided in the memory such as the memory (thus, during precharging, processing such as data reading cannot be performed). .
- video data stored in frame memory is transmitted in macroblock units, and decoding is performed in macroblock order.
- One Y-macro block has one line power of 16 pixels (hence 16 bytes) and consists of 16 line powers. Therefore, for example, in the case of the first Y macro block, the first line is address 0000 to 015, and the second line is address 0720 to 07.
- the address is divided and stored (not as a single address), for example, addresses 144 to 450.
- a screen of Standard Definition Television (SDTV) or a screen of High Definition Television (HDTV) may be transmitted.
- SDTV Standard Definition Television
- HDTV High Definition Television
- an SDTV screen program and an HDTV screen program may be multiplexed and transmitted on one channel.
- the channel of the program on the SDTV screen is switched to the channel of the program on the HDTV screen.
- the sequence layer is defined as the highest layer.
- the picture size / picture rate is the same.
- a sequence header is sent. The sequence header describes the picture size / disc ratio, picture rate, and the like.
- one Y macro block is composed of 16 lines, each time one line is read, a page miss occurs. That is, every time one Y macro block is read, 16 page misses are generated. Also, in the chroma (Cb, Cr), one macroblock consists of eight lines, each consisting of 8 bytes, so that one Cb (Cr) macroblock is used. Each time a packet is read, eight page misses will occur.
- the sequence layer of the MPEG system is a stream in which the picture size and the picture rate are the same.
- the sequence header is at least GOP (G r opuO fPicture)
- the force that can be applied to the period; the period of the sequence header is not determined. Therefore, the maximum sequence length is one video program. For this reason, conventionally, for example, when switching a satellite broadcast channel, it takes a long time to detect a sequence header, and a considerable waiting time is required before reproduction is started. May be required.
- Another object of the present invention is to estimate the sequence header information and start decoding if the sequence header information of the MPEG stream is not detected, so that the MPEG stream is started. It is an object of the present invention to provide a video processing apparatus and a method capable of immediately decoding an image. Disclosure of the invention
- Figs. 15A and 15B are dummy blocks 13 of memory 1 14 1 and the BBB chain 1332
- Fig. 16 is a flowchart to explain the processing operation of the decoder 100
- Figs. 17A to 17C show the media.
- FIG. 3 is a block diagram showing a more detailed configuration of the decoding unit 12 shown in FIG.
- the video data output from the demultiplexer 11 is input to the variable length decoder 31 of the decoder 12.
- the variable-length decoding unit 31 performs variable-length decoding on the input video data, performs the quantization step and the video data to the inverse quantization unit 32, and outputs the motion vector to the motion compensation prediction unit 3. Output to 5 respectively.
- the inverse quantization unit 32 inversely quantizes the video data that has been subjected to the variable length coding based on the quantization step supplied from the variable length coding unit 31.
- the inversely quantized video data is stored in the cache memory 7 via the controller 14.
- Writing data to frame memory 5 and reading data from frame memory 5 overnight are performed in macroblock units.
- One Y-macro block is composed of 16 ⁇ 16 pixel forces, so it is composed of 256-byle data.
- next Y macro block to be read is assigned to address 0 2 56 6 No to 0 5 11, and the next Y macro block to be read is assigned to Addresses are successively allocated and stored in ascending order, such as address 0 5 12 to 0 7688.
- MA— 3 MA_0 + A_w + 1
- MA-2, MA-3 which overlaps with the macroblock MA-m, is calculated according to the following equation. Is calculated.
- MA—0—h indicates the number of horizontal blocks at the portion where the macroblock .MA—m and the macroblock MA—0 overlap
- MA—0_V is the macroblock. At the point where MA m and macro block MA 0 overlap. Indicates the number of direct lines. Other descriptions have the same meaning.
- DRAMs and the like are provided with two banks, and data writing and reading are performed by switching the banks.
- writing is performed alternately in different banks for each horizontal line. Therefore, as shown in Fig. 6, when writing is performed using two banks 0 and 1, data of one horizontal line of macro block MA-0 is read from non-zero.
- the data of one horizontal line of the macro block MA-2 is read out from the bank 1 and the data of the one horizontal line of the macro block MA-1 is read from non-k0. Data is read out one night, and then the process of reading one horizontal line of macro block MA-3 from non-link 1 is repeated.
- the video data is re-transferred from the cache memory 7 to the frame memory 5; however, from the cache memory 7, the image data for display different from the frame memory 5 is displayed.
- the data may be transferred to a frame memory for scaling (DRAM).
- the MPEG decoder 12 decodes the MPEG stream, and the MPEG decoder 12 outputs a stream of digital video data.
- the output of the MPEG decoder 12 is supplied to the display 15 via the display processing unit 13. As a result, a screen based on the MPEG stream is displayed on the display 15.
- the MPEG decoder 12 When decoding an MPEG stream by the MPEG decoder 12, it is necessary to first set the image size, aspect ratio, and the like. This information can be detected by the Sequence-Header. However, it may take some time to detect the sequence header.
- the sequence header sends information such as picture size, aspect ratio, frame rate, VBV buffer size, and quantization matrix.
- the vertical image size is estimated using the slice information.
- macro block information horizontal
- the image size in the direction is estimated.
- the aspect ratio is estimated using the estimated vertical image size and horizontal image size.
- the image size and aspect ratio estimated by the sequence header estimating circuit 16 are sent to the display processing circuit 13, and the sequence header estimating circuit 16.
- the display screen is set according to the estimated image size ratio.
- VBV—Buf fer—Size The size of the virtual buffer (VBV) for controlling the amount of generated code.
- the information on the number of pixels in the vertical direction of the video (Ver cal_Size—Value) can be estimated from the slice information.
- FIG. 9 shows the configuration of a slice in one picture.
- one picture is divided into multiple slices.
- a slice start code (Slice_Start_Code), which is a synchronization code indicating the start of the slice layer, is inserted at the beginning of each slice.
- This slice start code is indicated by a hexadecimal number “0 0 0 0 0 1 0 1 to AF”, and the last byte of the code (4th, “0 1 to AF ”) indicates the vertical position of the slice in hexadecimal.
- the fourth byte of the slice start code corresponds to the vertical position of the slice, which is the same number of lines on the same line. Becomes
- the output of the slice start code detector 43 is sent to the fourth byte extractor 44.
- the fourth note extraction unit 44 extracts the fourth note information of the slice start code.
- the output of the bit extraction unit 44 is sent to the vertical size register 45.
- the head of one picture can be detected.
- the vertical size register 45 is reset. Then, it is determined whether the slice start code is detected by the slice start code detection unit 43.
- the fourth byte information of the slice start code is extracted by the bit extraction unit 44.
- the information of the fourth byte of the slice start code is supplied to the register 45.
- the information of the register 45 is used as the information of the number of pixels in the vertical direction, and the vertical size register 4 is used. Incorporated in 6.
- the slice start code extends from the beginning to the end of the picture.
- the detection section 43 detects the slice start code.
- the fourth byte oil discharge section 44 detects the value of the fourth zone. Is extracted and taken into the vertical size register 45 to obtain an estimated value of the number of pixels in the vertical direction from the value of the vertical size register 46.
- the macro mouth address increment is a VLC (Variable Length Code) indicating the macro block to be skipped, which is "1" for a normal adjacent macro block. If there are macroblocks to be skipped, the value is added by the number of skipped macroblocks.
- VLC Very Length Code
- an input terminal 51 is supplied with an MPEG stream.
- the slice start code (Slice — Start — Code) in the MPEG stream is detected by the slice start code detection section 52, and the macro block address increment (Slope — Start — Code) is detected.
- the slice code detecting section 52 detects the leftmost slice of one line, the register 55, the registers 58A, 58B,..., the horizontal size register 61 are cleared. Will be rearranged. Then, the macro block address increment detecting section 53 detects a macro block address (Increment) force.
- This macro block address increment indicates the skip information of the macro block, and the increment value corresponding to “1” to “33” is the variable length code. It is written in. If the macro block address increment force is 33 or more, macro block escape is also referred to.
- the output of G53 is supplied to the VLC decoding unit 54.
- the VLC decoding unit 54 decodes the value of the macro block address increment.
- the output of the VLC decoding unit 54 is supplied to the adder 56.
- the output of the register 55 is supplied to the adder 56.
- the output of the decoded macro block detector 57 is supplied to the register 55.
- the adder 56 When it is detected from the output of the decoded macroblock detector 57 that the macroblock has been decrypted, the adder 56 generates the macroblock address signal of the present macroblock.
- the value of the macro block is added to the value of the previous macro block address increment, and the value of the macro block address increment is accumulated. As a result, the accumulated value of the macroblock addressless increment in each slice of the same horizontal line can be obtained.
- the output of register 55 is supplied to registers 58A, 58B, ....
- the registers 58 A, 58 B,... fetch the accumulated values of the macro block address increments in each slice when there are multiple slices in the horizontal direction. It is a thing.
- the outputs of the slice start code detection section 52 are supplied to the registers 58A, 58B,. Based on the output of the slice start code detection unit 52, the accumulated value of the macro block address increment is stored in the registers 58A, 58B, ... for each slice. It is captured.
- the output of the adder 59 is supplied to the multiplier 50.
- the multiplier 50 is a macro The number of blocks is multiplied by the size of the macroblock to calculate the number of pixels in the horizontal direction. In other words, the multiplier 50 multiplies the number of macroblocks by the horizontal size of the macroblock, so that the number of pixels in the horizontal direction per picture is! ? Will be issued. The number of pixels in the horizontal direction obtained in this way is supplied to the horizontal size register 61.
- the memory 117 stores a decoding program and a data transfer processing program for decoding the MPEG audio data stored in the memory 114 at the timing of the supplied message. .
- the CPU 112 decodes the MPEG audio data stored in the memory 114 at the timing of the supplied message, and re-decodes the decoded data to the memory 114.
- the CPU 112 reads the overnight transfer processing program.
- the decoded MPEG audio data described in the memory 114 is transferred to the output buffer 118.
- the power is "0N"
- the memory data stored in memory 114 is stored in advance and the output data of "0" is output. Transferred to buffer 1 18.
- an "F” message is transmitted to the decoding program and the data transfer processing program.
- This "F” message indicates that "do not start decoding", and upon receiving this message, the CPU 112 sends the MPEG audio data stored in the memory 114 to the MPEG audio data. Start decryption. That Thereafter, an "N” message is sent to the decoding program and the data transfer processing program (T3). This "N” message indicates “do not control decoding", and according to this message, the CPU 112 continues decoding.
- Fig. 15B shows MPEG audio data after decoding
- step S 11 when the user operates the input unit 11 1 to turn on the power of the decoder 100, the CPU 11 2 connects the memory 11 15 to the AC link. Read and execute the program.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00915506A EP1089567A4 (en) | 1999-04-13 | 2000-04-13 | MEDIUM, DEVICE AND METHOD FOR VIDEO PROCESSING |
US09/719,452 US7110663B1 (en) | 1999-04-13 | 2000-04-13 | Video processing apparatus and method for allocating addresses to data of macroblocks and storing the same, and medium containing a program for performing such method |
US11/494,723 US20060263069A1 (en) | 1999-04-13 | 2006-07-27 | Video processing apparatus and method for allocating addresses to data of macroblocks and storing the same, and medium containing a program for performing such method |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11/105255 | 1999-04-13 | ||
JP10525599A JP4029520B2 (ja) | 1999-04-13 | 1999-04-13 | ビデオ復号化装置及び方法 |
JP12264799A JP4171949B2 (ja) | 1999-04-28 | 1999-04-28 | 情報処理装置および方法、並びに提供媒体 |
JP11/122647 | 1999-04-28 | ||
JP11/153797 | 1999-06-01 | ||
JP15379799A JP2000348168A (ja) | 1999-06-01 | 1999-06-01 | 画像処理装置および方法、並びに媒体 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/494,723 Division US20060263069A1 (en) | 1999-04-13 | 2006-07-27 | Video processing apparatus and method for allocating addresses to data of macroblocks and storing the same, and medium containing a program for performing such method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000062550A1 true WO2000062550A1 (en) | 2000-10-19 |
Family
ID=27310434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/002406 WO2000062550A1 (en) | 1999-04-13 | 2000-04-13 | Video processing device and method, and medium |
Country Status (5)
Country | Link |
---|---|
US (2) | US7110663B1 (ja) |
EP (1) | EP1089567A4 (ja) |
KR (1) | KR100767611B1 (ja) |
CN (1) | CN1140125C (ja) |
WO (1) | WO2000062550A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7852343B2 (en) | 2004-04-15 | 2010-12-14 | Panasonic Corporation | Burst memory access method to rectangular area |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100356779C (zh) * | 2003-12-24 | 2007-12-19 | 瑞昱半导体股份有限公司 | 能够提升影像处理效率的内存储存方法 |
US9560367B2 (en) * | 2004-09-03 | 2017-01-31 | Nokia Technologies Oy | Parameter set and picture header in video coding |
CN100397903C (zh) * | 2004-12-21 | 2008-06-25 | 北京中星微电子有限公司 | 视频编解码过程中宏块数据读取的方法 |
US8773328B2 (en) * | 2005-02-12 | 2014-07-08 | Broadcom Corporation | Intelligent DMA in a mobile multimedia processor supporting multiple display formats |
CN1949826B (zh) * | 2005-10-12 | 2010-06-23 | 宏正自动科技股份有限公司 | 数字影像数据处理装置 |
JP4900470B2 (ja) * | 2007-02-22 | 2012-03-21 | 富士通株式会社 | 動画像符号化装置および動画像符号化方法 |
KR101086434B1 (ko) * | 2007-03-28 | 2011-11-25 | 삼성전자주식회사 | 비디오 데이터 디스플레이 방법 및 장치 |
US8737469B1 (en) * | 2007-04-03 | 2014-05-27 | Mediatek Inc. | Video encoding system and method |
KR101664112B1 (ko) | 2010-11-16 | 2016-10-14 | 삼성전자주식회사 | 메모리 접근 주소 변환 장치 및 방법 |
CN101996142B (zh) * | 2010-11-17 | 2013-01-02 | 北京炬力北方微电子有限公司 | 一种访问存储器的方法及装置 |
US9231993B2 (en) * | 2013-09-06 | 2016-01-05 | Lg Display Co., Ltd. | Apparatus for transmitting encoded video stream and method for transmitting the same |
Citations (2)
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JPH08163558A (ja) * | 1994-12-07 | 1996-06-21 | Graphics Commun Lab:Kk | 画像復号装置 |
JPH10191236A (ja) * | 1996-12-25 | 1998-07-21 | Nec Corp | 画像処理装置及び画像データメモリ配置方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2907630B2 (ja) * | 1992-04-23 | 1999-06-21 | 松下電送システム株式会社 | フレームメモリ制御装置 |
JP3097437B2 (ja) | 1994-03-14 | 2000-10-10 | 松下電器産業株式会社 | 圧縮動画像の記録方法と再生装置 |
JPH07319436A (ja) * | 1994-03-31 | 1995-12-08 | Mitsubishi Electric Corp | 半導体集積回路装置およびそれを用いた画像データ処理システム |
JPH11339493A (ja) * | 1998-05-27 | 1999-12-10 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2000113670A (ja) * | 1998-10-05 | 2000-04-21 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2003045182A (ja) * | 2001-08-01 | 2003-02-14 | Mitsubishi Electric Corp | 半導体記憶装置 |
-
2000
- 2000-04-13 WO PCT/JP2000/002406 patent/WO2000062550A1/ja not_active Application Discontinuation
- 2000-04-13 KR KR1020007014148A patent/KR100767611B1/ko not_active IP Right Cessation
- 2000-04-13 US US09/719,452 patent/US7110663B1/en not_active Expired - Fee Related
- 2000-04-13 EP EP00915506A patent/EP1089567A4/en not_active Withdrawn
- 2000-04-13 CN CNB008010749A patent/CN1140125C/zh not_active Expired - Fee Related
-
2006
- 2006-07-27 US US11/494,723 patent/US20060263069A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08163558A (ja) * | 1994-12-07 | 1996-06-21 | Graphics Commun Lab:Kk | 画像復号装置 |
JPH10191236A (ja) * | 1996-12-25 | 1998-07-21 | Nec Corp | 画像処理装置及び画像データメモリ配置方法 |
Non-Patent Citations (2)
Title |
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See also references of EP1089567A4 * |
TAN, CHEE HENG, LIREN ZHANG: "effects of cell loss on the quality of service for MPEG video in ATM environment", PROCEEDINGS OF IEEE SINGAPORE INTERNATIONAL CONFERENCE ON NETWORK, 1995, THEME:ELECTROTECHNOLOGY 2000: COMMUNICATIONS AND NETWORKS (IN CONJUNCTION WITH THE) INTERNATIONAL CONFERENCE ON INFORMATION ENGINEERING, July 1995 (1995-07-01), pages 11 - 15, XP002929629 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7852343B2 (en) | 2004-04-15 | 2010-12-14 | Panasonic Corporation | Burst memory access method to rectangular area |
Also Published As
Publication number | Publication date |
---|---|
EP1089567A1 (en) | 2001-04-04 |
CN1314050A (zh) | 2001-09-19 |
US7110663B1 (en) | 2006-09-19 |
EP1089567A4 (en) | 2001-11-07 |
US20060263069A1 (en) | 2006-11-23 |
KR100767611B1 (ko) | 2007-10-17 |
CN1140125C (zh) | 2004-02-25 |
KR20010052823A (ko) | 2001-06-25 |
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