WO2000057565A1 - Dispositif de fin de ligne radio mobile et circuit de reception - Google Patents
Dispositif de fin de ligne radio mobile et circuit de reception Download PDFInfo
- Publication number
- WO2000057565A1 WO2000057565A1 PCT/JP2000/001818 JP0001818W WO0057565A1 WO 2000057565 A1 WO2000057565 A1 WO 2000057565A1 JP 0001818 W JP0001818 W JP 0001818W WO 0057565 A1 WO0057565 A1 WO 0057565A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock
- frequency error
- timing
- reception
- circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
Definitions
- the present invention relates to standby control of a digital mobile radio communication system, and in particular, resynchronization of reception timing is strictly required as in a CDMA (Code Division Multiple Access) system.
- the present invention relates to a mobile wireless terminal device of a system.
- mobile wireless terminals such as mobile phones are required to have low power consumption during standby operation in order to extend continuous operation time. For this reason, in the non-receiving section, the internal high-speed system lock is stopped, and instead, a low-speed, low-precision 32 kHz lock used for clocks is used instead. It is supplied to dwell and software to operate.
- this 32 kHz clock does not have a function to correct the frequency fluctuation component due to temperature, this clock is used as a timer to measure the length of the non-receiving section. A timing error occurs between the reception time determined by the timer and the actual reception time.
- the reception timing error is 1.6 ⁇ sec or more depending on the non-reception section. It is estimated as below msec.
- An object of the present invention is to provide a mobile radio communication terminal device and a receiving circuit capable of obtaining the following.
- the present invention relates to a mobile wireless terminal device that performs intermittent reception according to a reception section and a non-reception section that are temporally determined in a mobile radio communication system.
- the reception timing detecting means for detecting the start timing of the reception section, and the first clock are faster and faster.
- Frequency error detecting means for detecting a relative frequency error of the first clock using a high-accuracy second clock; and a frequency error detected by the frequency error detecting means.
- Reception section detected by reception timing detection means based on And a receiving means for receiving at the timing corrected by the timing correction means.
- the first clock is caught in a receiving circuit that performs intermittent reception according to a reception section and a non-reception section that are temporally determined in the mobile radio communication system.
- the reception timing detection means for detecting the start timing of the reception section and the second clock which is faster and more accurate than the first clock are used.
- timing correction means for correcting the start timing of the reception section detected by the above.
- the start timing of the receiving section obtained in the slow first clock which is expected to have an error, is corrected. Then, using a high-speed and high-accuracy second clock, the relative frequency error of the first clock is detected, and based on the detection result, the start timing detected above is detected. To make corrections.
- a desired clock can be obtained even if the first clock with low frequency accuracy is used as a timer in a non-receiving section. You can do it.
- the frequency error detection means uses the second clock to detect the relative first clock in the reception section. It is characterized by detecting frequency errors. According to this feature, it is not necessary to generate a high-speed second clock to detect the frequency error in the non-reception section, so that the first clock can be used without increasing power consumption. The frequency error of the lock can be detected.
- FIG. 1 is a circuit block diagram showing a configuration of an embodiment of a receiving system of a mobile wireless terminal device according to the present invention.
- FIG. 2A to 2H are diagrams for explaining the operation of the frequency deviation estimating circuit of the mobile radio terminal device shown in FIG.
- FIG. 3 is a circuit block diagram showing a configuration of a ⁇ detection circuit of the mobile wireless terminal device shown in FIG.
- FIG. 4 is a circuit block diagram showing a configuration of a ⁇ f sign determination circuit of the ⁇ f detection circuit shown in FIG.
- 5A to 5D are diagrams for explaining an enable signal generation operation of the ⁇ f code determination circuit shown in FIG.
- FIG. 6 is a circuit block diagram showing a configuration of a timer and a timing correction circuit of the mobile wireless terminal device shown in FIG.
- 7A to 7E are diagrams for explaining the operation of the timer 30 and the timing correction circuit 40 when the reception timing is advanced.
- FIGS. 8A to 8E are diagrams for explaining the operation of the timer 30 and the timing correction circuit 40 when the reception timing is delayed.
- FIG. 9 is a diagram for explaining a reception timing correction operation during a reception operation.
- FIG. 1 shows a configuration of a receiving system of a mobile wireless terminal device according to an embodiment of the present invention.
- the frequency deviation estimating circuit 10 calculates the frequency deviation Af between the clock for clock generated by the clock generating circuit 20 described later and the high-speed system clock synchronized with the system. It comprises a power counter 11, a latch circuit 12, and an Af detection circuit 13.
- the clock for clock generated by the clock generation circuit 20 has a relatively low accuracy because the temperature fluctuation of the frequency is not corrected at, for example, 32 kHz.
- the system clock is, for example, 9.803 MHz, which is faster and more accurate than a clock clock.
- the frequency of the clock for clock generated by the clock generation circuit 20 is assumed to be f1
- the ideal period indicating the ideal without error is denoted by TO
- the actual period is indicated by Let T 1 be the real period. Also, let the frequency of the system clock be f2.
- FIG. 2 is a diagram showing input / output signals of each unit in the frequency deviation estimating circuit 10.
- the counter 11 operates the system clock ( Figure 2A).
- the counter value is repeated, and the M value corresponding to the ideal period TO of the watch clock is repeated and counted.
- the count result is shown in Figure 2B.
- the latch circuit 12 holds the output of the counter 11 at the edge of the clock clock (FIG. 2C). This output is shown in Figure 2D and Figure 2E.
- the Af detection circuit 13 obtains a frequency deviation from the held output of the latch circuit 12, and outputs this deviation ⁇ as voltage or amplitude information.
- the frequency deviation is difference information between the ideal period T O and the real period T 1, but since it is usually a very small value of the ppm level, detection requires processing such as averaging over a long period of time.
- FIG. 3 shows a configuration example of the A f detection circuit 13.
- the final frequency deviation m f is obtained by averaging the difference information between the output of the latch circuit 12 and the output one sample before from the output of the latch circuit 12 for a certain period of time.
- the output of the latch circuit 12 is proportional to the frequency deviation of the clock. Will fluctuate. That is, if the frequency deviation is large, the fluctuation within one cycle is large, and if the deviation is small, the fluctuation is small.
- the output of the latch circuit 12 before the sample time and the output of the latch circuit 12 at the current sample time are obtained by the difference circuit 13 1 and the delay circuit 13 2. Find the difference between and (Fig. 2F), and use this as the instantaneous variation.
- the latch output one sample time before is used in the detection of the instantaneous fluctuation, but if the frequency deviation is small, the latch output before a plurality of samples is used to improve the detection accuracy.
- Switch output may be used.
- the average value of the instantaneous fluctuations is obtained by the averaging circuit 133.
- the instantaneous fluctuations have a predetermined period and have a dip portion irrespective of the frequency deviation as shown in Fig. 2F. Since D occurs, do not include it in the averaging process.
- the position of the dip D of the instantaneous variation is obtained by the ⁇ f code determination circuit 134 and is notified to the averaging circuit 133 as an enable signal (FIG. 2G). According to this notification, the averaging circuit 133 does not perform the averaging for the dip portion D.
- the averaging circuit 133 obtains the average value ⁇ f of the instantaneous fluctuation excluding the dip D as shown in FIG. 2H. This ⁇ is notified to CPU 50 described later.
- the ⁇ ⁇ sign determination circuit 13 4 finds the polarity (sign) si of the instantaneous variation in order to find the direction of the frequency deviation. Notify PU 50.
- FIG. 4 shows a configuration example of the Af code determination circuit 134.
- the ⁇ code determination circuit 13 4 includes an MSB detection circuit 13 4 1, an averaging circuit 13 4 2, a comparison circuit 13 4 3, 13 4 4, and a NOR circuit 13 4 5. Power.
- the MSB detection circuit 1341 detects the instantaneous fluctuation MSB output from the difference circuit 1331 and outputs the same to the averaging circuit 1342.
- the averaging circuit 1332 averages the MSB detection value of the MSB detection circuit 1341 for a predetermined time, obtains the code s i of the instantaneous variation, and notifies the CPU 50 of it.
- the sign si indicates that the reception timing is advanced compared to the actual reception time, and if it is determined to be negative, This indicates that the reception timing is delayed compared to the actual case.
- the dip D of the instantaneous fluctuation occurs only when the output of the latch circuit 12 fluctuates from near the maximum level to near the zero level (see Fig. 2F). Can be regarded as abnormal. This negative fluctuation (the dip D) usually becomes larger as compared with the other fluctuations.
- the dip portion D is detected by comparing with instantaneous fluctuations using threshold values t hi and th 2 of codes having appropriate sizes and different codes. This comparison is performed by the comparison circuits 1 3 4 3 and 1 3 4 4.
- the thresholds th 1 and th 2 are set in advance. It is assumed that they are set as shown in Fig. 5A.
- the comparison circuit 1343 compares the positive threshold value th1 with the instantaneous fluctuation, and outputs the comparison result (FIG. 5B) to the first input terminal of the NOR circuit 1345.
- the comparison circuit 1344 compares the negative threshold value th2 with the instantaneous fluctuation, and outputs the comparison result (FIG. 5C) to the second input terminal of the NOR circuit 1345.
- the NOR circuit 1345 performs a NOR logical operation on the input from the first input terminal and the input from the second input terminal. As a result, the NOR circuit 1345 outputs an output as shown in FIG. 5D. This indicates the position of the dip portion D, and is output to the averaging circuit 133 as an enable signal.
- the NOR circuit 1345 shown in the present embodiment is H-active, the request from the polarity of the enable terminal in the averaging circuit 133 and the comparison circuit 1 3 4 3, 1 3 4 depending on the request from the fourth output polarity, it may also be another logical operators les 0
- the clock generation circuit 20 generates the clock for the clock by the crystal oscillation without correcting the temperature fluctuation of the frequency, that is, the clock that may have an error due to the temperature fluctuation.
- a clock is generated, and the generated clock clock is input to the timer 30.
- the timer 30 counts the clock for the above clock, and outputs a signal indicating the reception timing every time the CPU 50 counts the number n specified.
- the timing correction circuit 40 operates using the high-precision system clock of the frequency f 2 synchronized with the system immediately after the setting by the timer 30, and is controlled by the timer 30.
- the specified reception timing is corrected and output by the delay amount ⁇ notified from the CPU 50 described later.
- FIG. 6 shows a configuration example of the timer 30 and the timing correction circuit 40.
- FIGS. 7 and 8 show the input / output signal waveforms of the respective components of the timer 30 and the timing correction circuit 40 when the reception timing is advanced and delayed, respectively.
- the timer 30 is composed of a counter 31 having the clock for the clock as a clock input and a mask circuit 32.
- the counter 31 counts the clock for clock (FIG. 7 7 and FIG. 8 ⁇ ) and the count value (FIG. 7 ⁇ and FIG. 8 ⁇ ) of the mask circuit 3. Output to 2.
- the mask circuit 32 compares the count value of the counter 31 with the set value ⁇ notified from the CPU 50, and if the two are different, the L level Is output, and when they match, ⁇ -level output is started.
- the output of the mask circuit 32 transitions from L logic to ⁇ logic at the time when the counter value of the counter 31 matches the set value ⁇ . At this time, the rising edge of the output of the mask circuit 32 becomes the above-mentioned reception timing, and is output to the timing correction circuit 40.
- the CPU 50 executes the ⁇ f code determination circuit 13 described above. 4 If the sign si of the instantaneous variation notified is positive, that is, if the reception timing is advanced, “N” is set as the above set value n.
- N is the number of pulses when a preset non-receiving section is counted by the clock generation circuit 20 operating in an ideal state (period T0).
- f 1 32 kHz
- the non-receiving section L s 1
- N is 409600. This calculation is performed by CPU.
- the timing correction circuit 40 includes a shift register 41, a selector 42, and a power.
- the output of the mask circuit 32 is supplied to a shift register 41.
- the shift register 41 reads the output of the mask circuit 32 by the system clock. That is, as shown in FIG. 7D and FIG. 8D, the output of the mask circuit 32 is latched by the system clock, and the data stored in each register is latched. Is output to the selector 42.
- the latch output of each register of the shift register 41 is the output of the mask circuit 32 synchronized with the clock for clock. It is a delay of the system clock cycle, instead of the timing of the system clock.
- the clock cycle supplied to the shift register 41 is an important parameter that determines the accuracy of the timing adjustment.
- the system clock is used as the clock input of the shift register, but other high-speed clocks synchronized with the system clock are used. Locks may be used instead.
- the selector 42 is notified of the latch output of each register of the shift register 41 from a CPU 50 described later.
- the one corresponding to the delay amount ⁇ is selectively output to the CPU 50.
- the selector 42 uses the reception timing obtained by the mask circuit 32, Select a latch output delayed by ⁇ .
- the selector 42 will use the reception timing calculated by the mask circuit 32 as shown in Figure 8 ⁇ .
- R TO ideal clock cycle
- the CPU 50 controls and controls each section of the mobile wireless terminal device.
- the CPU 50 includes a CPU, a processor, a processor such as a DSP, and a RAM for storing a control program and various data. Consists of ROM.
- a receiving system (not shown) is operated by the system clock, while at the time of standby operation, the clock clock corrected by the timing correction circuit 40 is operated. Operate with.
- the CPU 50 includes a ⁇ estimating circuit 51 for obtaining a timing correction amount.
- L s is the length of the non-receiving section.
- the CPU 50 In response to the reception section and the non-reception section (during standby) being repeated as shown in FIG. 9A, the CPU 50 has a higher speed than that immediately before the reception section as shown in FIG. 9B. A system clock is used, while a clock clock corrected by the timing correction circuit 40 is used in the remaining non-receiving section.
- the frequency deviation estimating circuit 10 estimates the frequency deviation ⁇ f immediately before and during the receiving section and obtains the sign si as shown in FIG.9C. At the end of such a reception section, and hold it to the CPU 50. Notify and stop the operation in the remaining non-reception section.
- the CPU 50 starts the operation at the reception timing estimated by the timer 30 as shown in FIG. 9E, and estimates the frequency deviation by the timing of FIG. 9D.
- the timing correction amount ⁇ and the set value ⁇ are obtained based on the frequency deviation A f notified from the circuit 10, the code si, and the non-reception section information L s obtained from the base station. Store in own RAM and stop operation.
- the timer 30 operating in the low-speed clock estimates the reception timing.
- the CPU 50 resumes the operation at the reception timing estimated by the timer 30, and gives the set value n stored in the RAM to the timer 30, and the reception timing Is written to shift register 41 in the system clock. Then, by reading the register information corresponding to the timing correction amount ⁇ stored in the RAM, the reception timing is corrected, and the reception is performed at the corrected timing. To start.
- the frequency deviation ⁇ of the clock for the clock is detected using the high-speed and high-precision system clock in the reception interval. From this detection result, the timing correction amount ⁇ is obtained. Then, the reception timing obtained by using the clock for the clock in the non-reception section is corrected by the above-mentioned timing correction amount, and the corrected reception timing is used in the reception section with the corrected reception timing. You are trying to start receiving.
- a clock with low frequency accuracy is used as a timer in a non-receiving section. Even in this case, the desired reception timing can be obtained, and if the system has a function of temperature compensation in generating the system clock, it can follow fluctuations due to ambient temperature, etc. it can.
- the power consumption may be increased due to this detection. There is no.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mobile Radio Communication Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20000911345 EP1089443A1 (en) | 1999-03-24 | 2000-03-24 | Mobile radio terminal device and receiving circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11/79619 | 1999-03-24 | ||
JP7961999A JP2000278752A (ja) | 1999-03-24 | 1999-03-24 | 移動無線端末装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000057565A1 true WO2000057565A1 (fr) | 2000-09-28 |
Family
ID=13695087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/001818 WO2000057565A1 (fr) | 1999-03-24 | 2000-03-24 | Dispositif de fin de ligne radio mobile et circuit de reception |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1089443A1 (ja) |
JP (1) | JP2000278752A (ja) |
WO (1) | WO2000057565A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6735454B1 (en) * | 1999-11-04 | 2004-05-11 | Qualcomm, Incorporated | Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode |
EP1368916A4 (en) * | 2001-03-12 | 2008-05-07 | Skyworks Solutions Inc | METHOD AND DEVICE FOR SPREADING SPECTRUM RADIO SIGNAL RESTORATION IN BROADBAND SPREADING SPECTRUM COMMUNICATION SYSTEMS |
JP3689021B2 (ja) * | 2001-05-25 | 2005-08-31 | 三菱電機株式会社 | タイミング制御装置及びタイミング制御方法 |
JP2008124524A (ja) * | 2005-03-04 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 間欠受信制御装置 |
JP5238144B2 (ja) * | 2006-05-12 | 2013-07-17 | 矢崎総業株式会社 | 時計の誤差補正方法 |
JP2008154185A (ja) * | 2006-12-20 | 2008-07-03 | Matsushita Electric Works Ltd | 無線送信装置 |
JP5088677B2 (ja) * | 2007-08-02 | 2012-12-05 | セイコーエプソン株式会社 | 時刻修正装置、時刻修正装置付き計時装置及び時刻修正方法 |
JP5213512B2 (ja) * | 2008-05-07 | 2013-06-19 | キヤノン株式会社 | 送信装置及び方法 |
CN101604990B (zh) * | 2008-06-13 | 2013-08-07 | 电信科学技术研究院 | 频偏补偿方法和装置 |
TWI502903B (zh) * | 2011-02-22 | 2015-10-01 | Panasonic Corp | 無線通信系統 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274707A (ja) * | 1995-03-31 | 1996-10-18 | Nec Corp | 無線送受信装置 |
JPH08307338A (ja) * | 1995-04-27 | 1996-11-22 | Fujitsu Ltd | 無線装置 |
JPH0918405A (ja) * | 1995-06-30 | 1997-01-17 | Nippondenso Co Ltd | 間欠受信制御装置 |
JPH09153854A (ja) * | 1995-11-28 | 1997-06-10 | Denso Corp | 間欠受信装置 |
-
1999
- 1999-03-24 JP JP7961999A patent/JP2000278752A/ja active Pending
-
2000
- 2000-03-24 WO PCT/JP2000/001818 patent/WO2000057565A1/ja not_active Application Discontinuation
- 2000-03-24 EP EP20000911345 patent/EP1089443A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08274707A (ja) * | 1995-03-31 | 1996-10-18 | Nec Corp | 無線送受信装置 |
JPH08307338A (ja) * | 1995-04-27 | 1996-11-22 | Fujitsu Ltd | 無線装置 |
JPH0918405A (ja) * | 1995-06-30 | 1997-01-17 | Nippondenso Co Ltd | 間欠受信制御装置 |
JPH09153854A (ja) * | 1995-11-28 | 1997-06-10 | Denso Corp | 間欠受信装置 |
Also Published As
Publication number | Publication date |
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JP2000278752A (ja) | 2000-10-06 |
EP1089443A1 (en) | 2001-04-04 |
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