WO2000049653A1 - Support de stockage et procede de fabrication d'un circuit integre a semi-conducteur - Google Patents
Support de stockage et procede de fabrication d'un circuit integre a semi-conducteur Download PDFInfo
- Publication number
- WO2000049653A1 WO2000049653A1 PCT/JP1999/000675 JP9900675W WO0049653A1 WO 2000049653 A1 WO2000049653 A1 WO 2000049653A1 JP 9900675 W JP9900675 W JP 9900675W WO 0049653 A1 WO0049653 A1 WO 0049653A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- data
- storage medium
- module
- integrated circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Definitions
- a hard macro block such as the hard IP module also includes information on a mask pattern for forming a verified late pattern as a data provided to a designer. Therefore, the circuit characteristics of blocks (circuits) provided as hard IP modules are guaranteed. Therefore, when designing microcomputers and system LSIs, the use of hard macro blocks such as hard IP modules, which are past design assets, can greatly reduce the design and verification period. Can be.
- the function description by HDL etc. included in the hard IP module is used to verify the logical operation etc. of the integrated configuration of the hard IP module and the outside when the hard IP module is connected to the outside .
- the present inventor described the above-mentioned hard IP module software in designing a semiconductor integrated circuit.
- G The use of data such as IP modules was examined.
- micro-computers can be deployed as products by adding peripheral functions that meet the specifications required by users to the CPU that is the core of micro-computers.
- the already designed hard IP module is reused as a peripheral circuit module to shorten the design period, the design period up to the layout can be reduced as described above.
- Still another object of the present invention is to provide a storage medium storing design data enabling reduction of power consumption and / or chip occupation area of a reusable module in a semiconductor integrated circuit. .
- FIG. 12 is an explanatory diagram showing an example in which the first circuit in FIG. 10 is a hard module, the second circuit is a soft module, and each is composed of separate IP modules.
- the second circuit 3 is an interface circuit or buffer circuit such as an address output register, a data input / output register, a control signal flip-flop, and a logic gate.
- the second circuit 3 includes a two-input OR gate 30, a two-input AND gate 31, an invar 32, and a buffer 33.
- PS 1 N and PS 3 N are representative input signals external to the module
- RXIN and ERIN are representative output signals external to the module.
- nl to n6 exemplify net names in the second circuit 3
- N1 to N6 exemplify terminal names in the first circuit 2.
- FIG. 2 shows data (hereinafter referred to as I
- the computer decodes the data and performs processing.
- the computer executes a specific program in order to decode and perform the processing.
- the computer may be a distributed processing system. For example, each of the disk access, the layout calculation, and the man-machine interface may be processed using a separate computer, and the processing results may be used in cooperation. If the capacity of the IP module data including the first to third data DTIDT 1 to DT 3 becomes large and cannot be stored in one storage medium 44, a plurality of The IP module may be stored over a storage medium. Of course, the IP module data may be divided in advance so as to be stored in a plurality of storage media, and may be stored in a plurality of storage media.
- Step S1B when designing the semiconductor integrated circuit, even when the external load of the above-mentioned inverter 32 is small, the second data DT 2 loaded on the computer as shown by 51 and the second data DT 2 shown by 50B Then, the result is logically synthesized (Step S1B). However, in this case, since the external load of the above-mentioned room 32 is determined to be relatively small from 50 B on the day, the second data that is loaded on the display is 52 B The description is modified so that the inverter 32 of the second circuit 3 employs the inverter INV-S having a small driving capability, as shown in FIG.
- DT4 which is the fourth day for Noh. Since the terminal of the first circuit 2 serves as a connection terminal with the second circuit 3, the fourth data DT 4 From the second circuit 3, the characteristic or / and the logic function at the terminal of the first circuit 2 can be grasped as data for making it visible.
- only the third information may be stored in a storage medium and provided.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99905204A EP1156523A4 (en) | 1999-02-17 | 1999-02-17 | STORAGE MEDIUM AND METHOD FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR CIRCUIT |
PCT/JP1999/000675 WO2000049653A1 (fr) | 1999-02-17 | 1999-02-17 | Support de stockage et procede de fabrication d'un circuit integre a semi-conducteur |
US09/913,021 US6654945B1 (en) | 1999-02-17 | 1999-02-17 | Storage medium in which data for designing an integrated circuit is stored and method of fabricating an integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1999/000675 WO2000049653A1 (fr) | 1999-02-17 | 1999-02-17 | Support de stockage et procede de fabrication d'un circuit integre a semi-conducteur |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000049653A1 true WO2000049653A1 (fr) | 2000-08-24 |
Family
ID=14234938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/000675 WO2000049653A1 (fr) | 1999-02-17 | 1999-02-17 | Support de stockage et procede de fabrication d'un circuit integre a semi-conducteur |
Country Status (3)
Country | Link |
---|---|
US (1) | US6654945B1 (ja) |
EP (1) | EP1156523A4 (ja) |
WO (1) | WO2000049653A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003036175A (ja) * | 2001-07-24 | 2003-02-07 | Pacific Design Kk | データ処理装置の設計方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5274033A (en) * | 1986-12-23 | 1993-12-28 | E. I. Du Pont De Nemours And Company | Tough high melt flow polyamides |
US20030120475A1 (en) * | 2001-12-26 | 2003-06-26 | Toshiba Tec Kabushiki Kaisha | Method of generating asic design database |
JP2003216670A (ja) * | 2002-01-25 | 2003-07-31 | Hitachi Ltd | コンピュータ読み取り可能な記録媒体および半導体集積回路装置 |
US6961919B1 (en) * | 2002-03-04 | 2005-11-01 | Xilinx, Inc. | Method of designing integrated circuit having both configurable and fixed logic circuitry |
US7243311B2 (en) * | 2004-05-28 | 2007-07-10 | Rohm Co., Ltd. | Method and apparatus for supporting development of integrated circuit and a transactional business method involving contracting and licensing |
US7519941B2 (en) * | 2006-04-13 | 2009-04-14 | International Business Machines Corporation | Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry |
JP2009134439A (ja) * | 2007-11-29 | 2009-06-18 | Nec Electronics Corp | ソフトマクロを用いたレイアウト設計方法、ソフトマクロのデータ構造及びソフトマクロライブラリの作成方法 |
US10261760B1 (en) | 2013-12-05 | 2019-04-16 | The Mathworks, Inc. | Systems and methods for tracing performance information from hardware realizations to models |
US10078717B1 (en) * | 2013-12-05 | 2018-09-18 | The Mathworks, Inc. | Systems and methods for estimating performance characteristics of hardware implementations of executable models |
US11545495B2 (en) * | 2017-06-29 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM |
Citations (6)
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JPH02249254A (ja) * | 1989-03-22 | 1990-10-05 | Kawasaki Steel Corp | 大規模集積回路のレイアウト設計支援方法 |
JPH05198672A (ja) * | 1992-01-21 | 1993-08-06 | Hitachi Ltd | セル設計方法、及びそれを用いた半導体集積回路の製造方法 |
JPH0877235A (ja) * | 1994-09-07 | 1996-03-22 | Oki Electric Ind Co Ltd | 集積回路設計支援装置 |
JPH09199598A (ja) * | 1996-01-16 | 1997-07-31 | Matsushita Electric Ind Co Ltd | レイアウト設計の自動配置配線方法 |
JPH10107614A (ja) * | 1996-09-30 | 1998-04-24 | Toshiba Corp | 半導体集積回路及びその設計方法 |
JPH10198726A (ja) * | 1996-09-25 | 1998-07-31 | Vlsi Technol Inc | 集積回路の設計において複合機能ブロックを効率的に実装する方法及び装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922432A (en) * | 1988-01-13 | 1990-05-01 | International Chip Corporation | Knowledge based method and apparatus for designing integrated circuits using functional specifications |
US5302864A (en) | 1990-04-05 | 1994-04-12 | Kabushiki Kaisha Toshiba | Analog standard cell |
FR2681748B1 (fr) | 1991-09-20 | 1994-10-14 | Sgs Thomson Microelectronics Sa | Procede pour concevoir des circuits integres controleurs de protocole et systeme pour sa mise en óoeuvre. |
US5499192A (en) * | 1991-10-30 | 1996-03-12 | Xilinx, Inc. | Method for generating logic modules from a high level block diagram |
JP3144967B2 (ja) * | 1993-11-08 | 2001-03-12 | 株式会社日立製作所 | 半導体集積回路およびその製造方法 |
US5960191A (en) | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
US6292931B1 (en) * | 1998-02-20 | 2001-09-18 | Lsi Logic Corporation | RTL analysis tool |
-
1999
- 1999-02-17 EP EP99905204A patent/EP1156523A4/en not_active Withdrawn
- 1999-02-17 WO PCT/JP1999/000675 patent/WO2000049653A1/ja not_active Application Discontinuation
- 1999-02-17 US US09/913,021 patent/US6654945B1/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH02249254A (ja) * | 1989-03-22 | 1990-10-05 | Kawasaki Steel Corp | 大規模集積回路のレイアウト設計支援方法 |
JPH05198672A (ja) * | 1992-01-21 | 1993-08-06 | Hitachi Ltd | セル設計方法、及びそれを用いた半導体集積回路の製造方法 |
JPH0877235A (ja) * | 1994-09-07 | 1996-03-22 | Oki Electric Ind Co Ltd | 集積回路設計支援装置 |
JPH09199598A (ja) * | 1996-01-16 | 1997-07-31 | Matsushita Electric Ind Co Ltd | レイアウト設計の自動配置配線方法 |
JPH10198726A (ja) * | 1996-09-25 | 1998-07-31 | Vlsi Technol Inc | 集積回路の設計において複合機能ブロックを効率的に実装する方法及び装置 |
JPH10107614A (ja) * | 1996-09-30 | 1998-04-24 | Toshiba Corp | 半導体集積回路及びその設計方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003036175A (ja) * | 2001-07-24 | 2003-02-07 | Pacific Design Kk | データ処理装置の設計方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1156523A4 (en) | 2003-08-06 |
EP1156523A1 (en) | 2001-11-21 |
US6654945B1 (en) | 2003-11-25 |
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