WO2000048243A1 - Substrat de circuit imprime flexible, bande porte-puces, dispositif a semiconducteur sur bande, dispositif a semiconducteur, procede de fabrication de semiconducteur, substrat de circuit, et dispositif electronique - Google Patents

Substrat de circuit imprime flexible, bande porte-puces, dispositif a semiconducteur sur bande, dispositif a semiconducteur, procede de fabrication de semiconducteur, substrat de circuit, et dispositif electronique Download PDF

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Publication number
WO2000048243A1
WO2000048243A1 PCT/JP2000/000552 JP0000552W WO0048243A1 WO 2000048243 A1 WO2000048243 A1 WO 2000048243A1 JP 0000552 W JP0000552 W JP 0000552W WO 0048243 A1 WO0048243 A1 WO 0048243A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
slit
wiring pattern
semiconductor device
wiring
Prior art date
Application number
PCT/JP2000/000552
Other languages
English (en)
Japanese (ja)
Inventor
Masahiko Yanagisawa
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to KR1020007011228A priority Critical patent/KR100354203B1/ko
Publication of WO2000048243A1 publication Critical patent/WO2000048243A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/0909—Preformed cutting or breaking line

Definitions

  • the present invention relates to a flexible wiring board, a film carrier, a tape-shaped semiconductor device, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.
  • TAB Tepe Automated Bonding
  • the semiconductor chip is punched from the flexible wiring board to obtain a TCP (Tape Carrier Package), but errors may occur in the TCP punching position.
  • TCP Transmission Carrier Package
  • the wiring pattern had to be formed considerably inside the flexible wiring board from the punching position. In other words, it was necessary to secure a relatively large area including errors as the punched area, which had an effect on miniaturization and securing a wiring routing area.
  • the present invention has been made to solve this problem, and an object thereof is to provide a flexible wiring board, a film carrier, and a tape-shape capable of obtaining an accurate external shape and securing a maximum wiring area.
  • An object of the present invention is to provide a semiconductor device, a semiconductor device and a manufacturing method thereof, a circuit board, and an electronic device.
  • a flexible wiring substrate according to the present invention includes: a long base substrate; and a plurality of wiring patterns formed on the base substrate.
  • a slit is formed on a punched imaginary line including each wiring pattern inside,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape of punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed into a shape J5 by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • the slit may be formed only at a position forming an outer shape outside the wide portion.
  • a protective film may be provided on the wiring pattern and on the base substrate on a region avoiding the peripheral portion of the slit.
  • the protective film is provided so as to avoid the peripheral portion of the slit, the material for forming the protective film on the back surface of the base substrate via the slit is prevented.
  • a film carrier according to the present invention comprises: a base substrate; And a formed wiring pattern,
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • a slit is formed on an imaginary punched line including the wiring pattern inside,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern is the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • a tape-shaped semiconductor device includes a long base substrate, a plurality of wiring patterns formed on the base substrate, and a plurality of wiring patterns mounted on the base substrate.
  • a semiconductor chip electrically connected to a wiring pattern, wherein the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction.
  • the base substrate has a slit formed on a punched imaginary line including a wiring pattern inside thereof,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. That is, a part of the outer shape of the member to be punched is previously formed by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error had to be secured as a punched area, but in the present invention, a large punched area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern can be increased. Then, the size of the semiconductor device can be reduced.
  • the semiconductor device according to the present invention is obtained by punching the base substrate of the tape-shaped semiconductor device by the punching virtual line.
  • the semiconductor device since the portion formed by the cut edge of the slit obtained by punching out the base substrate is located at an accurate position with respect to the wiring pattern, the semiconductor device is referred to based on the portion. Can handle.
  • the semiconductor device includes: a base substrate; a wiring pattern formed on the base substrate; and a semiconductor chip mounted on the base substrate and electrically connected to the wiring pattern.
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • a slit is formed on a punched imaginary line including a wiring pattern inside thereof,
  • the slit is formed at least at a position where the outer shape of the wide portion is formed in the shape for punching the base substrate.
  • the slit is formed on the imaginary punching line, when the base substrate is punched, a part of the outer shape of the punched member is formed by the end of the slit. It is formed. That is, a part of the outer shape of the stamped member is formed in advance by the slit. Therefore, a part of the outer shape can be formed at an accurate position with respect to the wiring pattern, and handling based on the part can be performed.
  • the slit is formed at the position where the interval between the punching position and the wiring pattern becomes the narrowest, and the punching may be performed in the slit, so that the wiring pattern can be formed close to the slit. That is, in the related art, a relatively large area including an error has to be secured as a punching area, but in the present invention, a wide punching area is not required. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is expanded. Then, the size of the semiconductor device can be reduced.
  • the semiconductor device is electrically connected to the circuit board according to the present invention.
  • An electronic apparatus includes the above-described semiconductor device.
  • a method of manufacturing a semiconductor device comprising the steps of: mounting a semiconductor chip on a flexible base substrate on which a wiring pattern is formed and having a slit; Including the step of punching with a virtual line passing above,
  • the wiring pattern has a wide portion formed in a wide region in the width direction of the base substrate, and a narrow portion formed in a narrow region in the width direction,
  • the outer shape of the wide part is formed by the end of the slit left after punching.
  • an accurate outer shape can be obtained at the position where the most accurate punching is desired. That is, in the past, an accurate outer shape can be formed by a slit in a region where a relatively large region including an error had to be secured. Therefore, it is not necessary to form a wiring pattern considerably inside from the punching position, and the degree of freedom in designing the wiring pattern is increased. Then, the size of the semiconductor device can be reduced.
  • the method may include a step of providing a protective film on the wiring pattern and on the base substrate on a region avoiding a peripheral portion of the slit.
  • the protective film is provided so as to avoid the peripheral portion of the slit, the protective film is provided through the slit. As a result, the material forming the protective film on the back surface of the base substrate can be prevented from flowing around. (12) In this method of manufacturing a semiconductor device,
  • a plurality of the wiring patterns are formed on the base substrate;
  • the slit is formed corresponding to each wiring pattern
  • the base line may be punched by setting the virtual line in a region including each wiring pattern and passing through the corresponding slit.
  • a plurality of semiconductor devices can be simultaneously or continuously manufactured by electrically connecting the semiconductor chip to each of the plurality of wiring patterns.
  • FIG. 1 is a diagram showing a flexible wiring board according to an embodiment to which the present invention is applied.
  • FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
  • 3A and 3B are views showing a semiconductor device according to an embodiment to which the present invention is applied.
  • FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied.
  • FIG. 5 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment.
  • FIG. 6 is a diagram showing an electronic apparatus having the semiconductor device according to the present embodiment.
  • 7A to 7C are diagrams showing a method for manufacturing a flexible wiring board according to the present embodiment.
  • FIG. 8A to 8C are diagrams illustrating the method for manufacturing the semiconductor device according to the present embodiment.
  • FIG. 9 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
  • FIG. 10 is a view showing a modification of the flexible wiring board according to the embodiment to which the present invention is applied.
  • FIG. 1 is a diagram showing a flexible wiring board according to the present embodiment.
  • the flexible wiring substrate 1 includes a base substrate 10 and a plurality of wiring patterns 20 (only one is shown in FIG. 1).
  • the flexible wiring board 1 can be wound on a reel (not shown) and handled.
  • the flexible wiring substrate 1 is a TAB substrate (film carrier tape), but is not limited to this, and a COF (Chip On Film) substrate, It may be a substrate for COB (Chip On Board).
  • the base substrate 10 is a long (tape-shaped) base material, and is a support member for the wiring pattern 20.
  • the base substrate 10 has flexibility.
  • the base substrate 10 is often formed of polyimide resin, but other well-known materials can be used. If a plurality of sprocket holes 12 arranged in the length direction are formed at both ends in the width direction of the base substrate 10, the flexible wiring substrate 1 can be sent out by engaging a hook (not shown) with the sprocket holes 12. Can be.
  • one (a plurality of device holes) 14 are formed in the base substrate 10 for each wiring pattern 20.
  • the semiconductor chip can be bonded to an electrical connection (for example, an inner lead) with the semiconductor chip.
  • the shape of the device hole 14 is not particularly limited, and may be a size that can completely accommodate the semiconductor chip or a size that can partially accommodate the semiconductor chip.
  • a plurality of wiring patterns 20 are formed on the base substrate 10.
  • the wiring pattern 20 is bonded to the base board 10 via an adhesive (not shown).
  • the wiring pattern 20 is formed directly on the base board 10 without any adhesive.
  • the wiring patterns 20 may be formed side by side in the longitudinal direction of the long-sized pace substrate 10, may be formed side by side in the width direction, or may be formed in a matrix (in the longitudinal direction and in the longitudinal direction). (Arranged in the width direction). Each of the wiring patterns 20 often has the same shape, but may have different shapes. For example, a wiring pattern group formed by arranging n wiring patterns 20 having n kinds of shapes may be repeatedly formed. The plurality of wiring patterns 20 may be electrically connected by a plating lead (not shown) in order to perform electrical plating.
  • Each wiring pattern 20 has a plurality of wirings 22 and 24. Specifically, a plurality of wirings 22 are formed on one side (the upper side in FIG. 1) of the device hole 14 along the longitudinal direction of the base substrate 10, and on the other side (the lower side in FIG. 1). A plurality of wirings 24 are formed. Each of the wirings 22 and 24 includes an inner lead 26 and 28 formed at one end, and other ends 34 and 36.
  • the leads 26 and 28 project into the device hole 14.
  • the inner leads 26 and the inner leads 28 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10.
  • the inner leads 26 and 28 are electrical connections with the semiconductor chip 60 (see FIG. 2).
  • the ends 34, 36 extend on the opposite side to the inner leads 26, 28.
  • the ends 34 and the ends 36 are formed in parallel, and may be formed to extend in the longitudinal direction of the base substrate 10.
  • the ends 34 and 36 may be formed so that at least one of the width and the pitch is wider than the inner leads 26 and 28.
  • the ends 34, 36 are electrically connected to other electrical components.
  • the end portion 36 of the wiring 24 is formed across the outer lead hole 38, and the portion inside the outer lead hole 38 of the end portion 36 is the outer lead. .
  • the connecting portion 30 between the inner lead 26 and the end portion 34 of the wiring 22 is formed to be inclined in a direction to increase the interval between the adjacent lead 26.
  • the wiring pattern 20 includes the wide portion 16 including the plurality of connection portions 30.
  • the wiring pattern 20 includes a narrow portion 18 that is narrower than the wide portion 16.
  • the narrow portion 18 shown in FIG. 1 is, for example, a portion extending linearly from the inner lead 26 to the connection portion 30.
  • the entire wiring 24 may also be referred to as a narrow portion.
  • the connection part 30 may be formed by drawing a straight line or may be formed by drawing a curve.
  • the connection part 32 between the inner lead 28 and the end part 36 of the wiring 24 shown in FIG. 1 may be formed in the same manner as the connection part 30.
  • a slit 40 is formed in the base substrate 10.
  • the slit 40 may be a cut or an elongated hole.
  • the slit 40 extends in the length direction of the base substrate 10, but may extend in the width direction, or may be formed obliquely with respect to the axis of the base substrate 10. You may. Further, the slit 40 may be formed in a straight line, may be bent, or may form a corner.
  • the slit 40 is formed on a virtual line 42 for punching.
  • the virtual line 42 includes at least a part of each wiring pattern 20 inside. At least one hole, for example, a device hole 14 or an outer lead hole 38 is formed inside the virtual line 42.
  • the imaginary line 42 is the contour of the outer shape of the final product except for the portion formed by the slit 40.
  • the end part becomes a part of the outer shape of the final product.
  • a part of the final product outer shape can be formed in advance.
  • the slit 40 can be formed at an accurate position with respect to the wiring pattern 20. Even if the position of the virtual 42 and the wiring pattern 20 is slightly shifted, the outer shape formed at the end of the slit 40 is formed at an accurate position with respect to the wiring pattern 20.
  • the virtual line 42 may be set at a position where at least one of the ends 34, 36 of the wirings 22, 24 is cut.
  • the inspection of the electrical characteristics may be performed using a portion outside the virtual line 42. Even if the end portions 34 and 36 are damaged as a result of the inspection of the electrical characteristics, this portion may be cut off and removed, so that there is no problem.
  • the slit 40 is formed in that portion, an accurate outer shape is secured. For example, the position of the outer shape outside the wide portion 16 of the wiring pattern 20 is often close to the wiring pattern 20. In this case, if the slit 40 is formed, The cutting of the wiring pattern 20 can be avoided.
  • the slit 40 may be formed only at a position outside the wide portion 16 and outside the wide portion 16, and may not be formed in other regions.
  • the slit 40 may not be formed at a position where there is room in the region, such as the outer shape of the narrow portion 18. By doing so, it is possible to minimize the formation of the slits 40 and prevent the strength of the base substrate 10 from decreasing.
  • the slit 40 is formed in the region where the slit 40 is formed.
  • the outer shape can be formed by the end of the slit 40.
  • the slit 240 shown in FIG. 9 is formed over the entire length of the wide portion 16. By doing so, the entire outer shape of the wide portion 16 can be formed by the end of the slit 240.
  • a plurality of slits 340 shorter than the length of the wide portion 16 may be formed in a row along the outer shape of the wide portion 16.
  • the width of the slit 40 may be equal to or greater than the sum of the thickness of the blade of the die for punching and the error during punching. In this case, even if an error is considered, the blade of the mold is located inside the slit 40, so that punching can always be performed in the slit 40.
  • a protective film 44 (see FIG. 2) may be provided on the wiring pattern 20.
  • the protective film 44 protects the wiring pattern 20 from oxidation and the like.
  • the protective film 44 may be formed of a resin such as a solder resist.
  • the protective film 44 is a part of the wiring pattern 20 excluding portions (inner leads, external terminals, outer leads, etc.) that are electrically connected to other components such as the semiconductor chip 60 (see FIG. 2).
  • the protective film 44 is provided not only on the wiring pattern 20 but also on the base substrate 10.
  • the peripheral portion of the slit 40 (specifically, the portion near the side where the opening of the slit 40 is formed) is formed on the base substrate 10.
  • a liquid material is provided. By doing so, it is possible to prevent the liquid material from going around the back surface of the base substrate 10 through the slit 40.
  • the formed protective film 44 is located at the periphery of the slit 40 (specifically, the opening of the slit 40). In the vicinity of the side forming the edge).
  • a positioning mark 50 is formed on the base substrate 10.
  • the positioning mark 50 can be formed of the same material as the wiring pattern 20 and may be formed simultaneously with the wiring pattern 20.
  • a positioning mark 50 is provided in a region offset from the wiring 22 in the width direction of the base substrate 10. By detecting the position of the positioning mark 5 °, the wiring pattern 20 may be positioned with respect to the terminal provided on another component connected thereto.
  • Holes 52, 54 for positioning are formed.
  • the holes 52 and 54 may be round holes or elongated holes extending in the width direction of the base substrate 10.
  • the film carrier according to the embodiment to which the present invention is applied has a shape obtained by cutting the flexible wiring board shown in FIG. 1 along a straight line (two-dot chain line indicated by reference numeral 56 in FIG. 1) in the width direction.
  • the film carrier is a piece of film cut from the above-described flexible wiring board.
  • the position where the flexible wiring substrate is cut is not particularly limited. In the example shown in FIG. 1, both sides of one wiring pattern 20 are set as the cutting positions, but both sides of a plurality of wiring patterns 20 may be set as the cutting positions.
  • FIG. 2 is a diagram illustrating a method of manufacturing a tape-shaped semiconductor device according to an embodiment to which the present invention is applied.
  • the tape-shaped semiconductor device has the above-described flexible wiring board 1 and a plurality of semiconductor chips 60 electrically connected to each wiring pattern 20.
  • the planar shape of the semiconductor chip 60 is generally rectangular, and may be rectangular or square.
  • a plurality of electrodes are formed on one surface of the semiconductor chip 60.
  • the electrodes are arranged along at least one side (often two or four) of the surface of the semiconductor chip. If the outer shape of the semiconductor chip 60 is rectangular, for example, The electrodes may be arranged in the longitudinal direction like a liquid crystal driving IC, or the electrodes may be arranged in the short direction.
  • the electrodes may be arranged at the end of the surface of the semiconductor chip 60 or may be arranged at the center.
  • Each electrode often includes a thin and flat pad made of aluminum or the like, and a bump formed thereon. If no bump is formed, only the pad will be the electrode.
  • a passivation film (not shown) is formed on the semiconductor chip avoiding at least a part of the electrode. Passhibeshiyon film, for example, S i 0 2, S i N, can be formed such as by Boriimi de resin.
  • the electrodes of the semiconductor chip 60 may be bonded to the inner leads 26 and 28 of the wiring pattern 20 via the device holes 14 by applying the TAB technology.
  • the semiconductor chip 60 may be face-down bonded.
  • the flexible wiring substrate is a substrate mounted with the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 and the base substrate facing each other, that is, a COF (Chip On Film). Good. .
  • the semiconductor chip 60 may be face-up bonded by applying wire bonding or the like.
  • the flexible wiring board is configured such that the active surface (the surface on which the electrodes are formed) of the semiconductor chip 60 faces the same direction as the mounting surface of the base substrate, and the semiconductor chip 60 is connected to the semiconductor chip 60 with a wire ( «) such as a gold wire. It may be a face-up type mounting substrate in which the electrodes of the chip 60 and the wiring patterns 20 are connected.
  • the tape-shaped semiconductor device may have a sealing portion 62.
  • the seal portion 62 seals at least an electrical connection portion (for example, the inner leads 26 and 28) between the electrode of the semiconductor chip 60 and the wiring pattern 20.
  • the seal portion 62 is often formed of resin.
  • the seal portion 62 preferably overlaps with the end of the protective film 44 (see FIG. 5). By doing so, it is possible to prevent the wiring pattern 20 from being exposed.
  • the sealing portion 62 may be provided by potting, It may be provided by one field.
  • the semiconductor device according to the present embodiment has a shape obtained by cutting the tape-shaped semiconductor device shown in FIG. 2 by a straight line extending in the width direction.
  • the tape-shaped semiconductor device may be cut on both sides of one wiring pattern 20 with a cutting jig 64 (such as a cutting tool or a punch).
  • the cutting position may be a position indicated by a two-dot chain line '56 in FIG.
  • 3A and 3B are views showing a semiconductor device having a shape obtained by punching out a base substrate of the tape-shaped semiconductor device shown in FIG.
  • the position where the base substrate 10 is punched is a virtual line 42 shown in FIG.
  • the punching of the base substrate 10 may be performed after the positioning bin is passed through the holes 52 and 54 and the base substrate 10 is positioned.
  • the distance (A dimension in the figure) between the end 66 formed by cutting the opening end of the slit 40 and the wiring pattern 20 is the same as that for forming the wiring pattern 20.
  • the range of error between the exposure and etching steps can be reduced. For this reason, the range of the wiring pattern 20 can be enlarged.
  • FIG. 4 is a diagram showing a circuit board according to an embodiment to which the present invention is applied.
  • a semiconductor device 72 to which the present invention is applied is electrically connected to a circuit board 70.
  • the circuit board 70 may be, for example, a liquid crystal panel.
  • the semiconductor device 72 is formed by punching a base substrate 10 of a tape-shaped semiconductor device with a contour surrounding the semiconductor chip 60.
  • the positioning between the circuit board 70 and the semiconductor device 72 may be performed by detecting the positioning mark 50 with a CCD camera or the like, calculating the coordinate position thereof, and transmitting this to the XY table.
  • the positional accuracy between the slit 40 and the wiring pattern 20 is high. For this reason, as shown in FIG. 3A, if the formed end portion 66 from which the slit 40 is cut is pressed against the positioning block 68 (the pressing force is F1, F2 in the figure). 2) Simple and highly accurate positioning is possible. Therefore, the connection between the semiconductor device 72 and the circuit board 70 can be achieved with high positioning accuracy and simplified equipment.
  • the base substrate 10 of the semiconductor device 72 may be provided to be bent.
  • the base substrate 10 may be bent around the end of the circuit substrate 70.
  • FIG. 8 shows a mobile phone 80 as an electronic apparatus having a semiconductor device to which the present invention is applied.
  • This mobile phone 80 also has a circuit board 70 (liquid crystal panel) to which the present invention is applied.
  • FIG. 6 shows a notebook personal computer 90 having a semiconductor device (not shown) to which the present invention is applied.
  • the electronic element (whether active element or passive element) is mounted on the flexible wiring board in the same manner as the semiconductor element, replacing the “semiconductor chip” with the “electronic element” of the present invention.
  • Electronic components manufactured using such electronic devices include, for example, optical devices, resistors, capacitors, coils, oscillators, filters, temperature sensors, summits, nos, squirrels, and volumes. Or a fuse.
  • FIGS. 7A to 8C are process explanatory diagrams showing a manufacturing process of a tab tape (an example of a flexible wiring board).
  • a film-like substrate (an example of a base substrate) 122 constituting the tab tape 120 is a polyimide having sprocket holes 122 formed at both ends in the width direction at equal intervals. Made of wood. By engaging with the sprocket, the tab table 120 can be transported in the longitudinal direction. Note that an adhesive is applied to one surface of the base material 122 in advance so that a copper foil described later can be attached to the base material 122.
  • a die for punching the base material 122 is provided in the middle of the transport path of the tab tape 120.
  • the mold has a device hole 1 2 4 inside the substrate 1 2 2 and a slit 1 26 and an outer lead hole 128.
  • FIG. 7B shows a form after forming these holes and slits 126 in the base material 122. Note that, as shown in FIG. 7B, the slit 126 has a form in which the longitudinal direction matches the longitudinal direction of the base material 122.
  • the slits 126 are arranged near the region where the sprocket holes 121 are formed in the substrate 122, that is, on both ends of the substrate 122.
  • a copper foil as a base of the wiring pattern is attached to the surface of the base material 122 (lamination step). After laminating the copper foil on the surface of the base material 122, exposure and etching are performed to form a wiring pattern, and wiring is performed in the wiring pattern area set on the surface of the base material 122. A pattern 130 is formed.
  • the position of the device hole 124 and the position of the slit 126 fluctuate in the subsequent process because the depth hole 124 and the slit 126 are formed at the same time as shown in FIG. never do. Therefore, the wiring pattern 130 can be brought close to the slit 126 up to an error range of the exposure and etching steps for forming the wiring pattern. Therefore, the wiring pattern 130 drawn out from the device hole 124 and set between the slits 126 can be set along the maximum outer shape between the slits 126.
  • FIG. 7C shows the positional relationship between the holes and the pattern region 130.
  • the semiconductor chip 13 2 is attached to the inner lead projecting from the device hole 124 as an extension of the wiring pattern 130. Align the terminals and join them.
  • FIG. 8A shows a state in which the semiconductor chip 132 is accommodated in the device hole 124. After the semiconductor chip 132 is placed in the device hole 124, a resin is applied to the inside of the edge of the device hole 124 (then, the resin is put into a drying step), and the semiconductor chip 132 is made of resin. By sealing, the inside of the device hole 124 is protected.
  • the base material 122 includes a depth hole 124, a slit 126, an outer lead hole 128, and a wiring pattern 130, and the punching which becomes the outer shape of the semiconductor device 134.
  • a virtual line 1 3 6 is set.
  • FIG. 8B shows a setting area of the imaginary punched line 1 36. As shown in FIG. 8B, the imaginary punched line 1 36 overlaps with the slit 1 26, and the slit 1 2 6 is cut by punching the substrate 1 2 2 along the imaginary punched line 1 36.
  • the shape of the slit 126 is partially present in a part of the outer shape of the semiconductor device 134.
  • FIG. 8C shows a semiconductor device 1336 punched from the base material 122.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un substrat de circuit imprimé flexible (1) qui comprend une bande de base (10) et plusieurs réseaux d'interconnexion (20) formés sur la bande de base (10). Des fentes (40) sont formées le long de lignes de perforation fantômes (42) en dehors des réseaux d'interconnexion (20) sur la bande de base (10). Les fentes (40) définissent la limite d'une large bande (16) sur laquelle sont formés les réseaux d'interconnexion (20).
PCT/JP2000/000552 1999-02-09 2000-02-02 Substrat de circuit imprime flexible, bande porte-puces, dispositif a semiconducteur sur bande, dispositif a semiconducteur, procede de fabrication de semiconducteur, substrat de circuit, et dispositif electronique WO2000048243A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020007011228A KR100354203B1 (ko) 1999-02-09 2000-02-02 가요성 배선 기판, 필름 캐리어, 테이프 형상 반도체장치, 반도체 장치 및 그의 제조방법, 회로 기판 및 전자기기

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/31402 1999-02-09
JP3140299 1999-02-09

Publications (1)

Publication Number Publication Date
WO2000048243A1 true WO2000048243A1 (fr) 2000-08-17

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PCT/JP2000/000552 WO2000048243A1 (fr) 1999-02-09 2000-02-02 Substrat de circuit imprime flexible, bande porte-puces, dispositif a semiconducteur sur bande, dispositif a semiconducteur, procede de fabrication de semiconducteur, substrat de circuit, et dispositif electronique

Country Status (2)

Country Link
KR (1) KR100354203B1 (fr)
WO (1) WO2000048243A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006191111A (ja) * 2005-01-04 2006-07-20 Samsung Electronics Co Ltd カッティングパターンが形成されたフレキシブルプリント回路基板用原板及びこれをカッティングしたフレキシブルプリント回路基板を含む表示装置
US7282389B2 (en) 2003-11-14 2007-10-16 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7316939B2 (en) 2003-11-14 2008-01-08 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7323365B2 (en) 2003-11-14 2008-01-29 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7656089B2 (en) 2004-12-07 2010-02-02 Samsung Sdi Co., Ltd. Tape carrier package on reel and plasma display device using the same
KR100947587B1 (ko) 2003-04-17 2010-03-15 삼성테크윈 주식회사 반도체 패키지용 기판
US7687317B2 (en) 2007-03-29 2010-03-30 Seiko Epson Corporation Semiconductor device having tape carrier with bendable region
WO2024156378A1 (fr) * 2023-01-25 2024-08-02 Interplex NAS Electronics GmbH Structure de connexion électrique

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03108789A (ja) * 1989-09-22 1991-05-08 Seiko Epson Corp フレキシブル基板の構造
JPH10116862A (ja) * 1996-10-11 1998-05-06 Texas Instr Japan Ltd テープキャリアパッケージ
JPH10242213A (ja) * 1997-02-27 1998-09-11 Seiko Epson Corp フレキシブル基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03108789A (ja) * 1989-09-22 1991-05-08 Seiko Epson Corp フレキシブル基板の構造
JPH10116862A (ja) * 1996-10-11 1998-05-06 Texas Instr Japan Ltd テープキャリアパッケージ
JPH10242213A (ja) * 1997-02-27 1998-09-11 Seiko Epson Corp フレキシブル基板

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100947587B1 (ko) 2003-04-17 2010-03-15 삼성테크윈 주식회사 반도체 패키지용 기판
US7282389B2 (en) 2003-11-14 2007-10-16 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7316939B2 (en) 2003-11-14 2008-01-08 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7323365B2 (en) 2003-11-14 2008-01-29 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7582955B2 (en) 2003-11-14 2009-09-01 Seiko Epson Corporation Semiconductor device manufacturing method and manufacturing apparatus
US7656089B2 (en) 2004-12-07 2010-02-02 Samsung Sdi Co., Ltd. Tape carrier package on reel and plasma display device using the same
JP2006191111A (ja) * 2005-01-04 2006-07-20 Samsung Electronics Co Ltd カッティングパターンが形成されたフレキシブルプリント回路基板用原板及びこれをカッティングしたフレキシブルプリント回路基板を含む表示装置
TWI402585B (zh) * 2005-01-04 2013-07-21 Samsung Display Co Ltd 具有裁切圖案之可撓性印刷電路膜母板以及設有由該母板裁切之可撓性印刷電路膜的顯示裝置
US7687317B2 (en) 2007-03-29 2010-03-30 Seiko Epson Corporation Semiconductor device having tape carrier with bendable region
WO2024156378A1 (fr) * 2023-01-25 2024-08-02 Interplex NAS Electronics GmbH Structure de connexion électrique

Also Published As

Publication number Publication date
KR20010042563A (ko) 2001-05-25
KR100354203B1 (ko) 2002-09-26

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