WO2000033199A1 - Circuit de traitement de signal - Google Patents

Circuit de traitement de signal Download PDF

Info

Publication number
WO2000033199A1
WO2000033199A1 PCT/JP1998/005449 JP9805449W WO0033199A1 WO 2000033199 A1 WO2000033199 A1 WO 2000033199A1 JP 9805449 W JP9805449 W JP 9805449W WO 0033199 A1 WO0033199 A1 WO 0033199A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
processing circuit
bus
input
signal
Prior art date
Application number
PCT/JP1998/005449
Other languages
English (en)
Japanese (ja)
Inventor
Hiromi Watanabe
Takashi Nakamoto
Hiroshi Hatae
Junko Nakase
Masaru Hase
Kenichi Iwata
Hiroshi Yamada
Yutaka Okada
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/005449 priority Critical patent/WO2000033199A1/fr
Publication of WO2000033199A1 publication Critical patent/WO2000033199A1/fr
Priority to US09/870,630 priority patent/US6889274B2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Definitions

  • the present invention relates to a signal processing circuit, and more particularly to a signal processing circuit for processing a large amount of data at a high speed using a microphone processor, such as processing of television image data.
  • the data transfer rate required between the microprocessor and the memory is 1 OOM. exceeds b / s.
  • the system bus is occupied by the data transfer, and the problem that the signal processing function that the processor should originally perform is alienated is solved.
  • a local memory bus that transfers video data independently of the above system bus is provided in the local memory that stores and stores video data, etc., and the local memory bus manages the right to use the bus of the local memory bus.
  • a local memory that stores and stores video data can shorten the signal processing time of the processor by directly accessing the local memory from an input / output circuit that inputs or outputs video.
  • high-speed and high-parallel signal processing other than arithmetic that is suitable for processing using the arithmetic unit inside the processor is executed by a dedicated arithmetic circuit. As a result, the processing speed can be improved.
  • the local memory can be accessed from a circuit that inputs and outputs video signals, from a video processing circuit that performs video signal processing using a dedicated arithmetic unit, and accessed from a processor. Is the most suitable configuration. Disclosure of the invention
  • each circuit and processor cannot function effectively without a connection configuration for accessing the oral memory from the video input / output circuit, the video processing circuit, and the processor and a circuit for controlling the connection.
  • the inventors of the present invention have clarified that the above-described conventional image processing apparatus has the above-described background art that has a problem that the load on the processor is large because the processor controls the connection. Was.
  • An object of the present invention is to provide a processor and data connected via a bus.
  • An object of the present invention is to provide a signal processing device which maximizes the performance of the processor, the data input / output circuit, and the dedicated processing circuit in a data input / output circuit, a dedicated processing circuit, and a signal processing device having memory.
  • Another object of the present invention is to provide a signal processing circuit provided with a system bus connected to a micro processor and a local memory bus for transferring data independently of the system bus in a local memory.
  • the purpose of the present invention is to provide a signal processing circuit that allows the microprocessor processor to directly access the local memory while the dedicated processing circuit is operating.
  • a signal processing circuit of the present invention has a data input / output circuit, a microprocessor, a dedicated processing circuit, a local memory and a memory access control circuit connected via a bus.
  • a signal processing circuit In one signal processing circuit,
  • the bus has a system bus connected to the data input / output circuit, microprocessor, special-purpose processing circuit, and memory access control circuit, and a mouth memory bus connected to the mouth memory. Between the system bus and the local memory bus, between the first local bus of the dedicated processing circuit and the local memory bus, and between the second local bus and the local memory bus of the data input / output circuit. A first, a second, and a third connection circuit, which is provided between each of the first and second circuits and whose priority connection is controlled by the memory access control circuit, is provided.
  • the system bus and the local memory bus have a data bus, an address bus, and control lines, and the system bus transfers control information between data input / output circuits, a dedicated processing circuit, and a memory access control circuit. In addition to being used to transfer data processed or processed by each circuit, the microprocessor accesses local memory through the first connection circuit.
  • the local memory bus transfers data to and from a dedicated processing circuit by a second connection circuit, and transfers data to and from a data input / output circuit by a third connection circuit. I do.
  • data transfer to and from local memory via the second local bus, the first local bus, and the system bus is performed by a data input / output circuit, a dedicated processing circuit, and a micro processor, respectively.
  • each circuit sends a request to use the oral memory bus to the memory access control circuit, and the memory access control circuit responds according to a preset priority.
  • Control the first connection circuit, the second connection circuit, and the third connection circuit to determine one bus to be used by the local memory bus, and to disconnect the other memory bus from the other bus.
  • the independent operation of each circuit is not hindered, the performance of each circuit can be enhanced because the ratio of each circuit operating in parallel is increased.
  • the microprocessor can directly access the low power memory by the first connection circuit, the access snoop rate can be improved. Can be increased.
  • the present invention is effective when processing a large amount of data in real time, such as encoding processing and decoding processing of high-efficiency compressed image data.
  • the following embodiment is applied to a signal processing circuit for image data.
  • FIG. 1 is a diagram showing a first embodiment of a signal processing circuit according to the present invention.
  • FIG. 2 is a diagram showing a configuration of the video input / output circuit 3 of FIG.
  • FIG. 3 is a diagram showing a configuration of the video processing circuit 4 of FIG.
  • FIG. 4 shows a configuration of the memory access controller 5 of FIG.
  • FIG. 5 is a diagram showing a second embodiment of the signal processing circuit according to the present invention.
  • FIG. 6 is a diagram showing a third embodiment of the signal processing circuit according to the present invention.
  • FIG. 7 is a diagram showing a fourth embodiment of the signal processing circuit according to the present invention.
  • C Best Mode for Carrying Out the Invention FIG. 1 shows a first embodiment of a signal processing circuit according to the present invention.
  • the present embodiment constitutes a video processing integrated circuit for processing image data.
  • a video input / output circuit 3 as a data input / output circuit, a microprocessor 2, a video processing circuit 4 as a dedicated processing circuit, a memory access control circuit 5, and a local memory connected via a system bus B1.
  • a bus bridge 10, that is, a bus bit number conversion means is provided at a portion where the system bus B 1 and the local memory bus B 2 are directly connected via the first bus connector 8. .
  • system bus B 1 and the local memory bus B 2 are shown as single lines, they include a data bus, an address bus, and a control line, and transfer control information to / from each circuit and transfer processing data in parallel. .
  • the video input / output circuit 3 is connected to the local memory bus B2 through the bus connector 6 connected to the local bus B3, so that the local memory 9 and the input line Pl and the output line P1 are connected. Between 2 Data transfer.
  • the video processing circuit 4 is connected to the local memory bus B2 through the bus connector 7 connected to the local bus B4, and thereby performs data transfer with the local memory 9.
  • the local memory 9 is used for storing input video data and recording display video data.
  • FIG. 2 is a diagram showing a configuration of the video input / output circuit 3 of FIG.
  • the control register 31 of the video input / output circuit 3 is connected to the microprocessor 2 via the system bus B1.
  • a plurality of pieces of control information for operating the video input / output circuit 3 are set in the control register 31. For example, an address or the like in which the display video in the oral memory 9 is recorded.
  • the control information stored in the control register 31 is read out by the control circuit 32, and the video input processing circuit 33, the video input buffer 34, the video output processing circuit 35, and the video output buffer 3 6 to control the input / output processing of the input video and output video data, and to the memory access control circuit 5 via the signal line S1 to the local memory bus B2.
  • the access request is issued and the permission signal is received from the memory access control circuit 5 through the signal line S2, the low power memory 9 accessed by the second local bus B3 is also controlled.
  • a memory access request is sent via the signal line S1 to the memory access controller. Then, the memory access controller 5 judges the priority and outputs an access permission signal through the signal line S2 when the memory access controller 5 is available.
  • the local bus B4 and the system bus B1 can be connected to the local memory bus B1. Independent from Linox B2 force.
  • FIG. 3 is a diagram showing a configuration of the video processing circuit 4 in FIG.
  • the microphone port processor 2 and the video processing circuit 4 are connected to various video processing circuits via a system bus B1.
  • the example in FIG. 3 (a) is a video processing circuit on the premise of an encoding process such as MPEG.
  • the encoding / decoding circuit 41, the discrete cosine transform circuit Z, the inverse discrete cosine transform circuit 42, the MPEG A motion detection circuit / motion compensation circuit 43 used for image encoding and decoding processes such as the above is connected.
  • Each of the circuits 41 to 43 operates to perform signal processing of a predetermined function according to a control instruction transferred from the system bus B1.
  • the circuits 41 to 43 are mutually connected by a first local bus B4, and data transfer between them is performed.
  • the controller 44 for controlling the entire video processing circuit 4 includes a memory access control circuit 5 when each of the circuits 41 to 43 needs to transfer data to and from the local memory 9. Request the bus right of the low memory bus B2 through the signal line S3, and the memory access control circuit When the access permission signal is received from 5 via the signal line S 4, the local memory 9 accessed by the first oral bus B 4 is also controlled.
  • the video processing circuit 4 When performing data transfer with the local memory 9, the video processing circuit 4 makes a memory access request to the memory access controller 5 via the signal line S 3, and The access controller 5 determines the priority and outputs an enable signal through the signal line S4 when available, and furthermore, opens the bus connector 7 to open the local memory bus through the local bus B4. By closing connectors 6 and 8 at the same time as connecting to B2, local bus B3 and system bus B1 are made independent of the local memory bus B2.
  • Fig. 3 (b) shows the detailed configuration of the motion detection circuit Z motion compensation circuit 43 in (a).
  • the motion detection arithmetic unit, the motion compensation arithmetic unit 44 43 and the nos 81 The instruction register 431, the status register 43, the data register 43, 43, the memory 43, 43, and the bus controller 43 RU
  • FIG. 4 is a diagram showing a configuration of the memory access controller 5 of FIG.
  • the memory access controller 5 has a memory priority designation register 51, and the micro processor 2 sends the local memory designation register 51 to the memory priority designation register 51 via the system bus B1. Indicates the order of priority for occupancy of the memory B2. According to this set order, The local bus B 3, the local bus B 3, and the system bus B 1 acquire the bus right of the local memory bus B 2, and pass through the memory access right control circuit 53, and the line S 5, The connectors 6, 7, and 8 are controlled by S6 and S7, and data transmission to and from the local memory 9 is performed.
  • the above embodiment is a video processing circuit based on image data such as MPEG.
  • the present invention does not specify the video processing circuit itself, and the video processing circuit 4 includes various other processing circuits. be able to.
  • FIG. 5 shows another embodiment of the signal processing circuit according to the present invention. This embodiment constitutes a video processing integrated circuit for processing image data.
  • an audio signal processing circuit is added to the video processing of the first embodiment. Audio signals require less transfer speed and capacity than video signals, and their signal processing can be performed by the microprocessor 2. For this reason, a sound input / output circuit 20 is provided so as to be directly connected to the system memory bus B1 by a bus. When sound data transfer occurs in the sound input / output circuit 20, an interrupt signal is given to the processor 2 via the signal line S 8, and the microprocessor 2 detects the interrupt, and Data transfer control with the sound input / output circuit 20 is performed.
  • the processing of video data and the configuration and operation of each circuit are the same as in the embodiment of FIG. Therefore, the same parts are denoted by the same reference numerals as in FIG. 1 and their description is omitted.
  • FIG. 6 shows a third embodiment of the signal processing circuit according to the present invention.
  • the present embodiment constitutes a video processing integrated circuit for processing image data.
  • a processing circuit for other signals is added.
  • a serial data input / output circuit 21 having input / output terminals P5 and P6 is added. Examples of the serial data include compressed video signals and audio signals. Because of the compression, the required transfer speed and capacity are smaller than those of the video signal, and the signal processing can be performed by the microphone port processor 2. Therefore, a serial data input / output circuit 21 is provided so as to be connected to the system memory bus B1.
  • serial data transfer occurs in the serial data input / output circuit 21
  • an interrupt signal is given to the processor 2 via the signal line S 9, and the microprocessor 2 detects the interrupt and It operates to perform data transfer control with the serial data input / output circuit 20. Since the processing of the video data and the configuration and operation of each circuit are the same as those of the embodiment of FIG. 1, the same parts are denoted by the same reference numerals as in FIG. 1 and their explanation is omitted.
  • FIG. 7 shows a fourth embodiment of the signal processing circuit according to the present invention.
  • a video processing integrated circuit for processing image data is configured.
  • the status register 441 and the instruction register 442 in the video processing circuit 4 are accessed according to the periodic interrupt signal Tl generated by the mask 23.
  • the status register 4 41 is a register that indicates the current state of the video processing circuit 4, and the simplest information is that if there is a process currently being executed, the process is being executed. The flag is shown.
  • the instruction register 422 is a register for instructing the video processing circuit 4 to execute an instruction that the microprocessor 2 should execute.
  • the video processing circuit 4 operates to execute the instruction specified in the instruction register 422.
  • the operation is based on the interrupt signal T1 from the timer 2, the status register 4 21 is periodically read out, the microprocessor 2 determines whether or not an instruction is given to the video processing circuit 4, and the instruction is displayed on the video. When the processing circuit 4 is accepted, the microprocessor 2 operates to issue an instruction to the instruction register 4222.
  • connection configuration and the local memory bus access right control of the present invention make it possible to maximize the performance of the microprocessor, video, audio input / output circuit, and video processing circuit.
  • image processing since the amount of input / output data of image data to / from the local memory 9 is large, by controlling the connection circuits 6, 7, and 8, the oral memory 9 and the micro processor 9 are controlled.
  • the data transfer between the local bus B 2 and the system bus can be performed in parallel with the input / output circuit 3 and the processing circuit 4 without using a register or the like. High-speed processing is possible because data is directly transferred to and from 1.
  • the signal processing circuit for video processing in which the present invention is particularly effective has been described.
  • the present invention is not limited to the above embodiment, and is applied to a signal processing device which needs to process a large amount of data in real time. Clearly what you can do.
  • the bus bridge 10 is shown only in the first embodiment, but can be adopted in other embodiments.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne un circuit de traitement de signal ayant deux bus indépendants, un bus système (B1) de microprocesseur (2) et un bus de mémoire locale (B2) d'une mémoire locale (9). Le bus système (B1) est relié à un circuit d'entrée-sortie vidéo (3), à un circuit de traitement vidéo (4) et à un circuit de commande d'accès mémoire (5), de manière à transmettre l'information de commande aux circuits et à transmettre les données traitées par les circuits. En conséquence, il est possible d'accéder directement à la mémoire locale (9) par le bus système et un premier circuit de liaison (8). Le bus de mémoire locale est relié à un premier bus local (B4) pour la transmission des données vers/depuis le circuit de traitement vidéo via un second circuit de liaison (7), et il est relié à un second bus local (B3) pour la transmission vers/depuis le circuit d'entrée-sortie vidéo (3) via un troisième circuit de liaison (6). Dans ces conditions, les perfomances du microprocesseur (2), du circuit d'entrée-sortie vidéo (3) et du circuit de traitement vidéo (4) peuvent être exploitées.
PCT/JP1998/005449 1998-12-03 1998-12-03 Circuit de traitement de signal WO2000033199A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1998/005449 WO2000033199A1 (fr) 1998-12-03 1998-12-03 Circuit de traitement de signal
US09/870,630 US6889274B2 (en) 1998-12-03 2001-06-01 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/005449 WO2000033199A1 (fr) 1998-12-03 1998-12-03 Circuit de traitement de signal

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/870,630 Continuation US6889274B2 (en) 1998-12-03 2001-06-01 Signal processing circuit

Publications (1)

Publication Number Publication Date
WO2000033199A1 true WO2000033199A1 (fr) 2000-06-08

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PCT/JP1998/005449 WO2000033199A1 (fr) 1998-12-03 1998-12-03 Circuit de traitement de signal

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005198289A (ja) * 2003-12-30 2005-07-21 Samsung Electronics Co Ltd データ処理システムおよびデータ処理方法
JP2007336023A (ja) * 2006-06-13 2007-12-27 Oki Electric Ind Co Ltd 動画処理装置
WO2008007419A1 (fr) * 2006-07-10 2008-01-17 Fujitsu Microelectronics Limited Contrôleur de mémoire

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01116682A (ja) * 1987-10-30 1989-05-09 Toshiba Corp 監視表示装置
JPH06205223A (ja) * 1992-05-07 1994-07-22 Murata Mach Ltd 画像処理装置
JPH1048048A (ja) * 1996-07-31 1998-02-20 Ricoh Co Ltd 画像評価方法と装置並びにこれらに用いる画像フレア計測用パターン

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01116682A (ja) * 1987-10-30 1989-05-09 Toshiba Corp 監視表示装置
JPH06205223A (ja) * 1992-05-07 1994-07-22 Murata Mach Ltd 画像処理装置
JPH1048048A (ja) * 1996-07-31 1998-02-20 Ricoh Co Ltd 画像評価方法と装置並びにこれらに用いる画像フレア計測用パターン

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005198289A (ja) * 2003-12-30 2005-07-21 Samsung Electronics Co Ltd データ処理システムおよびデータ処理方法
JP2007336023A (ja) * 2006-06-13 2007-12-27 Oki Electric Ind Co Ltd 動画処理装置
JP4610523B2 (ja) * 2006-06-13 2011-01-12 Ｏｋｉセミコンダクタ株式会社 動画処理装置
WO2008007419A1 (fr) * 2006-07-10 2008-01-17 Fujitsu Microelectronics Limited Contrôleur de mémoire

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