WO2000022668A1 - Module electronique, en particulier module multipuce, a metallisation multicouche et son procede de production - Google Patents

Module electronique, en particulier module multipuce, a metallisation multicouche et son procede de production Download PDF

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Publication number
WO2000022668A1
WO2000022668A1 PCT/DE1999/003247 DE9903247W WO0022668A1 WO 2000022668 A1 WO2000022668 A1 WO 2000022668A1 DE 9903247 W DE9903247 W DE 9903247W WO 0022668 A1 WO0022668 A1 WO 0022668A1
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WO
WIPO (PCT)
Prior art keywords
wiring
module
underside
carrier
multilayer wiring
Prior art date
Application number
PCT/DE1999/003247
Other languages
German (de)
English (en)
Inventor
Harry Hedler
Gregor Feiertag
Peter Deml
Franz Petter
Original Assignee
Tyco Electronics Logistics Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tyco Electronics Logistics Ag filed Critical Tyco Electronics Logistics Ag
Priority to JP2000576488A priority Critical patent/JP2002527906A/ja
Publication of WO2000022668A1 publication Critical patent/WO2000022668A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
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    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • Electronic module in particular multichip module, with multi-layer wiring and method for its production
  • the invention relates to an electronic module, in particular a multichip module, with multilayer wiring, on the component side of which at least one IC component is applied, the module being covered on one side on the component side with a hermetic housing, and with contact pads on the underside of the module, with which the contacting and integration of the module into a next higher module level can be established.
  • the invention also relates to a method for producing an electronic module, in particular a multi-chip module, with multi-layer wiring.
  • Multichip modules have been known for some time, by means of which an intermediate carrier substrate with high wiring density, HDI (High Density Interconnect), is introduced as an additional level in the hierarchy of the system structure. Typical of this are the use of several unhoused chips and a high area coverage of the multichip substrate.
  • HDI High Density Interconnect
  • a similar well-known new development relates to the chip size package (CSP), in which a single bare chip is applied to an intermediate carrier substrate that is hardly larger than the chip area, and in which the space-saving contact to the next architecture level directly below the chip area is used becomes.
  • CSP chip size package
  • the technologies of the printed circuit board manufacture enable wiring supports which allow the electrical through-plating from the chip side to the underside by means of through-plating holes which are relatively easy to produce. They are less advantageous with regard to the production of laterally small designs, in particular for multi-chip modules, since the wiring densities are too low.
  • vias in particular cannot be positioned precisely enough between the interconnect levels because of the shrinkage of the laminate materials. Uncertainties of typically up to 200 ⁇ m remain, which is made to fit by coarsening the structure around the Via (Land). Because of the shrinkage, high-density wiring carriers can only be realized if they are not produced on the inexpensive large panels, for example 600 x 600 mm, but on extremely small ones, for example 150 x 150 mm. This makes large-format production in circuit board technology as expensive as thin-film technology.
  • the technologies of thin-film production enable high wiring densities through their structurally fine processes and there are due to the solid carrier materials (the actual carrier for the multi-layer wiring consists of ceramic, silicon, glass or metal) no shrinkage problem.
  • the solid carrier materials the actual carrier for the multi-layer wiring consists of ceramic, silicon, glass or metal
  • other aspects of this technology are problematic, in particular the costly detours to be made when realizing the electrical connection from the carrier top to the carrier bottom, for example drilling or punching holes in the solid core materials, adjustment problems, metallizing the holes, etc.
  • the density the plated-through holes are limited by the substrate thickness and the technology used to produce the hole.
  • there is also a high risk of breakage of the carriers in the thin-film process which, moreover, does not allow a transition to inexpensive large-format production.
  • the present invention has for its object to provide an improved module of the type mentioned, in particular with a reduced overall height, and to provide a method for its production.
  • the object is achieved in a method of the type mentioned at the outset in that multilayer wiring with contact pads on its underside is applied only to the top of a plate-shaped wiring carrier made of solid material, so that IC or other electronic components are electrically and mechanically connected the assembly level of the multi layer wiring are connected, that the component side of the multi-layer wiring is provided with a hermetic housing adhering to its component-free areas, and that the solid carrier material is then removed again and the underside of the multi-layer wiring forming the underside of the module is exposed.
  • the invention achieves the desired improvements by not only the processes of the actual interconnect
  • ultra-thin modules can be produced, although on the one hand the advantages of thin-film technology, in particular the use of solid carrier materials or materials with high temperature stability (up to 400 ° C) remain, while on the other hand a high wiring density can be achieved without restrictions and can be produced with large-format panels, for example 400 x 400 mm.
  • process steps are advantageously saved.
  • a metallic wiring carrier 1 is shown, on the top of which the actual interconnect, i.e.
  • FIG. 1B shows a module in which, compared to FIG.
  • Multi-layer wiring 2 can form.
  • the customary molding compounds can be used, since these are compatible with the insulation materials used as the top layer of the multi-layer wiring 2, such as polyid, PBO, BCB or Ormocere, that is to say they are liable.
  • FIG. IC shows a module in which the next process step, the removal of the carrier material 1, has already been carried out. This can be done, for example, by dissolving the carrier material, in particular by wet chemical etching in one of the commercially available etching systems used, for example, in the highly integrated semiconductor technology.
  • the contact pads 6 are, of course, on the Un ⁇ underside of the multi-layer wiring 2, which are designed to provide 3 of the module with the contacts of the next higher module level via feedthroughs and connections to the conductor rail system the electrical connection of the components exposed.
  • cf. Figure ID for contacting the module solderable material, in particular solder balls 7, applied to the contact pads 6.
  • a passivation layer 15 can be provided for later easier testing of the module, cf. Figure IB.
  • z. B plastic as a carrier material into consideration.
  • FIGS. 2C to 2F show different variants.
  • FIG. 2C shows the result of the etching of pits 8 into the carrier material from the underside, so that the contact points, that is to say the contact pads 6, on the underside of the multilayer wiring 2 are exposed.
  • solderable material 9 eg SnPb
  • solder balls 7 can be electroplated or solder balls 7 using standard methods
  • FIGS. 3A to 3E show a process sequence in which a solder layer 10 is initially applied as an intermediate layer the carrier material is applied, which is then covered with a structured insulation layer 11. According to FIG. 3C, a structured metal level 12 is then produced, which according to FIG. 3D is provided with electronic components and is covered with a hermetic housing 4.
  • a solder layer 10 is initially applied as an intermediate layer the carrier material is applied, which is then covered with a structured insulation layer 11.
  • a structured metal level 12 is then produced, which according to FIG. 3D is provided with electronic components and is covered with a hermetic housing 4.
  • FIG. 3E shows the final result after heating the solder layer 10 and removing the wiring carrier 1, with harmless residues of the solder layer 10 remaining on the solder pads 6 and only there.
  • the metal islands 13 and 14 are connected to one another within the interconnect system of the multilayer wiring 2, which in this special case, which can be produced particularly cost-effectively, consists of only a single metal layer and an insulation layer 12 and 11.
  • a module results in the form of a BGA standard housing, the overall height of which is extremely low, since the remaining multilayer wiring 2, the actual interconnect, has an overall height of less than approximately 100 ⁇ m, usually even less than 60 ⁇ m. Since the chips 3 in the thinned form are typically approximately 300 ⁇ m high and the hermetic housing 4 again has a similar height, minimum housing heights (without
  • Balls of around 600 ⁇ m, while in laminate technology alone the well-known interconnect, i.e. the wiring carrier with multilayer wiring on top, is between 500 ⁇ m and 1000 ⁇ m high.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un module électronique à métallisation multicouche. La face composants de la métallisation multicouche (2) adhère, au niveau de ses zones sans composants, au boîtier hermétique (4). La face inférieure de la métallisation multicouche (2) d'une hauteur inférieure à environ 100 νm constitue directement, c'est-à-dire sans support d'interconnexion supplémentaire (1), la face inférieure du module.
PCT/DE1999/003247 1998-10-09 1999-10-08 Module electronique, en particulier module multipuce, a metallisation multicouche et son procede de production WO2000022668A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000576488A JP2002527906A (ja) 1998-10-09 1999-10-08 電子モジュール、特に多層金属配線層を有するマルチチップ・モジュールおよびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19846662A DE19846662A1 (de) 1998-10-09 1998-10-09 Elektronisches Modul, insbesondere Multichipmodul mit einer Mehrlagenverdrahtung und Verfahren zu seiner Herstellung
DE19846662.5 1998-10-09

Publications (1)

Publication Number Publication Date
WO2000022668A1 true WO2000022668A1 (fr) 2000-04-20

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PCT/DE1999/003247 WO2000022668A1 (fr) 1998-10-09 1999-10-08 Module electronique, en particulier module multipuce, a metallisation multicouche et son procede de production

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DE (1) DE19846662A1 (fr)
WO (1) WO2000022668A1 (fr)

Cited By (1)

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EP1180792A1 (fr) * 2000-08-09 2002-02-20 Kostat Semiconductor Co., Ltd. Boítier pour semi-conducteur

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DE10201782A1 (de) * 2002-01-17 2003-03-27 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens einem Halbleiterchip und Verfahren zu seiner Herstellung
US6794273B2 (en) * 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
DE102006001429A1 (de) * 2006-01-10 2007-03-22 Infineon Technologies Ag Nutzen und Halbleiterbauteil aus einer Verbundplatte mit Halbleiterchips und Kunststoffgehäusemasse sowie Verfahren zur Herstellung desselben
JP5218606B2 (ja) * 2011-06-13 2013-06-26 大日本印刷株式会社 半導体装置用回路部材の製造方法とそれを用いた樹脂封止型半導体装置の製造方法
JP5807815B2 (ja) * 2013-11-01 2015-11-10 大日本印刷株式会社 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法
DE102015122282A1 (de) * 2015-12-18 2017-06-22 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zu dessen Herstellung

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US5218759A (en) * 1991-03-18 1993-06-15 Motorola, Inc. Method of making a transfer molded semiconductor device
US5492266A (en) * 1994-08-31 1996-02-20 International Business Machines Corporation Fine pitch solder deposits on printed circuit board process and product
EP0751556A1 (fr) * 1995-06-30 1997-01-02 Commissariat A L'energie Atomique Procédé de réalisation d'un substrat d'interconnexion permettant de connecter une puce sur un substrat de réception

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