Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/4076—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
  • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
  • G11C7/1093—Input synchronization
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
  • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

• the present invention relates to a clock-synchronous semiconductor device that takes in an input signal input from the outside in synchronization with a clock signal.
• Synchronous DRAM operates at high speed in synchronization with an external clock signal input from the outside, so that data can be written and read at high speed. It has been developed with a maximum operating frequency of 100 MHz or more.
• FIG. 1 shows a configuration example of an input interface section in this type of semiconductor device.
• the input interface section 1 has a plurality of input signal receiving circuits 3.
• Each input signal capture circuit 3 receives an external clock signal CLK and an input signal Din (a) (or Mn (b)).
• the input signal capturing circuit 3 outputs an internal signal Doutz (a) ⁇ Doutx (a) (or Doutz (b) ⁇ Doutx (b)) to the internal circuit 5.
• the internal signal Doutz is a signal having the same phase as the input signal Din
• the internal signal Doutx is a signal having a phase opposite to that of the input signal Din.
• the above-described input signal capture circuit 3 converts the input signal Din It is captured in synchronization with the internal clock signal CLK and output to the internal circuit 5 as internal signals Dout z and Doutx.
• FIG. 2 shows an example of a timing at which the input signal D in is fetched by the input interface unit 1 shown in FIG.
• the input period of the input signal D in is defined by the setup time tDS and the hold time tDH with respect to the rise of the external clock signal CLK.
• the setup time tDS is the minimum time required to determine the input signal Din before the rise of the external clock signal CLK
• the hold time tDH is the external clock signal. This is the minimum time required to hold the input signal D in after the rise of the lock signal CLK.
• the input signal Din is captured at the rising edge of the clock signal CLK, and the internal signals Doutz and Doutx are generated. .
• the setup time tDS and the hold time tDH are the worst values in consideration of the variation in characteristics between semiconductor devices that occur during the semiconductor manufacturing process, and the temperature and power supply voltage when operating the semiconductor devices. It is determined so that the input signal D in can be reliably captured even under the above conditions.
• a user who mounts this type of semiconductor device in a system device determines the input signal D in to be input to the semiconductor device before the setup time tDS and sets the hold time as follows. It is necessary to design the timing of the system equipment so as to maintain tDH or more.
• the system device requires a circuit that satisfies the setup time tDS and a circuit that satisfies the hold time tDH to generate each input signal D in. It was increasing and complicated.
• the cycle of the external clock signal CLK is generally 10 ns or less.
• the margin of the timing design on the system device side is reduced, and the timing It was difficult to create the input signal D in according to the mining rules.
• the system unit determines whether the external clock signal CLK rises or falls one clock cycle before. And the timing design was very difficult when the period of the external clock signal CLK was short.
• the inventor of the present invention outputs the input signal Din from the system device at the same time as the switching of the external clock signal, and outputs the external clock signal CLK in the input interface section 1.
• a clock signal delayed by a predetermined time with respect to the clock signal was created, and it was considered that the input signal D in was fetched in synchronization with the clock signal.
• FIG. 3 shows the configuration of the input interface section 1 considered by the present inventor.
• the input interface unit 1 includes the above-described input signal capturing circuit 3 and the inverter 7.
• Inverter 7 receives an external clock signal CLK and outputs an inverted clock signal / CLK of the external clock signal CLK.
• Each input signal capture circuit 3 receives an inverted clock signal / CLK.
• Other configurations are the same as those shown in FIG.
• FIG. 4 shows the timing of capturing the input signal Din in the input interface section 1 shown in FIG.
• the input period of the input signal Din is defined by the setup time tDSl and the hold time tDHl with respect to the rising edge of the inverted clock signal / CLK.
• FIG. 5 shows the configuration of another input interface 1 considered by the present inventors.
• the input interface section 1 has the input signal capturing circuit 3 and the delay circuit 9 described above.
• the delay circuit 9 receives the external clock signal CLK, and outputs a delayed clock signal DCLK delayed by a predetermined time with respect to the external clock signal CLK.
• Each input signal capture circuit 3 receives the delayed clock signal DCLK.
• Other configurations are the same as those shown in FIG.
• the delay circuit 9 is composed of, for example, a capacitor and a resistor, and has a predetermined time constant.
• FIG. 6 shows the timing of taking in the input signal D in the input interface section 1 shown in FIG.
• the input signal D in is received at the rising edge of the delayed clock signal DCLK, which is delayed by the delay time De 1 ay from the rising edge of the external clock signal CLK.
• the input period of the input signal D in is defined by the setup time tDS2 and the hold time tDH2 with respect to the rise of the delay clock signal DCLK.
• the input period of the input signal D in can be made shorter than the delay time De Lay, the time tDS from the rise of the external clock signal CLK to the end of the delay is determined. In this case, only the hold time tDH for the rise of the external clock signal CLK needs to be satisfied.
• the user can change the input signal D in on the system device at the same time as the rising of the external clock signal CLK.
• the evening timing In order to generate the input signal D in after the rise, it is only necessary to design the evening timing so that the hold time tDH is maintained. That is, timing design becomes easy.
• the above considerations by the inventor are not yet known.
• the input interface unit 1 having the inverter 7 shown in FIG. 3 uses the inverted clock signal / CLK obtained by inverting the external clock signal CLK. Input signal D in is being acquired. For this reason, the timing of outputting the internal signals Dout z and Doutx to the internal circuit 5 is almost half a clock later than the rising timing of the external clock signal CLK.
• the main input / output interface 1 is applied to the address signal / data signal input section of a chip-synchronous memory LSI such as a synchronous DRAM, the read time and the write time may be reduced. Access time, such as time, is delayed by half a clock.
• This delay has a small effect on the access time when the frequency of the external clock signal CLK is high, but has a large effect on the access time as the frequency of the external clock signal CLK becomes low. There was a problem that it became worse.
• the access time of the memory LSI to which the interface section 1 is applied is determined by the time from when the memory cell at the specified address is selected and when the selected memory cell is output to the outside. It is almost equal to the sum of the required time and the time for a half clock of the external clock signal CLK.
• the former time is almost constant regardless of the frequency of the external clock signal CLK, but the latter time becomes longer as the frequency of the external clock signal CLK becomes lower.
• the input interface section 1 having the delay circuit 9 shown in FIG. 5 uses the delayed clock signal D CLK obtained by delaying the external clock signal CLK to generate the input signal D. In is taken in.
• the delay time D delay of the delay circuit 9 is determined by the semiconductor produced in the semiconductor manufacturing process. Variations in characteristics between devices, and changes due to temperature, power supply voltage, etc. when operating semiconductor devices. This change does not depend on the frequency of the external clock signal CLK.
• the influence of the variation in the delay time Delay increases as the frequency of the external clock signal CLK increases. Specifically, for example, when the delay time D delay of the delay circuit 9 varies from 2 to 7 ns, the frequency of the external clock signal CLK becomes 125 MHz (clock cycle 8 ns). In this case, the margin between the maximum value of the delay time Delay and the clock cycle is only Ins, and it is difficult to design the timing inside the semiconductor device.
• Semiconductor device manufacturing processes include a single-wafer processing process in which wafers on which a plurality of semiconductor devices are formed are processed one by one, and a batch processing process in which a plurality of wafers are processed simultaneously.
• the single-wafer processing step is, for example, a photolithography process
• the batch processing step is, for example, a heat treatment step.
• characteristics tend to vary between semiconductor devices on the same wafer, and in a batch processing step, characteristics tend to vary between semiconductor devices on different wafers.
• the variations in the maximum operating frequency of the manufactured semiconductor device have a peak distribution with a peak at the center, as shown in Fig. 7. Is shown.
• Semiconductor devices are classified into three types, for example, the fastest product, the high-speed product, and the standard product according to the highest operating frequency, based on a probe test in the wafer state and a screening test after assembly.
• the input interface section 1 having the inverter 7 shown in FIG. 3 is applied to a semiconductor device, the influence on the access time becomes larger in the standard product. A semiconductor device becomes defective when the access time exceeds a predetermined time.
• An object of the present invention is to provide a semiconductor device which can reliably take in an input signal irrespective of the frequency of an external clock signal.
• Another object of the present invention is to set the timing of an internal clock signal for capturing an input signal during operation of a semiconductor device.
• Another object of the present invention is to set the timing of an internal clock signal for capturing an input signal in a semiconductor manufacturing process.
• the clock timing selection unit outputs a predetermined clock selection signal.
• the clock generation unit receives the clock selection signal and the external clock signal, and generates a clock signal having a predetermined timing according to the signal value of the clock selection signal. Generate.
• the input signal capturing section captures the input signal in synchronization with the clock signal output from the clock generating section. For this reason, the input signal acquisition unit uses the clock signal with the optimal timing according to the frequency of the external clock signal to be used, etc., to obtain the input signal (address signal, delay signal, etc.). ) Can be imported. That is, the input signal can be reliably captured regardless of the frequency of the external clock signal.
• the clock generation unit includes a plurality of internal clock generation circuits, and each of the internal clock generation circuits has a phase inverted from that of the external clock signal.
• a predetermined time delay from the external clock signal Generates internal clock signal.
• the input signal capturing unit captures an input signal using the selected internal clock signal. For this reason, the input capture unit can capture the input signal even when the input signal is input simultaneously with the external clock signal edge timing. As a result, it is possible to relax the rules for the input timing of the input signal, and it becomes easy to design the timing of the system device on which the semiconductor device is mounted.
• the first internal clock generation circuit generates an inverted internal clock signal whose phase is inverted with respect to the external clock signal.
• the second internal clock generation circuit generates a delayed internal clock signal delayed by the delay circuit with respect to the external clock signal.
• the clock generation unit uses the first clock generation unit to invert the phase of the external clock signal. Outputs inverted internal clock signal.
• the clock generator generates a delayed internal clock signal by the delay circuit of the second clock generator when the clock selection signal has the other signal value. , Output. Therefore, for example, the clock timing selection unit changes the signal value of the clock selection signal to one value according to the high / low frequency of the external clock signal.
• the input signal capturing unit obtains the input signal with an inverted internal clock signal that depends on the cycle of the external clock signal.
• the input signal can be captured by a delayed internal clock signal that does not depend on the period of the external clock signal. That is, the input signal capturing section can capture the input signal at the optimum and fastest timing in accordance with the frequency of the external clock signal.
• the clock selection information is set in the selection information setting section.
• the clock timing selection section outputs a clock selection signal based on the clock selection information. Therefore, the clock selection information can be set in advance when the semiconductor device operates.
• the selection information setting section is constituted by a register that can be set from the outside. The setting of the clock selection information is performed, for example, by accessing this register on a system device equipped with a semiconductor device.
• the clock timing selection unit outputs a clock selection signal having a signal value according to the stored value of the register.
• the selection information setting section is constituted by a fuse.
• Clock selection information is set by blowing and unfusing the fuse in the test process.
• the clock timing selection section outputs a clock selection signal having a signal value according to whether or not the fuse is blown. For this reason, for example, the fuse is blown and unblown according to the maximum operating frequency evaluated in the probe test, so that the optimal clock selection information for the manufactured semiconductor device is set.
• the selection information setting section is constituted by a bonding pad and a bonding wire.
• Clock selection information is set by changing the connection destination of the bonding wire connected to the bonding pad during the assembly process.
• the clock timing selection unit outputs a clock selection signal having a signal value corresponding to a voltage value applied to a bonding wire connected to the bonding pad.
• the selection information setting section is constituted by a conductive film formed at a predetermined position on the semiconductor substrate corresponding to the pattern of the pattern of the photomask.
• Clock selection information is set by switching a photomask used in the semiconductor manufacturing process.
• the clock timing selection unit outputs a clock selection signal having a signal value according to a voltage value of a connection destination of the conductive film.
• the clock selection information is set during the photolithography process, which is a normal semiconductor manufacturing process, and during the etching process. Therefore, clock selection information is set without providing a special process.
• the clock timing selection unit includes a frequency detection circuit that detects the frequency of the external clock signal.
• the clock timing selection unit automatically selects the internal clock signal according to the detected frequency of the external clock signal.
• FIG. 1 is a configuration diagram showing an input interface unit in a conventional semiconductor device.
• FIG. 2 is a timing chart showing the operation of capturing an input signal in the input interface unit of FIG.
• FIG. 3 is a configuration diagram showing an input interface section considered by the present inventors.
• FIG. 4 is a timing diagram showing the operation of capturing an input signal in the input interface section of FIG.
• FIG. 5 is a configuration diagram showing another input / output interface section considered by the present inventors.
• FIG. 6 is a timing chart showing the operation of capturing an input signal in the input interface section of FIG.
• FIG. 7 is an explanatory diagram showing an example of a variation in the maximum operating frequency of a plurality of manufactured semiconductor devices.
• FIG. 8 is a principle configuration diagram in Embodiment 1 of the present invention.
• FIG. 9 is an overall configuration diagram showing Embodiment 1 of the semiconductor device of the present invention ⁇ ).
• FIG. 10 is a circuit diagram showing a mode register.
• Figure 11 is a circuit diagram showing the clock generation circuit in the clock control unit. It is a road configuration diagram.
• FIG. 12 is a circuit configuration diagram showing an input signal capturing circuit in an input buffer.
• FIG. 13 is a timing chart showing an internal clock signal and an internal clock inverted signal.
• FIG. 14 is a timing chart showing the operation of capturing an input signal when the clock selection signal is at a low level.
• FIG. 15 is a timing chart showing the operation of capturing an input signal when the clock selection signal is at a high level.
• FIG. 16 is a circuit configuration diagram showing one mode of a selection information setting unit in Embodiment 2 of the semiconductor device of the present invention.
• FIG. 17 is a configuration diagram showing one mode of a selection information setting section in Embodiment 3 of the semiconductor device of the present invention.
• FIG. 18 is a circuit configuration diagram showing one embodiment of a selection information setting section in Embodiment 4 of the semiconductor device of the present invention.
• FIG. 19 is a circuit configuration diagram showing one mode of a frequency detection circuit in Embodiment 5 of the semiconductor device of the present invention.
• FIG. 20 is a timing chart showing the operation of the frequency detection circuit of FIG.
• FIG. 21 is an evening timing diagram illustrating another operation of the frequency detection circuit of FIG.
• FIG. 22 is a timing chart showing an example in which the setup time tDS for the rising of the external clock signal CLK is specified.
• FIG. 8 is a principle configuration diagram in Embodiment 1 of the semiconductor device of the present invention. Is shown.
• the semiconductor device includes an input signal capturing unit that captures an input signal input from the outside in synchronization with a clock signal, and a clock timing selection unit that outputs a clock selection signal.
• an internal clock signal having a predetermined timing corresponding to the signal value of the clock selection signal is generated, and the internal clock signal is generated.
• a clock generation unit that outputs a clock signal to an input signal acquisition unit.
• the clock generation unit includes a plurality of internal clock generation circuits that generate a predetermined internal clock signal according to a clock selection signal.
• the clock timing selection unit includes a selection information setting unit that sets the clock selection information. The clock selection signal is generated based on the clock selection information.
• an internal clock generation circuit is selected by a clock selection signal generated based on a selection information setting section, and an internal clock signal at a predetermined evening is generated. Generated. For this reason, the input signal acquisition unit uses the optimal clock signal for the input signal (address signal, data signal, etc.) according to the frequency of the external clock signal used. It becomes possible to take in.
• FIG. 9 shows the overall configuration of the semiconductor device of the present invention.
• the semiconductor device 100 of this embodiment includes an input / output interface unit 200, a memory control interface unit 300, and a memory cell 400. .
• the input / output interface section 200 is used to control signals such as the external clock signal CLK, chip select signal / CS, write enable signal / WE, etc., and the address signal AD. Receiving the data signal DQ. Note that the data signal D Q is an input / output signal, and signals other than the data signal D Q are input signals.
• the address signal AD and the data signal DQ indicated by thick arrows in the figure are bus signals composed of a plurality of lines.
• the semiconductor device 100 is connected to each circuit of the input / output interface section 200 from outside the semiconductor device 100 via a bonding pad and a bonding pad.
• the input / output interface 200 includes a clock control unit 21, a plurality of input and output amplifiers 23 and 25.
• the clock control unit 21 receives an external clock signal CLK from the outside, and inputs an internal clock signal INCLK indicated by a broken line in the figure to each input buffer 23 and output buffer. This signal is output to the FAM 25 and the memory control interface 300.
• Each input buffer 23 externally inputs a chip select signal / CS, a write enable signal / WE, an address signal AD, and a data signal DQ from outside.
• the internal signals Dout z and Doutx corresponding to each signal are output to the memory control interface unit 300.
• Doutz is the signal in phase with the input signal
• the internal signal Doutx is the signal in phase opposite to the input signal
• the output buffer 25 receives the data signal DQout from the memory control interface section 300 and outputs the data signal DQ to the outside.
• the memory control interface unit 300 includes a mode register 27 for setting an operation mode of the semiconductor device 100 and a plurality of timing devices for performing timing control of the entire semiconductor device 100. It is composed of a control circuit 29. Mode register 27 corresponds to the selection information setting section shown in FIG.
• the mode register 27 outputs the clock selection signal CLK SEL to the clock control section 21 of the input / output interface section 200.
• control signal 31 a row address signal 33, a column address signal 35, and an I / O signal.
• O signal 37 is connected.
• the memory cell array 400 has a plurality of memory cells (not shown) arranged vertically and horizontally.
• these memory cells are: The same memory cell as that of the DRAM is used, and one memory cell is composed of one transistor and one capacitor.
• the semiconductor device 100 of this embodiment is manufactured by using a CMOS (Complementary M0S) process technology.
• CMOS Complementary M0S
• FIG. 10 shows the circuit configuration of the mode register 27 of the memory control interface section 300.
• the mode register 27 includes a control circuit 39 and a plurality of flip-flop circuits 41 (0) to 41 (n).
• the flip-flop circuits 4 1 (0) —4 l (n) correspond to the selection information setting section shown in FIG.
• the control circuit 39 includes an inverter 39a and a two-input NAND gate 39b.
• the input of the inverter 39a receives the light enable signal / WEa, and the output of the inverter 39a is connected to one input of the NAND gate 39b. I have.
• the other input of the NAND gate 39b receives the chip select signal / CSa, and the output of the NAND gate 39b is each flip-flop circuit 4 1 (0) — 4 Connected to l (n) input.
• the chip select signal / CSa and the write enable signal / WEa are signals of the opposite logic to those generated from the chip select signal ZCS and the write enable signal / WE. .
• Each of the flip-flop circuits 4 1 (0) —4 l (n) can hold 1-bit setting information BIT 0—BITn.
• the setting information BIT0 which is the least significant bit of the mode register 27, is used to hold clock selection information.
• Each flip-flop circuit 4 1 (0) —41 ( ⁇ ) receives the output signal of the control circuit 39 and the address signal ADaO—ADan, and the setting information BIT 0—BITn Outputs the information signal INF 0—INF n corresponding to. Note that the information signal INF0 is used as the clock selection signal CLKSEL. I have.
• the clock selection signal CLKSEL is supplied to the clock control unit 21 of the input / output interface unit 200 as described above.
• the address signals ADa0-ADan are signals of the same logic as these signals generated from the address signals AD0-ADn.
• the information is set to the flip-flop circuit 4 1 (0) —4 l (n) when the output of the control circuit 39 is low, that is, when the chip select signal / CSa is set to high level. This is possible when the write enable signal / WEa is set to a low level.
• the level of the address signal ADa0—ADan at this time is set as it is as the setting information BIT0—BITn, and the set setting information BIT0—BITn becomes the information signal INF0— Output as INFn.
• the setting of the output value of the clock selection signal CLKSEL is performed by the system device on which the semiconductor device 100 is mounted. Generally, this setting is performed in the initialization program of the system unit.
• Setting information of mode register 27 The value to be set in BIT0 is set to “0” when the frequency of the external clock signal CLK is higher than a predetermined value, and the value of the external clock signal CLK is set to “0”. When the frequency is lower than the specified value, “1 j is set.
• the clock selection signal CLKSEL goes low when the setting bit BIT0 is set to “0” and goes high when the setting information BIT0 is set to “1”. .
• FIG. 11 shows a clock generation circuit 2la for generating an internal clock signal INCLK formed in the clock control section 21.
• the clock generation circuit 2la corresponds to the clock generation unit shown in FIG.
• the clock generation circuit 2 la includes a first internal clock generation circuit 43 and a second internal clock generation circuit 45 connected in parallel.
• the first internal clock generation circuit 43 is configured by connecting an inverter 43b to the output of a two-input NOR gate 43a.
• the second internal clock generation circuit 45 includes a 2-input NAND gate 45a, an inverter 45b, a delay circuit 45c, and an inverter 45d in series with the output of the NAND gate 45a. It is configured to be connected to.
• the delay circuit 45 c is connected to a resistor 45 e connected in series to the output of the inverter 45 b and a capacitor 45 f connected between the output terminal of the resistor 45 e and the ground VSS. It is composed of:
• the resistor 45e is formed using an n-type diffusion layer
• the capacitor 45f is formed using an NM0S transistor (hereinafter, referred to as NM0S).
• NM0 S connects a gate electrode (hereinafter, referred to as “gate”) to the output terminal of the resistor 45 e, and a source electrode (hereinafter, referred to as “source”) and a drain electrode (hereinafter, referred to as “drain”). ) Is connected to ground VSS to form a capacitance of 45 f.
• the inputs of the NOR gate 43a of the first internal clock generation circuit 43 and the NAND gate 45a of the second internal clock generation circuit 45 are connected to the external clock. It receives the clock signal CLK and the clock selection signal CLK SEL, respectively.
• the output of the first internal clock generation circuit 43 3 b and the second internal clock generation circuit 45 b is the 2-input NAND gate 4. Connected to input 7. The output of the NAND gate 47 is output to each circuit as an internal clock signal INCLK.
• Fig. 12 shows the circuit configuration of the input signal capture circuit 23a included in each input buffer 23 of the input / output interface section 200.
• 23a corresponds to the input signal capturing section shown in FIG.
• the input signal capture circuit 23a includes a control clock creation unit 49, an input signal capture unit 51, and an internal signal output unit 53.
• the control clock generator 49 is composed of two sets of delay circuits 55a and 55b each composed of an inverter and an M0S capacitor, and a two-input NAND gate 57.
• the delay circuits 55a and 55b are connected in series, and the output of the delay circuit 55b is connected to one input of the NAND gate 57.
• the other input of the NAND gate 57 and the input of the delay circuit 55a receive the internal clock signal INCLK.
• the output of the NAND gate 57 outputs an inverted signal / INCLK.
• the input signal acquisition unit 51 is composed of a plurality of PM0S transistors (hereinafter, referred to as PM0S) and an NM0S.
• the input signal acquisition unit 51 receives the internal clock signal INCLK, the inverted signal / INCLK, the input signal Din, and the reference signal Vref, and outputs the acquisition signals D0 and / DO.
• the acquisition signal DO is a signal having the same phase as the input signal Din
• the acquisition signal / DO is a signal having the opposite phase to the input signal Din.
• the input signal acquisition unit 51 has symmetrically arranged comparison circuits 59a and 59b in which one PM0S and three NM0Ss are connected in series. These comparison circuits 59a and 59b compare the magnitudes of the voltage values of the input signal Din and the reference signal Vref, and generate the capture signals D0 and / DO corresponding to the input signal Din. .
• the capture signals D0 and / DO are output from two CMOS amplifiers 61b and 61a, respectively, where the input and output are interconnected.
• These CMOS inverters 61a and 61b are circuits for setting the voltage values of the capture signals D0 and / DO to the power supply voltage VCC or the ground voltage VSS.
• the input signal capturing section 51 has an NM0S 59e for equalizing the nodes 59c and 59d of the comparison circuits 59a and 59b.
• the internal signal output section 53 is connected to two output circuits 63a, 63b composed of PM0S and NM0S, and to the gate of NM0S of each output circuit 63a, 63b to receive the capture signal. Latch the input signals D0 and ZDO 65a and 65b and the internal signals Doutz and Doutx output from the output circuit.
• the input and output are composed of two members 67a and 67a which are connected to each other.
• the clock signal circuit 2 la receives the clock selection information written in the setting information BIT0, which is the least significant bit of the mode register 27, as shown below. It operates, and the input signal capture circuit 23a captures the input signal Din.
• the setting of the output value of the clock selection signal CLKSEL is performed by the system device on which the semiconductor device 100 is mounted.
• the clock selection information “0” is written to the setting information BIT0 of the mode register 27, the clock selection signal CLKSEL becomes low level.
• the NOR gate 43a of the first internal clock generation circuit 43 outputs a signal having a logic opposite to that of the external clock signal CLK.
• the NAND gate 45a of the second internal clock generation circuit 45 outputs a high level regardless of the logical value of the external clock signal CLK.
• the external clock CLK and the inverted logic signal (inverted internal clock signal) output to the NOR gate 43a are connected to the inverter gate 43b and the NAND gate 43a. And is output as the internal clock signal INCLK.
• the first internal clock generation circuit 43 is activated by setting the clock selection signal CLKSEL to low level, and the phase is inverted with respect to the external clock signal CLK.
• the inverted internal clock signal is output as the internal clock signal INCLK.
• the second internal clock generation circuit 45 is inactive.
• the clock selection signal CLKSEL becomes high level.
• the NOR gate 43a of the first internal clock generation circuit 43 outputs a low level regardless of the logical value of the external clock signal CLK.
• the NAND gate 45a of the second internal clock generation circuit 45 outputs a signal having a logic opposite to that of the external clock signal CLK.
• the external clock signal CLK output to the NAND gate 45a and the signal of the reverse logic are output from the inverter 45b, the delay circuit 45c, the inverter 45d, the NAND
• the signal passes through the gate 47 and is output as an internal clock signal INCLK (delayed internal clock signal) delayed by a predetermined time with respect to the external clock signal CLK.
• the second internal clock generation circuit 45 is activated by raising the clock selection signal CLK SEL to a high level, and the delay circuit is almost delayed with respect to the external clock signal CLK.
• the delayed internal clock signal at the timing delayed by the delay time of 45c is output as the internal clock signal INCLK.
• the first internal clock generation circuit 43 is in an inactive state.
• the control clock generator 49 of the input signal capture circuit 23a sets the internal clock signal INCLK rising timing for a predetermined time. Create a delayed inverted signal / INCLK.
• the input signal capturing section 51 operates as follows according to the state of the internal clock signal INCLK and the inverted signal / INCLK.
• the comparison circuits 59a and 59b are activated.
• a current corresponding to the voltage of the input signal D in and the reference signal Vref flows through the comparison circuit 59 as 59 b, and the voltage values of the capture signal / D0 and DO change ( That is, when the internal clock signal INCLK goes high, the capture of the input signal Din starts.
• the CMOS inverters 61a and 61b are activated and the capture signals D0 and / DO Is amplified.
• the internal signal output section 53 drives the output circuits 63a and 63b according to the voltage values of the capture signals D0 and / DO. Then, the internal signals Doutz and Doutx corresponding to the input signal Din are output.
• FIG. 14 shows the capture of the input signal Din when the clock selection signal CLKSEL is at a low level (when the frequency of the external clock signal CLK is high).
• the internal clock signal INCLK is an inverted internal clock signal obtained by inverting the external clock signal CLK.
• the input period of the input signal Din is defined by the setup time tDSl and the hold time tDHl with respect to the rise of the internal clock signal INCLK, as in FIG. 4 described above.
• Fig. 15 shows the capture of the input signal Din when the clock selection signal CLKSEL is at a high level (when the frequency of the external clock signal CLK is low).
• the internal clock signal INCLK is a delayed internal clock signal obtained by delaying the external clock signal CLK by the delay time Delay.
• the input signal Din is the rising edge of the internal clock signal INCLK.
• the internal signal Doutz and Doutx corresponding to the input signal Din are taken out and the input signal Din is input during the input period of the internal clock signal INCLK, as in FIG. Specified by the setup time tDS2 and hold time tDH2.
• the start times of the tDS1 and tDS2 are set later than the rise of the external clock signal CLK.
• the input period of the input signal Din is defined only by the hold time tDH with respect to the rise of the external clock signal CLK.
• the clock generation circuit 21a inverts the external clock signal CLK when the external clock signal CLK is higher than a predetermined frequency.
• the internal clock signal INCLK inverted internal clock signal
• the clock generation circuit 21a generates an internal clock delayed from the external clock signal CLK by a delay time Delay.
• Clock signal INCLK delayed internal clock signal
• the input signal Din when the frequency of the external clock signal CLK is low, the input signal Din can be acquired with a delayed internal clock signal independent of the cycle of the external clock signal CLK. Therefore, the input signal capture circuit 23a can capture the input signal Din at the optimum and fastest timing according to the frequency of the external clock signal CLK. As a result, even when the frequency of the external clock signal CLK is low, the access time is not unnecessarily delayed, and when the frequency of the external clock signal CLK is high, The input signal Din can be reliably captured, and the setup time tDSl and tDS2 of the input signal Din with respect to the rise of the internal clock signal INCLK is determined by the rise of the external clock signal CLK. Set more slowly than ascending. Therefore, even if the input signal Din is input at the same time as the rising of the external clock signal CLK, the input signal Din can be reliably captured.
• the design of the system device mounting the semiconductor device can be easily designed, and the circuit for outputting the input signal of the system device can be simplified. That is, a semiconductor device that is easy for the user to use can be configured.
• the clock select information can be set during the operation of the semiconductor device. it can. As a result, the user can set the clock selection information by writing the data into the register 27 from the system device side.
• the semiconductor device does not need to set the clock selection signal CLK SEL in advance, it is possible to provide the user with a semiconductor device that can operate in a wide range of frequencies.
• FIG. 16 shows one mode of the selection information setting section shown in FIG. 8 in the semiconductor device of the present invention.
• the configuration other than the selection information setting unit is the same as that of the first embodiment.
• the input of the inverter 71 which outputs the clock selection signal CLK SEL, is connected to one end of a fuse 73 made of polysilicon, etc., and a resistor 7 formed using an n-type diffusion layer. 5 is connected to one end.
• the other end of the fuse 73 and the other end of the resistor 75 are connected to the power supply VCC and the ground VSS, respectively.
• the resistor 75 has a high resistance value in order to minimize the power supply current when the fuse 73 is not blown.
• the highest operating frequency is evaluated in a probe test in a semiconductor manufacturing process, and it is determined whether the built-in fuse 73 is blown or not blown.
• the fuse 73 is not blown when the maximum operating frequency is equal to or higher than the predetermined value.
• the high level is The clock select signal CLKSEL supplied to the input goes low. Therefore, the internal clock signal INCLK becomes an inverted signal of the external clock signal CLK.
• the fuse 73 is blown when the maximum operating frequency is lower than a predetermined value. At this time, a low level is supplied to the input of the inverter 71, and the clock selection signal CLKSEL becomes a high level. Therefore, the internal clock signal INCLK is a signal delayed by a predetermined time with respect to the external clock signal CLK.
• the internal clock is The specifications change the timing of signal INCLK. Therefore, the timing of the internal clock signal INCLK can be set according to the maximum operating frequency of the semiconductor device evaluated by a probe test or the like.
• FIG. 17 shows an embodiment of the selection information setting section shown in FIG. 8 in the present invention.
• the configuration other than the selection information setting unit is the same as that of the first embodiment.
• the input of the amplifier 77 that outputs the clock selection signal CLKSEL is connected to the bonding pad 79.
• the bonding pad 81 connected to the power supply VCC and the bonding pad 83 connected to the ground VSS are located close to the bonding pad 79. ing.
• the highest operating frequency of the semiconductor device is evaluated in a probe test in the semiconductor manufacturing process, and in the assembly process, the bonding pad 79 is replaced with the bonding pad 81 or the bonding pad 81. 8 Connected to 3.
• the bonding pad 79 and the bonding pad 81 are connected by the bonding wire 85. At this time, the clock selection signal CLK SEL is made low.
• the bonding pad 79 and the bonding node 83 are connected by the bonding wire 85. At this time, the clock selection signal CLK SEL is set to a high level.
• FIG. 18 shows an embodiment of the selection information setting section shown in FIG. 8 in the semiconductor device of the present invention.
• the configuration other than the selection information setting unit is the same as that of the first embodiment.
• the input of the inverter 87 which outputs the clock selection signal CLK SEL is connected to the power supply VCC or the ground V SS via the wiring patterns 89 a and 89 b which are conductive films.
• the input of the connector 87 is connected to the power supply VCC or the ground VSS depending on the pattern of the photomask used in the wiring process.
• the wiring step two photomasks having different pattern shapes are prepared.
• the wiring process is performed using one of these photomasks, and the input of the inverter 87 is connected to the power supply VCC via the wiring pattern 89a or the wiring pattern 89b. Or connected to ground VSS.
• a photoresist pattern corresponding to the pattern shape of a photomask is formed on a semiconductor device in the photolithography process.
• a conductive film formed in advance by sputtering or the like is selectively etched by a photoresist register to form a wiring pattern 89a or a wiring pattern 89b. Is formed.
• the wiring patterns 89a and 89b can be composed of wiring of about several tens of zm from the input of the inverter 87 to the power supply VCC or the ground VSS. b does not increase the chip area of the semiconductor device.
• the same effects as those of the above-described second embodiment can be obtained.
• the input of the inverter 87 was connected to the power supply VCC or the ground VSS using the photomask used in the wiring process, so that the operating frequency of the semiconductor device for each operating frequency was previously determined.
• the photomask in the wiring process can be switched according to the production instruction quantity.
• the selection information can be set without increasing the chip area of the semiconductor device. A part can be formed.
• the level of the clock select signal CLKSEL can be changed only by performing the photolithographic process and etching process, which are normal semiconductor manufacturing processes.
• the clock selection signal CLKSEL can be selected without any special process.
• FIG. 19 shows one embodiment of the frequency detection circuit in the semiconductor device of the present invention.
• the configuration other than the frequency detection circuit (clock timing selection unit) is the same as that of the first embodiment.
• the frequency detection circuit 90 includes a 1/2 frequency divider 91 that halves the frequency of the external clock signal CLK, a delay circuit dl that generates a positive pulse signal on the falling side of the input signal, A latch 93 composed of delay circuits d 2 and d 3 having a predetermined time constant, an RS flip-flop circuit, and a data transfer unit 95 that outputs a clock selection signal CLKSEL is supplied to It is composed of:
• the inputs and outputs of the 1/2 divider 91 are each connected to the external clock signal CLK and the node N1.
• the delay circuit dl is composed of a plurality of delay stages in which a two-input NAND and an amplifier are connected in series.
• One input of the NAND in the first delay stage is connected to the power supply VCC.
• the output of each delay stage is connected to one input of the NAND in the connected delay stage.
• the other input of the NAND of each delay stage is connected to node N1.
• the output of delay circuit dl is connected to node N4.
• the input and output of delay circuit d2 are connected to nodes N1 and N2, respectively.
• the input and output of the delay circuit d 3 are connected to the nodes N2 and N3, respectively.
• the latch section 93 is composed of two 2-input NANDs.
• the reset terminal / R of the latch 93 is connected to the node N3, and the set terminal / S is connected to the inverted signal of the node N4.
• Output Q of latch 93 is connected to node N5.
• the data transfer unit 95 is composed of M0S switches 95a and 95b in which the source and drain of PM0S and NM0S are connected to each other, and two impellers in which inputs and outputs are connected to each other. It consists of an evening train 95e that controls the evening trains 95c and 95d, and the M0S switches 95a and 95b.
• the impulse train 95 d is connected in series.
• the node N6 is a node connecting the inverter row 95c and the M0S switch 95b ⁇
• the input side of the M0S switch 95a is connected to the node N5, and the output of the inverter row 95d is connected to the clock selection signal CLKSEL.
• the NM0S gate of the M0S switch 95a and the PM0S gate of the M0S switch 95b are connected to the node N2.
• the PM0S gate of the M0S switch 95a and the NM0S gate of the M0S switch 95a are connected to the inverted signal of the node N2.
• the delay circuit d l is a circuit that adjusts the set timing of the latch section 93.
• the delay circuit d2 is a circuit that adjusts the timing of capturing the transfer data of the data transfer unit 95.
• FIG. 20 and FIG. 21 show the operation timing of the frequency detection circuit 90 described above.
• the frequency detection circuit operates as shown in FIG.
• the 1/2 frequency divider 91 outputs a signal having a frequency that is half the frequency of the external clock signal CLK to the node N1.
• the latch section 93 sets the node N5 to a high level in response to the pulse of the node N4.
• the high level state of the node N5 is maintained until the node N3 goes low and the latch 93 is reset.
• Node N6 goes low in response to the high level of node N5. And the node The low state of N6 is latched on the falling edge of node N2
• the inverse row 95d outputs an inverted signal of the node N6, and the clock selection signal CLK SEL changes from a low level to a high level.
• the clock selection signal CLK SEL becomes highly resilient when the period t CLK of the external clock signal CLK is longer than the delay time of the delay circuit d1.
• the frequency detection circuit operates as shown in FIG.
• the level of the clock selection signal CLKSEL automatically changes according to the frequency of the external clock signal CLK. Then, the internal clock INCLK with the optimal timing is selected by the clock selection signal CLK SEL.
• the external clock signal is supplied to the clock timing selection unit.
• a frequency detection circuit 90 that detects the frequency of CLK is provided, and a clock selection signal CLK SEL is output according to the detected frequency.Therefore, automatically, according to the frequency of the external clock signal CLK.
• the optimal internal clock signal IN CLK can be selected.
• clock selection information is set in the semiconductor manufacturing process. This eliminates the need for setting the clock selection information on the system device on which the semiconductor device is mounted.
• the internal clock signal INCLK can be automatically selected according to the operating frequency, so that it is not necessary to limit the operating frequency in the semiconductor manufacturing process in advance, and the It is possible to provide users with semiconductor devices having a wide range of frequencies.
• the first to fifth embodiments described above have dealt with the cases where the present invention is applied to a clock synchronous type memory LSI.
• the present invention is not limited to such an embodiment.
• the present invention may be applied to microcomputer evening or system LSI.
• the present invention is effective when applied to a semiconductor device having an internal circuit that is not synchronized with the external clock signal CLK.
• the input timing of the input signal D in is specified only by the hold time tDH with respect to the rising edge of the external clock signal CLK.
• the present invention is not limited to such an embodiment.
• a setup time tDS for the rising edge of the external clock signal CLK may be further defined.
• the system device on which the semiconductor device is mounted only needs to generate the input signal D in almost simultaneously with the rise of the external clock signal CLK. Designing becomes easier.
• the clock generation circuit 21a is provided with the first internal clock generation circuit 43 and the second internal clock generation circuit 45.
• the examples provided are described.
• the present invention is not limited to such an embodiment.
• three or more internal clock generation circuits are provided, and an internal clock signal INCLI (is generated by multiple clock selection information and multiple clock selection signals. In this case, it is possible to capture the input signal D in at a more detailed timing.
• INCLI internal clock signal
• the example in which the resistor 45 e is formed using the n-type diffusion layer has been described.
• the present invention is not limited to such an embodiment.
• a P-type diffusion layer may be used, or a wiring such as polysilicon may be used.
• the bonding pad 79 and the bonding pad 81 or the bonding pad 83 are connected has been described.
• the present invention is not limited to such an embodiment.
• the bonding pad 79 may be directly connected to the lead frame with a bonding wire.
• an input signal can be captured with a clock signal having an optimum timing according to the frequency of an external clock signal to be used. That is, the input signal can be reliably taken in irrespective of the frequency of the external clock signal.
• the clock generation unit can easily select or activate a predetermined internal clock generation circuit based on the signal value of the clock selection signal, and can easily set the internal clock at a predetermined timing.
• a lock signal can be generated.
• the input signal when the frequency of the external clock signal is high, the input signal is captured by an inverted internal clock signal that depends on the cycle of the external clock signal, and the external clock is input.
• the frequency of the clock signal is low, input with a delayed internal clock signal independent of the cycle of the external clock signal.
• the semiconductor device of the present invention by setting the clock selection information in the selection information setting section, it is possible to set the clock selection information before operating the semiconductor device.
• the selection information setting section is configured by the register, so that the clock selection information can be set according to the frequency of the external clock signal used during operation of the semiconductor device. Can be set.
• the selection information setting section is constituted by the fuse, so that the clock selection information can be set by blowing and unfusing the fuse. Therefore, for example, optimal clock selection information can be set according to the maximum operating frequency evaluated in the probe test.
• the selection information setting section is constituted by the bonding pad and the bonding wire, so that the setting of the clock selection information can be performed by the connection destination of the bonding wire connected to the bonding pad. You can do this by changing it. For example, optimal clock selection information can be set according to the highest operating frequency evaluated in the probe test.
• the selection information setting section is formed of a conductive film formed at a predetermined position on the semiconductor substrate corresponding to the pattern shape of the photomask, so that the clock selection information is set.
• Clock selection information can be set during the photolithography process and etching process, which are normal semiconductor manufacturing processes, and the clock can be set without any special process. Selection information can be set.
• the clock timing selection unit includes a frequency detection circuit that detects the frequency of the external clock signal, so that the frequency can be adjusted according to the frequency of the external clock signal. Automatically selects internal clock signal You can choose. As a result, it is not necessary to set clock selection information in the semiconductor manufacturing process, or it is necessary to set clock selection information on a system device having a semiconductor device. No longer needed. Therefore, the input signal can be reliably taken in irrespective of the frequency of the external clock signal.

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• 1998
  • 1998-10-13 JP JP29081198A patent/JP4034886B2/ja not_active Expired - Fee Related
• 1999
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