WO2000014873A2 - Schaltungsanordnung und verfahren zur takterzeugung - Google Patents
Schaltungsanordnung und verfahren zur takterzeugung Download PDFInfo
- Publication number
- WO2000014873A2 WO2000014873A2 PCT/DE1999/002734 DE9902734W WO0014873A2 WO 2000014873 A2 WO2000014873 A2 WO 2000014873A2 DE 9902734 W DE9902734 W DE 9902734W WO 0014873 A2 WO0014873 A2 WO 0014873A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- oscillator
- mixer
- unit
- vcol
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 5
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 claims description 6
- 101100082028 Arabidopsis thaliana PLL2 gene Proteins 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 13
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 12
- 230000003287 optical effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000010363 phase shift Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
Definitions
- clock signals are formed from transmitted data for further data processing.
- Multiplexers which are controlled by a clock generator with clock signals, are formed.
- the clock frequency of the data signal present at the output of the multiplexer is higher by a factor of n than the clock frequency of each data signal present at the input of the multiplexer.
- the factor n can move from a technologically easily manageable to a higher clock frequency of the data signals at the outputs of the multiplexer.
- demultiplexers are used to generate n data streams with a low data transmission rate from a data stream with a high data transmission rate.
- the clock signals with the corresponding clock frequency are derived from the transmitted data signals.
- IEEE JOURNAL OF SOLID STATE CIRCUITS Vol SC-27, pp. 1752 - 1762, December 1992 is a 6 GHz Integrated Phase-Locked Loop using AlGaAs / GaAs heterojunction bipolar transistors shown.
- Phase synchronization within a circuit arrangement for clock signal generation requires a clock frequency of at least 40 GHz.
- the invention is based, another object
- the invention has the advantage that a clock frequency is achieved in the clock signal generation, which is approximately half the cut-off frequency used in the circuit arrangement active switching elements.
- the invention has the advantage that no LC filters have to be used, which makes it possible to integrate the circuit for clock generation on a semiconductor chip.
- FIG. 1 shows a transmitting and receiving unit which are connected by an optical transmission path
- FIG. 2 shows an assignment of data signals transmitted in data streams to clock signals
- Figure 3 is a schematic diagram of a known
- Output signals 5 'or the timing signal generating unit, a two-stage Ringoszillat figure, Figure 6 associated pulse diagrams, Figure 7 is a schematic diagram of a further
- FIG. 1 shows the transmission unit S mentioned above and the reception unit E, which are connected by the optical transmission link UE.
- a first multiplexer MUX1 for combining the incoming first and second data signals DU, DI2 into a fifth data signal DI5 and a second multiplexer MUX2 for combining the incoming third and fourth data signals DI3, DI4 into a sixth data signal DI6 are arranged in the transmission unit S.
- the fifth and sixth data signals DI5, DI6 are fed to a third multiplexer MUX3.
- the data signals DI that can be tapped at the output of the third multiplexer MUX3 are forwarded to an electro-optical converter EOW.
- the V genaration the first, second and third multiplexers MUX1, MUX2 and MUX3 having first, second and third clock signals CLKI1, CLKI2 and CLKI3 accepts a
- Clock signal generation unit CLKIGEN The first and second clock signals CLKI1, CLKI2 for the first and second
- Multiplexers MUX1 and MUX2 have a first clock frequency.
- the third clock signal CLKI3 for the third multiplexer MUX3 has a second clock frequency.
- an optoelectric converter OEW receiving the transmitted optical data signals
- a third demultiplexer DEMUX3 and a second and first de ultiplexer DEMUX2, DEMUX1.
- the second and third demultiplexer DEMUX1, DEMUX2 is arranged after the third demultiplexer DEMUX3.
- a preamplification of the optical signal that becomes necessary can be done with an erbium doped fiber amplifier EDFA.
- the data signals DO are divided by the third demultiplexer DEMUX3 into fifth and sixth data signals D05, D06.
- the fifth and sixth data signals D05 and D06 are further divided by the first and second demultiplexer DEMUX1, DEMUX2.
- the first and second data signals DO1 and D02 are present at the outputs of the first demultiplexer DEMUXl.
- the third and fourth data signals D03 and D04 are present at the outputs of the second demultiplexer DEMUX2.
- the first, second and third demultiplexers DEMUX1, DEMUX2 and DEMUX3 are replaced by first, second and third clock signals with different
- the first, second and third clock signals CLKOl, CLK02 and CLK03 are from one Clock generation unit CLKOREGEN issued.
- the first and the second clock signals CLKOL and CLK02 have a first clock frequency.
- the third clock signal CLK03 has a second clock frequency.
- the data signals DO emitted by the optoelectric converter OEW are present as an input signal at the clock generation unit CLKOREGEN.
- FIG. 2 shows the phase positions of the data edges and the clock edges of the data and clock signals present at the inputs or the output of the first multiplexer MUX1 in the transmission unit S.
- the incoming data signals DU and DI2 are shifted by 180 ° to one another in order to ensure an optimal takeover of the data signals DU and DI2 at the output of the first multiplexer MUX1.
- the first phase of the clock signal CLKI1 With the high phase of the clock signal CLKI1, the first
- the data rate of the fifth data signal DI5 present at the output of the first multiplexer MUX1 is twice as high as the data rate of the data rate of the first or second data signal DU, DI2 present at the inputs of the first multiplexer MUXl.
- the clock frequency of the clock signal CLKI1 corresponds to the data rate at the input of the first
- Multiplexer MUXl applied first and second data signal or half the data rate of the output signal of the first multiplexer MUXl.
- the phase of the clock edge of the second clock signal CLKI2 is shifted by 90 ° with respect to the phase of the clock edge of the first clock signal CLKI1.
- the third multiplexer MUX3 requires twice the clock frequency of the first or second clock signal.
- the clock frequency of the clock signal CLKI3 present at the third multiplexer corresponds to the maximum data rate that at the data output of the first and second Multiplexers MUX1, MUX2 present fifth and sixth data signals DI5, DI6.
- FIG. 3 shows a first tracking psychronization unit PLL1, which is subsequently referred to as
- This clock signal generating unit CLKIGEN is called.
- This clock signal generating unit CLKIGEN is formed with a first and second mixer M1, M2, a low-pass filter TP, a proportional integral controller PI and a voltage-controlled oscillator VCO.
- the clock signal generation unit CLKIGEN is synchronized by a clock signal CLKI.
- the clock frequency of the clock signal CLKI corresponds to the first, second, third and fourth data signals DU, DI2, DI3, DI4 present at the inputs of the first and second multiplexers MUX1, MUX2.
- the voltage-controlled oscillator VCO is essentially formed from a ring oscillator, as shown in FIG. 5 and described in the associated description.
- the first and second mixers M1 and M2 are Gilbert multipliers or diode mixers. If a first and second frequency of a first and second signal U1, U2 are present at the inputs of a first or second mixer M1, M2, then first mixer M1 generates a sum signal and a difference signal.
- the ring oscillator oscillates at the clock frequency of the data signals DU ... 4 present at its inputs.
- the first and second signals Ul (U1N), U2 (U2N) present at the outputs of the voltage-controlled oscillator VCO are shifted by 90 ° to one another.
- the first and second signals Ul (U1N) and U2 (U2N) at the input of the first mixer Ml result in the first at the output of the first mixer Ml
- the low-frequency component of the second mixed signal M2 is filtered out with the low-pass filter TP, fed to the proportional integral controller PI and a control voltage Ustl is formed.
- the phase of the voltage-controlled oscillator VCO is readjusted with the control voltage Ustl.
- Figure 5 shows a two-stage ring oscillator.
- This two-stage ring oscillator consists of a first and a second limiting amplifier, which is advantageous as a
- Schmitt trigger OZ1, OZ2 is configured.
- the first and second Schmitt triggers OZ1, OZ2 are controlled via the control input S, to which the first control voltage Ustl is applied.
- a first and second output OZ1 is connected to a first and second input of the second Schmitt trigger.
- the applied signal is inverted at the second output of the first Schmitt trigger OZ1 and at the second input of the second Schmitt trigger OZ2.
- the second output of the first Schmitt trigger OZ1 is connected to the first input of the second Schmitt trigger OZ2.
- a first output of the second Schmitt trigger OZ2 is connected to a second input of the first Schmitt trigger OZ1.
- the second output of the second Schmitt trigger is connected to the first input of the first cutting trigger OZ1.
- the input signal at the second input of the first Schmitt trigger OZ1 is inverted.
- a first and second output signal Ul (U1N) and at the output of the second S chmitt trigger OZ2 a first and second output signal U2 (U2N) tapped.
- the control inputs of the first and second S chmitt trigger OZ1, OZ2 of the two-stage ring oscillator are used to set the delay time which regulates the frequency of the output signal U2 of the ring oscillator.
- the structure of the Schmitt trigger depends on the technology.
- Ring oscillators have the advantage that they can only be formed from semiconductors and resistors.
- the delay time can be set in a wide range by changing the load. Both a resistive and a capacitive load such as e.g. Junction capacities are used.
- FIG. 6 shows the first and second signals U1 (U1N), U2 (U2N) which are emitted by the two-stage ring oscillator.
- the threshold marked with o gives an upper one
- the threshold labeled u indicates the lower bet level of the respective cut trigger.
- the delay time tv indicates the time from exceeding or falling below the application level to the beginning of the signal drop.
- the rise or fall time tsf of the signal indicates the time until the cut trigger level is reached.
- the first and second signals U1, U2 are shifted from one another by 90 °.
- the clock frequency is the reciprocal of four times the sum of the delay time tv and the rise and fall time tsf.
- the delay time tv or the rise or fall time tsf is controlled via the control signal Ust and the clock frequency of the output signal of the two-stage ring oscillator is thus determined.
- phase shift depends on the dielectric constant of the substrate.
- An integrated structure with mutliplexers, a voltage-controlled oscillator VCO and mixers is advantageous due to the small phase shift.
- FIG. 7 shows a basic circuit diagram of a clock signal generation unit.
- Data signals with a data frequency of 40 Gbit / s are applied to the input of the clock signal generation unit.
- the clock frequency of the data signals is achieved by the synchronization of a command signal DF with a comparison signal X.
- the comparison signal X is formed from first and second tracking synchronization units PLL1, PLL2.
- the first tracking synchronization unit PLL1 has a first voltage-controlled oscillator VCOl, a first and fourth mixer Ml, M4, a first low-pass filter TP1 and a first proportional-integral controller PI1.
- the second tracking synchronization unit PLL2 has a second voltage-controlled oscillator VC02, a second and third mixer M2, M3, a second low-pass filter TP2 and a second proportional-integral controller PI2.
- the second voltage controlled oscillator VC02 generates the same
- a first output signal I of the first mixer M1 and a second output signal Q of the second mixer M2 are fed to the third mixer M3.
- the comparison signal X of the third mixer M3 is fed to the fourth mixer M4 and the second low-pass filter TP2.
- the input of the fourth mixer M4 is connected to the output of a fifth mixer M5.
- This fifth mixer M5 is acted upon on the input side by the data signals DO given by the optoelectric unit O E W a b .
- the data signal DO is fed via a delay unit V to a second input of the fifth mixer M5.
- the fifth mixer M5 and the delay unit V form a unit B for forming a guide signal DF.
- the two output signals U1 and U2 of the first voltage-controlled oscillator VCOl which are shifted by 90 ° to one another, are fed to the first mixer Ml.
- the first mixer delivers a first output signal I.
- the first and second signals U1 and U2 of the second voltage-controlled oscillator VC02 which are shifted by 90 ° to one another, are fed to the second mixer M2.
- the output signals Ul and U2 have a clock frequency of 10 GHz.
- the output signal Ul is the clock signal CLKOl and the output signal U2 is the clock signal CLK02 (see Fig.l).
- the clock frequency is 10 GHz in each case.
- the second mixer M2 supplies the second output signal Q.
- the two first and second output signals I, Q shifted by 90 ° with respect to one another are fed to a third mixer M3.
- the third mixer M3 supplies the comparison signal X.
- the first output signal I serves as the third clock signal CLK03 and has a clock frequency of 20 GHz.
- the second output signal Q also has a clock frequency of 20 GHz.
- the comparison signal X has twice the clock frequency of the first or second output signal I, Q.
- a DC voltage also arises depending on the relative phase position between the first and second output signals I, Q, which regulates the phase of the output signals of the second voltage-controlled oscillator VC02 via the second low-pass filter TP2 and the second proportional-integral controller PI2 so that A phase difference of 90 ° arises between the edges of the first output signal I and the second output signal Q.
- the comparison signal X contains no DC component.
- the comparison signal X has twice the clock frequency of the first or second output signal I, Q. This clock frequency is the highest frequency to be processed in the circuit arrangement for clock signal generation and is decisive for the maximum bit rate of the guide signal DF. With this comparison signal X, a constant phase relationship to the command signal DF can be established.
- the high-frequency comparison signal X of the third mixer M3 is fed to the fourth mixer M4.
- the comparison signal X is multiplied in an analog manner in the fourth mixer M4 by the guide signal DF formed from the data signal DO.
- the low-frequency component of the fourth output signal R of the fourth mixer M4 is filtered out in the first low-pass filter TP1 and fed to the proportional integral controller PI1.
- the output signal Ustl of the proportional integral controller PH With the output signal Ustl of the proportional integral controller PH, the phase between the output signals Ul and U2 of the first voltage-controlled oscillator VCOl is readjusted.
- the guide signal DF formed from the data signals DO is in principle obtained by an EXOR link between the data signal DO and the delayed data signal DO.
- the EXOR link is achieved by the fifth mixer M5.
- Each edge change of the data signal DO generates a data pulse with a defined duration.
- the duration of the data pulse is determined by the delay unit V.
- the duration of the data pulses of the guide signal DF should be half the duration of the data signal DO.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Control Of Multiple Motors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU10298/00A AU762120B2 (en) | 1998-09-08 | 1999-09-01 | Circuit and method for generating clock pulses |
EP99953649A EP1112620A2 (de) | 1998-09-08 | 1999-09-01 | Schaltungsanordnung und verfahren zur takterzeugung |
BR9913531-0A BR9913531A (pt) | 1998-09-08 | 1999-09-01 | Dispositivo de ligação e processo para a produção de tempo |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19841008 | 1998-09-08 | ||
DE19841008.5 | 1998-09-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000014873A2 true WO2000014873A2 (de) | 2000-03-16 |
WO2000014873A3 WO2000014873A3 (de) | 2000-06-02 |
Family
ID=7880236
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/002734 WO2000014873A2 (de) | 1998-09-08 | 1999-09-01 | Schaltungsanordnung und verfahren zur takterzeugung |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1112620A2 (de) |
AU (1) | AU762120B2 (de) |
BR (1) | BR9913531A (de) |
WO (1) | WO2000014873A2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2363268A (en) * | 2000-06-08 | 2001-12-12 | Mitel Corp | Timing circuit with dual phase locked loops |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4186356A (en) * | 1977-04-20 | 1980-01-29 | Adret Electronique | Phase locked loop frequency synthesizer and frequency modulator |
DE3837246A1 (de) * | 1988-10-28 | 1990-05-03 | Siemens Ag | Frequenzgenerator |
US5128940A (en) * | 1989-09-11 | 1992-07-07 | Kabushiki Kaisha Toshiba | Demultiplexer |
EP0549881A1 (de) * | 1991-11-29 | 1993-07-07 | Alcatel SEL Aktiengesellschaft | Frequenzsynthetisierer |
US5734283A (en) * | 1992-07-01 | 1998-03-31 | Telelfonaktebolaget Lm Ericsson | Demultiplexor circuit |
-
1999
- 1999-09-01 WO PCT/DE1999/002734 patent/WO2000014873A2/de not_active Application Discontinuation
- 1999-09-01 EP EP99953649A patent/EP1112620A2/de not_active Ceased
- 1999-09-01 AU AU10298/00A patent/AU762120B2/en not_active Ceased
- 1999-09-01 BR BR9913531-0A patent/BR9913531A/pt not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4186356A (en) * | 1977-04-20 | 1980-01-29 | Adret Electronique | Phase locked loop frequency synthesizer and frequency modulator |
DE3837246A1 (de) * | 1988-10-28 | 1990-05-03 | Siemens Ag | Frequenzgenerator |
US5128940A (en) * | 1989-09-11 | 1992-07-07 | Kabushiki Kaisha Toshiba | Demultiplexer |
EP0549881A1 (de) * | 1991-11-29 | 1993-07-07 | Alcatel SEL Aktiengesellschaft | Frequenzsynthetisierer |
US5734283A (en) * | 1992-07-01 | 1998-03-31 | Telelfonaktebolaget Lm Ericsson | Demultiplexor circuit |
Non-Patent Citations (1)
Title |
---|
AUSTIN J ET AL: "DOPPLER CORRECTION OF THE TELECOMMUNICATIONS PAYLOAD OSCILLATORS INTHE UK T-SAT" PROCEEDINGS OF THE EUROPEAN MICROWAVE CONFERENCE,GB,TUNBRIDGE WELLS, MICROWAVE EXHIBITIONS, Bd. CONF. 18, 1988, Seiten 851-857, XP000094117 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2363268A (en) * | 2000-06-08 | 2001-12-12 | Mitel Corp | Timing circuit with dual phase locked loops |
GB2363268B (en) * | 2000-06-08 | 2004-04-14 | Mitel Corp | Timing circuit with dual phase locked loops |
US7006590B2 (en) | 2000-06-08 | 2006-02-28 | Zarlink Semiconductor Inc. | Timing circuit with dual phase locked loops |
Also Published As
Publication number | Publication date |
---|---|
WO2000014873A3 (de) | 2000-06-02 |
EP1112620A2 (de) | 2001-07-04 |
AU762120B2 (en) | 2003-06-19 |
BR9913531A (pt) | 2001-06-05 |
AU1029800A (en) | 2000-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60029826T2 (de) | Mehrratentransportsystem sowie chipsatz | |
DE68921700T2 (de) | Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten. | |
DE69714881T2 (de) | Integrierter Hochfrequenzverstärker | |
DE2317960C2 (de) | Synchrondetektor für Farbsynchronsignale | |
DE2361928A1 (de) | Anordnung fuer einen starr phasengeregelten mikrowellensender, insbesondere fuer richtfunkgeraete | |
DE2739035C3 (de) | Frequenzsteuerbarer Oszillator mit einer Schaltungsanordnung zur Vervielfachung der Frequenz | |
DE602006000532T2 (de) | Pulsgenerator | |
DE3913025C2 (de) | ||
DE3005764C2 (de) | Regelbarer Oszillator | |
DE2159653A1 (de) | Einrichtung zur automatischen Phasenregelung von Oszillatorfrequenzen | |
DE102020001985A1 (de) | Ac/dc-schaltnetzteil mit 10 mhz-zeitbasis | |
EP0073400B1 (de) | Regenerator für digitale Signale mit quantisierter Rückkopplung | |
DE2802981A1 (de) | Mit phasensynchronisierter schleife arbeitende abstimmeinrichtung | |
WO2000014873A2 (de) | Schaltungsanordnung und verfahren zur takterzeugung | |
DE3125825A1 (de) | Demodulatorschaltung fuer fm-signale (frequenzmodulierte signale) | |
DE3022287C2 (de) | Schaltung zur Kompensation von Frequenzschwankungen in FM-Systemen | |
DE2323101C3 (de) | Monolithisch integrierter Schaltkreis zur Erzeugung einer Rechteckschwingung für die horizontale Ablenkung bei Fernsehempfängern | |
DE10061167A1 (de) | Verfahren und Anordnung zur Erzeugung eines Taktes in einem Datenverarbeitungssystem mit einer Vielzahl von Datenkanälen | |
DE19739645C2 (de) | Vorrichtung zur Gewinnung eines Takt- oder Trägersignales | |
EP0392056B1 (de) | Taktsignalschaltung | |
EP0626761B1 (de) | Anordnung zur Synchronisation zweier getaktet arbeitender Geräte | |
DE102020203841A1 (de) | Elektrische schaltung, pulsradargerät, verfahren zum bereitstellen eines ausgangssignals und radarverfahren | |
DE102023200451A1 (de) | Schaltung mit einer stromspiegelschaltung und verfahren zum betreiben einer schaltung | |
EP0109963B1 (de) | Einrichtung zur Bildträgeraufbereitung von Fernsehsignalen | |
WO2023232625A1 (de) | Taktsignalgenerator zur erzeugung eines referenzsignals und eines taktsignals, system mit einem solchen und verfahren zum synchronisieren mehrerer teilnehmer eines systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref country code: AU Ref document number: 2000 10298 Kind code of ref document: A Format of ref document f/p: F |
|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AU BR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AU BR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1999953649 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10298/00 Country of ref document: AU |
|
WWP | Wipo information: published in national office |
Ref document number: 1999953649 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 10298/00 Country of ref document: AU |
|
WWR | Wipo information: refused in national office |
Ref document number: 1999953649 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1999953649 Country of ref document: EP |