WO1999054939A1 - TRANSISTOR BIPOLAIRE VERTICAL, EN PARTICULIER A BASE A HETEROJONCTION SiGe, ET PROCEDE DE FABRICATION - Google Patents
TRANSISTOR BIPOLAIRE VERTICAL, EN PARTICULIER A BASE A HETEROJONCTION SiGe, ET PROCEDE DE FABRICATION Download PDFInfo
- Publication number
- WO1999054939A1 WO1999054939A1 PCT/FR1999/000867 FR9900867W WO9954939A1 WO 1999054939 A1 WO1999054939 A1 WO 1999054939A1 FR 9900867 W FR9900867 W FR 9900867W WO 9954939 A1 WO9954939 A1 WO 9954939A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- collector
- intrinsic
- extrinsic
- base
- Prior art date
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000000284 resting effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
Definitions
- the invention relates to vertical bipolar transistors, and more particularly to high speed bipolar transistors having a SiGe heterojunction base (Silicon-Germanium).
- An object of the invention is to produce a high speed bipolar transistor of low complexity, compact, having a reduced collector-substrate capacity and a reduced capacity between the extrinsic base and the collector.
- the bipolar transistor according to the invention consequently comprises a semiconductor region of intrinsic collector surrounded by a region of lateral isolation, a semiconductor layer, comprising for example a heterojunction SiGe, located partially between the emitter and the intrinsic collector and s' extending on either side of the transmitter above the lateral isolation region.
- the bipolar transistor according to the invention also comprises an intrinsic base region formed in said semiconductor layer between the emitter and the intrinsic collector. It also comprises an extrinsic base region and an extrinsic collector region respectively comprising first zones formed in said semiconductor layer. These first zones are situated respectively on either side of the transmitter and above a first part of the lateral isolation region and are mutually electrically isolated by a second part of the lateral isolation region.
- the extrinsic base and extrinsic collector regions also comprise second zones extending in the intrinsic collector, in practice produced by implantation.
- the base and collector metallizations are respectively located in contact with said first corresponding zones above said first part of the lateral isolation region.
- the bipolar transistor according to the invention does not include an extrinsic collector formed by a collector well and a buried layer.
- the extrinsic collector is formed here essentially in the semiconductor layer, for example with heterojunction.
- the base, and therefore the base metallization, does not completely surround the emitter. Therefore, it is necessary that the extrinsic collector and extrinsic base regions are electrically isolated which is achieved in the invention by a part of the lateral isolation region.
- the bipolar transistor according to the invention therefore has not only a basic metallization overflowing on the field oxide, but also an extrinsic collector metallization overflowing on the field oxide which further contributes to increasing the operating speed of the transistor and which makes it possible to obtain both a reduced extrinsic base-collector capacity and also a reduced collector-substrate capacity.
- the absence of a remote collector well makes it possible to obtain a particularly compact bipolar transistor.
- the transistor has two layers of amorphous silicon resting on the first part of the lateral isolation region respectively under said first areas of the extrinsic base and of the extrinsic collector, these two layers of silicon amorphous projecting beyond the lateral isolation region respectively towards the emitter.
- the emitter region comprises a projecting zone surrounded by insulating spacers and extending by a narrower window in contact with the intrinsic base. The distance between the edge of the window and the insulating spacer located on the extrinsic collector side is then advantageously greater than the distance between the edge of the window and the insulating spacer located on the side of the extrinsic base.
- the invention also relates to a method of manufacturing a vertical bipolar transistor.
- this method comprises a step of implanting an intrinsic collector region in a region of semiconductor substrate surrounded by an insulating lateral region and a step of producing the extrinsic base regions, base intrinsic and extrinsic collector.
- This production step includes the formation, by selective epitaxy, of a semiconductor layer, for example with SiGe heterojunction, extending over the intrinsic collector region and above the lateral isolation region.
- This production step also includes implantations of dopants through first predetermined zones of this semiconductor layer, for example heterojunction, located respectively on either side of the intrinsic collector and above a first part of the region d lateral isolation and mutually electrically isolated by a second part of the lateral isolation region. There are also plans for implantations in second predetermined zones of the intrinsic collector. The extrinsic base and extrinsic collector regions are thus formed.
- the method according to the invention also comprises a step of producing contact metallizations comprising producing base and collector contact metallizations respectively on either side of the emitter region and above the first part of the region insulating side.
- the formation of the semiconductor layer comprises the deposition of an amorphous silicon layer on the intrinsic collector and on the insulating lateral region, an etching of this layer of amorphous silicon so as to leave on each side of the exposed surface of the intrinsic collector two distinct zones of amorphous silicon extending respectively over the first part of the insulating lateral region and projecting respectively over the uncovered surface of the intrinsic collector, then said selective epitaxy on the uncovered area of the intrinsic collector and on the two distinct areas of amorphous silicon.
- the method according to the invention also advantageously comprises a step of producing the emitter region comprising the deposition of an insulating bilayer on the semiconductor layer, for example with heterojunction, then the etching of the bilayer so as to produce a window uncovering an area of the semiconductor layer located above the intrinsic collector.
- This step also includes depositing a layer of polysilicon on the unetched part of the insulating bilayer and in said window, then etching the polysilicon so as to produce a protruding part of polysilicon, wider than the window, the distance between the edge of the window and the edge of the projection on the extrinsic collector side being greater than the distance between the edge of the window and the edge of the projection on the extrinsic base side.
- FIGS. 1 to 5 schematically illustrate a mode for implementing the method according to the invention making it possible to obtain a transistor according to the invention
- FIG. 6 schematically illustrates a structure of a bipolar transistor according to the invention.
- the reference 1 generally designates a P-type semiconductor substrate (for example).
- lateral isolation regions 2 field oxide
- a lateral isolation method by narrow trenches and a shallow insulating barrier layer 3 is formed, formed of silicon dioxide (SiO2) and having a typical thickness of the order of 100 ⁇ .
- a standard N-type implantation is then carried out in the active zone so as to produce the intrinsic collector region 4.
- a layer 5 of amorphous silicon typically having a thickness of 500 ⁇ .
- a conventional etching of this layer is carried out with stopping on the oxide layer 3.
- two layers of amorphous silicon 50 and 51 are obtained (FIGS. 3 and 4) extending above a first part 200 and 201 of the insulating lateral region 2, and mutually electrically insulated by a second part 202 of this insulating lateral region.
- These two layers of amorphous silicon 50 and 51 also extend beyond the surface of the intrinsic collector 4 discovered after deoxidation.
- this heterojunction layer consists of a stack of a first silicon sublayer surmounted by a sublayer of Si j _ ⁇ Ge ⁇ (with x typically of the order of 10%), this second sublayer being itself encapsulated by another silicon sublayer.
- the epitaxy is selective in the sense that the growth of the heterojunction layer takes place only on the two layers of amorphous silicon 50 and 51 and on the intrinsic collector region 4.
- a selective epitaxy is an operation perfectly known to those skilled in the art. It uses in particular gases such as dichlorosilane (SiH 2 Cl 2 ) Due to the presence of the two layers of amorphous silicon 50 and 51, there will be growth of polycrystalline silicon on these two layers. There will also be growth of monocrystalline silicon on the intrinsic collector region 4. Furthermore, the presence of these layers 50 and 51 on the collector makes it possible to obtain a substantially identical growth rate between the monocrystalline silicon and the polycrystalline silicon. This would not have been the case if silicon had been grown directly on oxide. Furthermore, the overflow of the layers 50 and 51 makes it possible to ensure that there are no parts formed of SiO 2 on which the selective epitaxy of the heterojunction layer would have led to an absence of silicon at these locations.
- the thickness of the heterojunction layer 6 is typically of the order of 1000 to 1500 A.
- the next step is the deposition on the heterojunction layer 6 (FIG. 4) of an insulating bilayer formed of a first insulating layer 7 of silicon oxide Si02 surmounted by a second insulating layer 8 of silicon nitride Si 3 N.
- a photolithography step is then carried out (FIG. 5) making it possible to define the window 80 of the emitter, then an etching of the insulating bilayer 7, 8 so as to effectively define the emitting window 80.
- the etching of the nitride layer of silicon is a plasma etching with stop on the layer 7 of silicon oxide while the etching of the oxide layer 7 is a chemical etching using the layer of silicon nitride as a mask.
- a layer 9 of N + doped polysilicon is then deposited, typically having a thickness of the order of 2500 Angstroms, which is then etched so as to form the emitter region 90 formed of polysilicon (FIG. 6).
- the emitter polysilicon is advantageously etched asymmetrically so as to obtain a distance L1 between the edge of the window 80 and the edge of the region 90 shorter than the distance L2 between the edge of the window 80 and the edge of the region 90.
- This makes it possible to take account of the lateral diffusion differential between the implants of the extrinsic base and of the extrinsic collector, which will be described below.
- spacers 100 formed of silicon nitride.
- a P + type implantation for example with boron ions, of the assembly thus obtained so as to produce the extrinsic base.
- An N + type implantation (for example based on phosphorus) is likewise carried out on the assembly thus obtained so as to produce the extrinsic collector.
- This transistor has an intrinsic base 60 with a SiGe heterojunction disposed between the polysilicon emitter 90 and the intrinsic collector 4.
- the extrinsic base has a first zone 61 formed in the heterojunction layer 6 and disposed on one side of the emitter, thus that a second implanted zone 62 projecting into the intrinsic collector.
- the extrinsic collector comprises a first zone 63 formed in the heterojunction layer 6 on the other side of the emitter, and a second implanted zone 64 projecting into the intrinsic collector.
- the first zones 61 and 63 of the extrinsic base and of the extrinsic collector are located above the field oxide 200 and 201. It is therefore the same for the contact metallizations.
- the invention has been described with a heterojunction semiconductor layer 6 leading to the production of a heterojunction base for the vertical transistor, which makes it possible to optimize the adjustment of the transistor and in particular to further increase its speed (that is to say increasing the transition frequency and the maximum oscillation frequency), the invention also applies to any type of epitaxial base, in particular an entirely silicon base, and makes it possible in particular to obtain, even with any type of base, reduced collector-substrate and extrinsic-collector base capacities.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/674,021 US6384469B1 (en) | 1998-04-22 | 1999-04-14 | Vertical bipolar transistor, in particular with an SiGe heterojunction base, and fabrication process |
JP2000545198A JP4643005B2 (ja) | 1998-04-22 | 1999-04-14 | バイポーラトランジスタ、およびその製造方法 |
EP99913403A EP1074051A1 (fr) | 1998-04-22 | 1999-04-14 | TRANSISTOR BIPOLAIRE VERTICAL, EN PARTICULIER A BASE A HETEROJONCTION SiGe, ET PROCEDE DE FABRICATION |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9805019A FR2778022B1 (fr) | 1998-04-22 | 1998-04-22 | Transistor bibolaire vertical, en particulier a base a heterojonction sige, et procede de fabrication |
FR98/05019 | 1998-04-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999054939A1 true WO1999054939A1 (fr) | 1999-10-28 |
Family
ID=9525522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR1999/000867 WO1999054939A1 (fr) | 1998-04-22 | 1999-04-14 | TRANSISTOR BIPOLAIRE VERTICAL, EN PARTICULIER A BASE A HETEROJONCTION SiGe, ET PROCEDE DE FABRICATION |
Country Status (5)
Country | Link |
---|---|
US (1) | US6384469B1 (fr) |
EP (1) | EP1074051A1 (fr) |
JP (1) | JP4643005B2 (fr) |
FR (1) | FR2778022B1 (fr) |
WO (1) | WO1999054939A1 (fr) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2779573B1 (fr) * | 1998-06-05 | 2001-10-26 | St Microelectronics Sa | Transistor bipolaire vertical comportant une base extrinseque de rugosite reduite, et procede de fabrication |
US6784467B1 (en) * | 2002-08-13 | 2004-08-31 | Newport Fab, Llc | Method for fabricating a self-aligned bipolar transistor and related structure |
US6444535B1 (en) * | 2001-05-09 | 2002-09-03 | Newport Fab, Llc | Method to reduce emitter to base capacitance and related structure |
US20020197807A1 (en) * | 2001-06-20 | 2002-12-26 | International Business Machines Corporation | Non-self-aligned SiGe heterojunction bipolar transistor |
US6670654B2 (en) * | 2002-01-09 | 2003-12-30 | International Business Machines Corporation | Silicon germanium heterojunction bipolar transistor with carbon incorporation |
US6617619B1 (en) * | 2002-02-04 | 2003-09-09 | Newport Fab, Llc | Structure for a selective epitaxial HBT emitter |
US6597022B1 (en) * | 2002-02-04 | 2003-07-22 | Newport Fab, Llc | Method for controlling critical dimension in an HBT emitter and related structure |
KR20040038511A (ko) * | 2002-11-01 | 2004-05-08 | 한국전자통신연구원 | 자기정렬형 이종접합 쌍극자 트랜지스터 및 그의 제조 방법 |
US6686250B1 (en) * | 2002-11-20 | 2004-02-03 | Maxim Integrated Products, Inc. | Method of forming self-aligned bipolar transistor |
US6919253B2 (en) * | 2003-02-07 | 2005-07-19 | Matsushita Electric Industrial Co., Ltd. | Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer |
US6797580B1 (en) * | 2003-02-21 | 2004-09-28 | Newport Fab, Llc | Method for fabricating a bipolar transistor in a BiCMOS process and related structure |
US6881640B2 (en) * | 2003-09-05 | 2005-04-19 | United Microelectronics Corp. | Fabrication method for heterojunction bipolar transistor |
US6972237B2 (en) * | 2003-12-01 | 2005-12-06 | Chartered Semiconductor Manufacturing Ltd. | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth |
CN100394562C (zh) * | 2003-12-12 | 2008-06-11 | 联华电子股份有限公司 | 异质接面双极晶体管制造方法 |
US7566919B2 (en) * | 2003-12-12 | 2009-07-28 | Nxp B.V. | Method to reduce seedlayer topography in BICMOS process |
ATE400063T1 (de) * | 2004-07-15 | 2008-07-15 | Nxp Bv | Bipolartransistor und herstellungsverfahren dafür |
DE102004053394B4 (de) * | 2004-11-05 | 2010-08-19 | Atmel Automotive Gmbh | Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung |
US7511317B2 (en) * | 2006-06-09 | 2009-03-31 | International Business Machines Corporation | Porous silicon for isolation region formation and related structure |
SE1150065A1 (sv) * | 2011-01-31 | 2012-07-17 | Fairchild Semiconductor | Bipolär transistor i kiselkarbid med övervuxen emitter |
US9887278B2 (en) | 2015-09-28 | 2018-02-06 | International Business Machines Corporation | Semiconductor-on-insulator lateral heterojunction bipolar transistor having epitaxially grown intrinsic base and deposited extrinsic base |
CN118043973A (zh) * | 2021-09-24 | 2024-05-14 | 华为技术有限公司 | 半导体结构及其制备方法、射频电路、终端 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0350610A2 (fr) * | 1988-07-14 | 1990-01-17 | International Business Machines Corporation | Procédé pour la formation d'un transistor bipolaire ayant un émetteur et une base autoalignés utilisant une épitaxie sélective et non sélective |
EP0367293A2 (fr) * | 1988-11-04 | 1990-05-09 | Matsushita Electric Industrial Co., Ltd. | Dispositif semi-conducteur avec base auto-alignée et méthode de sa fabrication |
US5070028A (en) * | 1990-06-07 | 1991-12-03 | Siemens Aktiengesellschaft | Method for manufacturing bipolar transistors having extremely reduced base-collection capacitance |
JPH0488637A (ja) * | 1990-07-31 | 1992-03-23 | Nec Corp | 縦型バイポーラトランジスタを有する半導体集積回路装置 |
EP0779652A2 (fr) * | 1995-12-12 | 1997-06-18 | Lucent Technologies Inc. | Méthode de fabrication d'un transistor bipolaire à hétérojonction |
EP0779664A2 (fr) * | 1995-12-12 | 1997-06-18 | Lucent Technologies Inc. | Dispositif comprenant un transistor bipolaire à hétérojonction |
JPH1065015A (ja) * | 1996-08-19 | 1998-03-06 | Sony Corp | 半導体装置およびその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3600651A (en) * | 1969-12-08 | 1971-08-17 | Fairchild Camera Instr Co | Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon |
JP2538077B2 (ja) * | 1988-11-04 | 1996-09-25 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US5073810A (en) * | 1989-11-07 | 1991-12-17 | Hitachi, Ltd. | Semiconductor integrated circuit device and manufacturing method thereof |
US5117271A (en) * | 1990-12-07 | 1992-05-26 | International Business Machines Corporation | Low capacitance bipolar junction transistor and fabrication process therfor |
JPH106515A (ja) * | 1996-06-26 | 1998-01-13 | Canon Inc | 記録ヘッド用基体、該記録ヘッド用基体を用いた記録ヘッ ド及び該記録ヘッドを用いた記録装置 |
JPH10135238A (ja) * | 1996-11-05 | 1998-05-22 | Sony Corp | 半導体装置およびその製造方法 |
WO2000013227A2 (fr) * | 1998-08-31 | 2000-03-09 | Koninklijke Philips Electronics N.V. | Procede de production d'un dispositif a semi-conducteur dote d'un transistor bipolaire |
-
1998
- 1998-04-22 FR FR9805019A patent/FR2778022B1/fr not_active Expired - Fee Related
-
1999
- 1999-04-14 JP JP2000545198A patent/JP4643005B2/ja not_active Expired - Fee Related
- 1999-04-14 US US09/674,021 patent/US6384469B1/en not_active Expired - Fee Related
- 1999-04-14 EP EP99913403A patent/EP1074051A1/fr not_active Withdrawn
- 1999-04-14 WO PCT/FR1999/000867 patent/WO1999054939A1/fr not_active Application Discontinuation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0350610A2 (fr) * | 1988-07-14 | 1990-01-17 | International Business Machines Corporation | Procédé pour la formation d'un transistor bipolaire ayant un émetteur et une base autoalignés utilisant une épitaxie sélective et non sélective |
EP0367293A2 (fr) * | 1988-11-04 | 1990-05-09 | Matsushita Electric Industrial Co., Ltd. | Dispositif semi-conducteur avec base auto-alignée et méthode de sa fabrication |
US5070028A (en) * | 1990-06-07 | 1991-12-03 | Siemens Aktiengesellschaft | Method for manufacturing bipolar transistors having extremely reduced base-collection capacitance |
JPH0488637A (ja) * | 1990-07-31 | 1992-03-23 | Nec Corp | 縦型バイポーラトランジスタを有する半導体集積回路装置 |
EP0779652A2 (fr) * | 1995-12-12 | 1997-06-18 | Lucent Technologies Inc. | Méthode de fabrication d'un transistor bipolaire à hétérojonction |
EP0779664A2 (fr) * | 1995-12-12 | 1997-06-18 | Lucent Technologies Inc. | Dispositif comprenant un transistor bipolaire à hétérojonction |
JPH1065015A (ja) * | 1996-08-19 | 1998-03-06 | Sony Corp | 半導体装置およびその製造方法 |
Non-Patent Citations (3)
Title |
---|
BURGHARTZ J N ET AL: "SELF-ALIGNED SIGE-BASE HETEROJUNCTION BIPOLAR TRANSISTOR BY SELECTIVE EPITAXY EMITTER WINDOW (SEEW) TECHNOLOGY", IEEE ELECTRON DEVICE LETTERS, vol. 11, no. 7, 1 July 1990 (1990-07-01), pages 288 - 290, XP000133226 * |
PATENT ABSTRACTS OF JAPAN vol. 016, no. 316 (E - 1231) 10 July 1992 (1992-07-10) * |
PATENT ABSTRACTS OF JAPAN vol. 098, no. 008 30 June 1998 (1998-06-30) * |
Also Published As
Publication number | Publication date |
---|---|
US6384469B1 (en) | 2002-05-07 |
JP2002512452A (ja) | 2002-04-23 |
JP4643005B2 (ja) | 2011-03-02 |
EP1074051A1 (fr) | 2001-02-07 |
FR2778022B1 (fr) | 2001-07-13 |
FR2778022A1 (fr) | 1999-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO1999054939A1 (fr) | TRANSISTOR BIPOLAIRE VERTICAL, EN PARTICULIER A BASE A HETEROJONCTION SiGe, ET PROCEDE DE FABRICATION | |
EP1266409B1 (fr) | Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor | |
EP0962967B1 (fr) | Procédé de dopage sélectif du collecteur intrinsèque d'un transistor bipolaire vertical à base épitaxiée | |
EP0962966A1 (fr) | Transistor bipolaire vertical à faible bruit et procédé de fabrication correspondant | |
US7074685B2 (en) | Method of fabrication SiGe heterojunction bipolar transistor | |
FR2823009A1 (fr) | Procede de fabrication d'un transistor vertical a grille isolee a faible recouvrement de la grille sur la source et sur le drain, et circuit integre comportant un tel transistor | |
FR2779573A1 (fr) | Transistor bipolaire vertical comportant une base extrinseque de rugosite reduite, et procede de fabrication | |
EP1087424B1 (fr) | Procédé de fabrication d'un transistor bipolaire vertical auto-aligné | |
EP1139407A1 (fr) | Procédé de fabrication d'un transistor bipolaire de type double-polysilicium auto-aligné à base à hétérojonction et transistor correspondant | |
EP1292991B1 (fr) | Procédé de fabrication d'un transistor MOS vertical à grille enterrée | |
JP2002525874A (ja) | バイポーラトランジスタ及びその製造方法 | |
FR2824666A1 (fr) | Transistor bipolaire a fonctionnement lateral et procede de fabrication correspondant | |
JP2002231727A (ja) | SiGeヘテロ接合バイポーラ・トランジスタ及びその製造方法 | |
EP1146561A1 (fr) | Procédé de réalisation d'un transistor bipolaire | |
EP1058302A1 (fr) | Procédé de fabrication de dispositifs bipolaires à jonction base-émetteur autoalignée | |
FR2801420A1 (fr) | Transistor bipolaire vertical a faible bruit basse frequence et gain en courant eleve, et procede de fabrication correspondant | |
EP0675544A1 (fr) | Procédé de fabrication d'un transistor à effet de champ à grille isolée de longueur de canal réduite, et transistor correspondant | |
EP1006573A1 (fr) | Procédé de fabrication de circuits intégrés BICMOS sur un substrat CMOS classique | |
EP1241704A1 (fr) | Procédé de fabrication d'un transistor bipolaire de type double polysilicum à base à hétérojonction et transistor correspondant | |
US6465318B1 (en) | Bipolar transistor and method for producing same | |
FR2868203A1 (fr) | Procede de fabrication d'un transistor bipolaire a base extrinseque monocristalline | |
EP1475830A2 (fr) | Procédé de fabrication d'un transistor bipolaire | |
EP1575098A1 (fr) | Condensateur intégré | |
FR3138965A1 (fr) | Transistor MOSFET | |
FR3141800A1 (fr) | Transistor MOSFET |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1999913403 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09674021 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 1999913403 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1999913403 Country of ref document: EP |