WO1999052013A1 - Substrat de groupements tft pour ecran a cristaux liquides et son procede de production, et ecran a cristaux liquides et son procede de production - Google Patents

Substrat de groupements tft pour ecran a cristaux liquides et son procede de production, et ecran a cristaux liquides et son procede de production Download PDF

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Publication number
WO1999052013A1
WO1999052013A1 PCT/JP1999/001646 JP9901646W WO9952013A1 WO 1999052013 A1 WO1999052013 A1 WO 1999052013A1 JP 9901646 W JP9901646 W JP 9901646W WO 9952013 A1 WO9952013 A1 WO 9952013A1
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Prior art keywords
substrate
tft
liquid crystal
manufacturing
crystal display
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PCT/JP1999/001646
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English (en)
Japanese (ja)
Inventor
Kazufumi Ogawa
Kazuyasu Adachi
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Matsushita Electric Industrial Co., Ltd.
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Priority claimed from JP8572698A external-priority patent/JP3288968B2/ja
Priority claimed from JP8569998A external-priority patent/JPH11282013A/ja
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to US09/647,397 priority Critical patent/US6472297B1/en
Priority to EP99909351A priority patent/EP1069465A1/fr
Priority to KR1020007010478A priority patent/KR20010071123A/ko
Publication of WO1999052013A1 publication Critical patent/WO1999052013A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to an active matrix type TFT array substrate for a liquid crystal display device using a thin film transistor. Background technology
  • poly-Si TFTs low-temperature process type polysilicon thin film transistors
  • poly-Si TFTs have been used as control elements.
  • the development of matrix type liquid crystal display devices has been active.
  • poly-Si TFTs have a higher field-effect mobility than amorphous silicon TFTs, so that higher definition and higher aperture ratio of liquid crystal display devices can be achieved.
  • a low-temperature process type can use an inexpensive glass substrate, there is a possibility that a large-area, high-definition liquid crystal display device can be provided at low cost.
  • FIG. 7 is a cross-sectional view showing a manufacturing procedure of the low-temperature process poly-Si type TF II.
  • reference numeral 701 denotes a glass substrate
  • reference numeral 702 denotes a knob layer
  • reference numeral 703 denotes a layer.
  • Amorphous silicon layer 704 is a polysilicon layer
  • 705 is a gate insulating layer
  • 706 is a gate electrode
  • 707 is a source region
  • 708 is a gate.
  • In the drain region 709 is a contact hole
  • 710 is a source electrode
  • 711 is a drain electrode.
  • a glass layer 70 2 composed of a Si 3 N 4 layer having a thickness of, for example, 60 OA is formed on a glass substrate 70 1, and this metal buffer is formed.
  • Amorphous silicon is deposited on the entire surface of layer 702 (Fig. 7 (a)).
  • the entire surface of the amorphous silicon layer 703 is irradiated with an excimer laser, and the silicon is heated and melted to be recrystallized.
  • the gate insulating layer 705 is etched to form contact holes 709 and 709 that reach the source region 707 and the drain region 708.
  • a contact electrode 710 and a drain electrode 711 having a film thickness of 300 A with A 1 buried in the contact holes 709 and 709 are formed.
  • a low-temperature process poly-Si TFT is completed.
  • excimer laser light is used for polycrystallization, so that the substrate temperature rise is small (approximately 600 ° C. or less).
  • an inexpensive glass substrate can be used, and a large-area polysilicon thin film can be formed as compared with the high-temperature process method (approximately 100 or more). Therefore, the liquid crystal display device can have a large screen.
  • An object of the present invention is to solve the above-mentioned problems in the conventional low-temperature process poly-Si type TFT. More specifically, it is possible to provide a poly-Si type TFT array substrate having a high field effect mobility and a small in-plane variation of the field effect mobility without using an expensive quartz substrate. aimed to. It is another object of the present invention to provide a large-screen, high-definition, high-performance liquid crystal display device at a lower cost using such a poly-Si type TFT array substrate.
  • FIG. 4 is a schematic plan view of the TFT array substrate.
  • reference numeral 412 denotes a glass substrate
  • reference numeral 413 denotes a pixel portion formed on the glass substrate 412.
  • pixels are arranged in a matrix shape in the pixel section 413, and a TFT for pixel switch is arranged corresponding to each pixel.
  • Reference numerals 414 and 415 denote so-called peripheral drive circuits for driving the TFTs for the pixel switches.
  • reference numeral 414 denotes a gate drive circuit unit having a built-in TFT
  • reference numeral 415 denotes a TFT. This is the source drive circuit section that incorporates.
  • amorphous silicon is deposited on the entire surface of the glass substrate 412, and thereafter, an excimer laser is formed on almost the entire surface of the amorphous silicon layer.
  • a single light is applied to melt the silicon and make it polycrystalline.
  • the width of one light of an excimer laser is limited, so that a large area cannot be irradiated at one time. Therefore, a method of sequentially scanning the substrate surface with a line-shaped excimer laser beam (line beam) is adopted. According to this method, a long width in the line direction of the line beam is used. It becomes narrow crystal grains.
  • the shape and size of the crystal grains are likely to be non-uniform.
  • the amorphous silicon layer has no crystal nuclei that induce crystal growth in the initial stage of crystallization.
  • the excimer laser is irradiated, and crystal nuclei are generated uncertainly and randomly at a certain stage when crystallization starts, and crystals grow rapidly. Therefore, the crystal growth becomes unstable and disordered, and as a result, the shape and size of the crystal grains become uneven.
  • minute crystal grains may bulge up at the grain boundaries where they collide, or the structure of the grain boundaries may be distorted.
  • the present inventors scan the amorphous silicon layer of 320 mm ⁇ 400 mm with an excimer laser beam (line beam) to perform polycrystallization, and When the field-effect mobility of each part of the polysilicon layer was examined, the field-effect mobility varied depending on the part within the range of 50 to 300 cm 1 / Vs. This was confirmed. It was also confirmed that the polysilicon in the peripheral region had a higher field-effect mobility than the polysilicon in the vicinity of the center.
  • the field-effect mobility of the polysilicon layer becomes non-uniform, and particularly, the pixel portion has an array-like shape. Since this tendency is remarkable in the TFT formed in the above, it is considered that display unevenness (for example, linear unevenness) occurs.
  • the high-temperature process polycrystallization method approximately 100 ° C or more
  • the low-temperature process method is not used.
  • the present invention for solving the above-mentioned problems is configured as follows. In the following, the present invention will be described in order of the first invention group to the seventh invention group.
  • the first aspect of the present invention according to the first invention group is a liquid crystal having a process of forming a poly-Si type TFT on a substrate using a polysilicon semiconductor layer in a channel region.
  • a polysilicon layer having a uniform in-plane field-effect mobility can be formed.
  • the reason is as follows.
  • a conventional method of forming a polysilicon layer is to deposit amorphous silicon on a substrate and then heat and melt the amorphous silicon to recrystallize it. A silicon layer was being produced.
  • crystal nuclei are generated in an uncertain and random manner in the initial stage after heating and melting, and the shape and size of the crystal grains are not uniform, so that the field effect mobility varies. Problems arise.
  • the above-described configuration uses a silicon particle to which energy is added, thereby producing a polysilicon layer at the stage when the silicon particle is deposited on the substrate.
  • the silicon particles to which the energy is added have energy above a steady level for a while after reaching the substrate.
  • migration occurs on the substrate, and the energy state moves to a stable point where the energy state becomes more stable.
  • the temperature distribution becomes non-uniform, so that it is difficult to form a high-quality polysilicon layer.
  • the silicon particles to which energy is added are sequentially irradiated on the substrate to simultaneously perform polycrystallization, so that the uniform polysilicon is not affected by the size of the substrate area.
  • the production efficiency is high because a heat-melting layer can be formed and heating and melting are not required.
  • a polysilicon layer formed by the polysilicon layer forming step is further provided.
  • a heat treatment step for heating, melting and recrystallizing the silicon layer is added.
  • the polysilicon layer formed in the polysilicon layer forming step has a remarkably high field-effect mobility.
  • a third aspect of the first invention group is characterized in that the heat treatment in the heat treatment step is performed in an atmosphere containing hydrogen.
  • the TFT using the polysilicon layer as a channel region has a high speed. Therefore, it can be suitably used as an element for a pixel switch and also as an element for a driving circuit of the pixel switch. Therefore, the above-described manufacturing method, in which a poly-Si TFT for pixel switching and a poly-Si TFT for driving the same on a single substrate, are formed together, a liquid crystal with high speed and high integration can be obtained. TFT array substrates for display devices can be manufactured efficiently.
  • the specific region for forming the driving poly-Si type TFT is provided before the step of forming the driving poly-Si type TFT. Only heat treatment selectively It is characterized by having a specific region heat treatment step for increasing the crystallinity of the polysilicon layer in the region.
  • a sixth aspect according to the first invention group is characterized in that, in the fifth aspect, an excimer laser or an infrared lamp is used as a heating means in the specific area heating treatment step. I do. Excimer lasers or infrared lamps are preferred because they can be partially heated and have good heating efficiency.
  • FIGS. 4 (a) and 4 (b) are plan views schematically showing a general TFT array substrate for a liquid crystal display device.
  • the difference between FIGS. 4 (a) and 4 (b) is the display of the liquid crystal display device.
  • the point is that the area of the part is different. That is, FIG. 4 (b) has a larger display area than FIG. 4 (a).
  • the excimer laser light is applied to almost the entire surface of the substrate. Must be irradiated. But, At present, there is no device that can irradiate a large area with one light of excimer laser at a time.
  • the layer formed on the substrate is a polysilicon layer from the beginning
  • the second is that only a limited specific area on the substrate is subjected to heat treatment (recrystallization). Processing).
  • the width of the drive circuit section is not significantly affected by the size of the display section. Therefore, if only the driving circuit portion is recrystallized, recrystallization can be achieved without requiring a special excimer laser irradiation device.
  • the other part is a polysilicon layer, it has sufficient field-effect mobility without recrystallization.
  • a higher quality polysilicon layer can be obtained as compared with the case where the amorphous layer is crystallized.
  • uniform transistor characteristics can be obtained over the entire surface of the array substrate.
  • a seventh aspect according to the first invention group is characterized in that, in the sixth aspect, the heat treatment in the specific region heat treatment step is performed in an atmosphere containing hydrogen. Heat treatment in a hydrogen atmosphere can terminate the silicon dangling bond, which is preferable in that the field-effect mobility of the polysilicon layer can be further improved.
  • the heat treatment is performed so that the field-effect mobility of the specific region is 100 cm 2 / Vs or more. It is characterized by performing. When the field effect mobility is 100 cm ! / D ⁇ s or more, high frequency driving becomes possible.
  • a ninth aspect according to a first aspect of the present invention is the method according to the second aspect, wherein after the heat treatment step, a poly-Si TFT for a pixel switch for switching pixels is manufactured.
  • An IC chip mounting step for mounting a single-crystal silicon IC chip including a circuit for driving a poly-Si TFT for a pixel switch manufactured by the above-described manufacturing method on the substrate. It is characterized by having.
  • poly-Si TFTs can perform switching at a much higher speed than amorphous Si TFTs
  • single-crystal series that can be driven at high frequency can be used for the poly-Si TFTs for pixel switches.
  • a TFT array substrate for liquid crystal display devices with excellent response speed that can fully utilize the high-speed operation performance of the single-crystal silicon IC chip is manufactured. it can.
  • the step of forming a polysilicon layer in the first aspect is performed by applying thermal energy to an evaporation source made of solid silicon.
  • the silicon is evaporated to silicon particles, which are excited in the plasma region and ionized, and then excited. And irradiating the substrate with silicon particles in a dry state to deposit the particles.
  • the polysilicon layer is formed using an evaporation source made of the same silicon as the material constituting the polysilicon layer, impurities are added to the polysilicon layer. No contamination.
  • this method using an evaporation source can increase the silicon particle generation area and irradiate the silicon particles from multiple directions to the substrate surface. . Therefore, a polysilicon layer having excellent uniformity can be formed, and this effect is remarkably exhibited particularly when a large-area polysilicon layer is formed.
  • the silicon particles are excited in the plasma region to be ionized, and then irradiated on the substrate surface to form a deposited layer.
  • the silicon particles irradiated by this method are used. Holds energy even after reaching the substrate, and can move (migrate) to a stable point where the energy state becomes more stable on the substrate. Therefore, if a defect occurs in the crystal during the crystallization process, the newly irradiated silicon particles will migrate and eliminate the defect.
  • a dense silicon layer having few crystal defects is formed by the movement of the silicon particles. Such a polysilicon layer is excellent in the transistor characteristics.
  • a eleventh aspect according to a first invention group is characterized in that, in the tenth aspect, the substrate in the polysilicon layer forming step is arranged outside a plasma region. I do. When the substrate is placed in the plasma region, the substrate temperature rises due to the collision of the plasma particles. However, this is not the case with the above configuration in which the substrate is placed outside the plasma region. Therefore, an inexpensive glass substrate having a low heat-resistant temperature can be used.
  • a twelfth aspect according to a first invention group is the twelfth aspect, in the first aspect, wherein the substrate in the polysilicon layer forming step is configured such that silicon particles are evaporated from the evaporation source. It is characterized by being arranged in a direction different from the direction.
  • the evaporated silicon particles once move away from the substrate, and then only the excited and ionized particles having a high energy are irradiated to the substrate surface. .
  • the step of forming a polysilicon layer in the first aspect is formed by decomposing a gaseous silicon compound with high-frequency energy.
  • the method is characterized in that, after the silicon particles thus excited are excited in a plasma region to be ionized, the silicon particles in an excited state are irradiated onto the substrate to deposit them.
  • a fourteenth aspect according to a first invention group is characterized in that, in the thirteenth aspect, the substrate in the polysilicon layer forming step is arranged outside a plasma region. And According to this configuration, the same function and effect as in the eleventh embodiment can be obtained.
  • the silicon particles excited and ionized in the plasma region are extracted and irradiated onto the substrate.
  • the electric field applying means are extracted and irradiated on the substrate. Due to the high energy levels, they are actively migrated on the substrate to form a better polysilicon layer. Therefore, a higher-speed poly-Si type TFT can be formed.
  • the step of forming a polysilicon layer comprises applying arc discharge energy to an evaporation source made of solid silicon.
  • excited and ionized silicon particles are produced using a pressure gradient plasma gun equipped with a means for irradiating and depositing the silicon particles on the substrate.
  • a seventeenth aspect of the present invention according to a second invention group is a method for manufacturing a TFT array substrate for a liquid crystal display device, comprising a process of manufacturing a TFT on a substrate, wherein the material forming the gate insulating layer is provided.
  • Heat energy is applied to a solid evaporation source composed of the same substance as above to evaporate the substance to form particles, which are excited in the plasma region to be ionized and irradiated to the substrate.
  • a gate insulating layer forming step for forming a gate insulating layer on the silicon semiconductor layer in the channel region of the TFT by depositing the gate is provided.
  • the gate insulating layer forming step is a vapor deposition method having the same principle as the method of forming the polysilicon layer described in the first invention group.
  • this vapor deposition method the same material as the material constituting the gate insulating layer is used as an evaporation source, and particles evaporated from this evaporation source are stacked to form a gate insulating layer, so that there are few impurities.
  • a gate insulating layer can be formed.
  • the silicon layer which is the active layer of the TFT, is not exposed to the air by adopting the load lock method, so that the polysilicon layer can be formed.
  • a gate insulating layer can be continuously formed on the layer. Therefore, contamination at the interface between the silicon layer and the gate insulating layer can be completely prevented.
  • a uniform and dense gate insulating layer can be formed as in the case of the polysilicon layer, and as a result, the variation in transistor characteristics is reduced.
  • a small number of TFT array substrates can be manufactured.
  • An eighteenth aspect according to a third invention is a method of manufacturing a TFT array substrate for a liquid crystal display device having a process of forming a TFT on a substrate, the method being the same as the element constituting the gate insulating layer.
  • a gaseous compound containing an element is decomposed by using high-frequency energy to generate element particles, and the element particles are excited in a plasma region, ionized, and irradiated on the substrate, thereby forming the TFT.
  • This configuration utilizes the same principle as that of the thirteenth aspect of the first invention group for forming the gate insulating layer.
  • This configuration also has the Vt characteristic (the operation of the transistor). It is possible to form a TFT group with less variation in threshold voltage (threshold voltage).
  • a ninth aspect according to a fourth invention group is a method for manufacturing a TFT array substrate for a liquid crystal display device, which has a process of manufacturing a poly_Si type TFT on a substrate, the method comprising a solid silicon.
  • the thermal energy is applied to the evaporation source to evaporate the silicon into silicon particles, which are excited in the plasma region, ionized, and irradiated to the substrate.
  • the step of forming a polysilicon layer on a substrate and the step of applying heat energy to a solid-state evaporation source made of the same material as the material constituting the gate insulating layer The source is evaporated to form particles, and the particles are excited in a plasma region, ionized, irradiated on the substrate, and laminated to form a gate insulating layer, thereby forming a gate insulating layer. And a step.
  • a TFT group having a high field-effect mobility and a small variation in v t characteristics can be manufactured with high production efficiency.
  • a twenty-fifth aspect according to a fourth invention group is the twelfth aspect, wherein the apparatus for performing the polysilicon layer forming step and the gate insulating layer forming step is provided. Then, a particle generating means for irradiating the evaporation source made of a solid substance with arc discharge energy to evaporate the evaporation source to form particles, and an excitation means for guiding the generated particles to a plasma region to excite and ionize. It is characterized by using a pressure gradient plasma gun equipped with a pressure gradient plasma gun.
  • Evaporated particles can be efficiently generated by using the above-mentioned pressure gradient plasma gun. Also, the evaporation area can be increased. Therefore, a uniform thin film having a small variation in the film density can be formed, and this effect is remarkably exerted particularly when the area of the thin film becomes large. (5) Fifth invention group
  • At least a twenty-first aspect according to a fifth aspect of the present invention is a pixel switch TFT for switching the transparent pixel electrode, a transparent pixel electrode, and a drive for driving the pixel switch TFT.
  • the TFT for the pixel switch has a field-effect mobility of 1 to 25 cm '/ Vs.
  • Poly-Si TFTs having a field-effect mobility of 100 cm ! / Vs or more are used as the driving elements, and these poly-Si TFTs are used.
  • the transparent pixel electrode is formed on the transparent substrate.
  • the pixel can be switched at a sufficient speed, and if the field-effect mobility is within this range, it can be printed on the substrate. It can be manufactured by a method of forming a silicon layer at the stage where silicon particles are deposited. Therefore, even if the area of the display section is increased, switching without variation can be performed.
  • a field-effect mobility of 100 cm ! / Vs or more can be realized by a Si-type TFT formed on a substrate, and a field-effect mobility of 100 cm ⁇ / Vs or more.
  • necessary and sufficient high-speed control can be performed. Therefore, with the above configuration, an array substrate for a liquid crystal display device capable of displaying moving images with high definition can be provided at low cost.
  • a twenty-second aspect according to a fifth invention group is the poly-Si type TFT according to the twenty-first aspect, wherein the pixel switch TFT has a field-effect mobility of 1 to 25 cm ′ / V ⁇ s.
  • a TFT is used, and an M0S transistor having a field-effect mobility of 100 cm ! / Vs or more is used as the driving element.
  • the MOS transistor is retrofitted on the transparent substrate.
  • a poly-Si TFT with a field-effect mobility of 1 to 25 cm 2 / V-s is sufficient to turn on and off the light transmission, and the field-effect mobility is 100 cm 2 / V
  • a MOS transistor of .s or more is retrofitted as a driving element, a TFT array substrate for a liquid crystal display device capable of high-frequency driving can be constructed, taking full advantage of the performance of the MOS transistor.
  • At least a first comb pixel electrode, a pixel switch TFT for switching the first comb pixel electrode, and a pixel switch TFT are provided.
  • a second comb-shaped pixel electrode disposed opposite to the first comb-shaped pixel electrode on the substrate.
  • a poly-Si TFT having a field effect mobility of l to 25 cm ! / Vs is used as the TFT for the pixel switch, and the field effect mobility is used as the driving element.
  • a poly-Si TFT having a degree of 100 cm / Vs or more is used, and the poly-Si TFT and the first and second comb-shaped pixel electrodes are formed on the substrate. It is characterized in that
  • a TFT array substrate for a liquid crystal display device that can be driven at a high frequency can be configured, and this substrate has little angle dependence in display.
  • a twenty-fourth aspect according to a sixth invention group is the poly-Si type having a field-effect mobility of 1 to 25 cm / Vs as the pixel switch TFT in the second aspect.
  • TFT is used, and as the driving element, A MOS transistor having a field-effect mobility of 100 cm 2 / V ⁇ s or more is used, and the MOS transistor is retrofitted to the substrate.
  • the poly-Si TFT for the pixel switch is an n-channel TFT, and
  • the field-effect mobility is 5 to 25 cm 1 / V ⁇ s.
  • the n-channel type TFT has a high field-effect mobility, and a poly-Si type TFT having a field-effect mobility set to 5 to 25 cm ! / V-s is used as an element for a pixel switch.
  • a TFT array for liquid crystal display devices with sufficient high-speed response can be constructed.
  • the opposing electrode (common electrode) formed on the second substrate is composed of a reflective film mainly composed of metal A1, and a color filter is formed on the surface of the opposing electrode to form a reflective electrode. It can be used as a color liquid crystal display device.
  • a color filter is first formed on the second substrate, and a counter electrode is formed with a transparent conductive film thereon, a transmission type color liquid crystal display device can be obtained.
  • FIG. 1 is a sectional view showing a procedure for manufacturing a poly-Si type TFT according to the present invention.
  • FIG. 2 is a conceptual diagram illustrating the structure of a thin film forming apparatus using a pressure gradient plasma gun.
  • FIG. 3 is a conceptual diagram for explaining the structure of another thin film forming apparatus using a pressure gradient plasma gun.
  • FIG. 4 is a plan view schematically showing a TFT array substrate.
  • FIG. 5 is a cross-sectional view schematically showing a liquid crystal display device according to the present invention.
  • ⁇ FIG. 6 is a cross-sectional view schematically showing a comb-shaped pixel electrode.
  • FIG. 7 is a cross-sectional view showing a manufacturing procedure of a low-temperature process po-Si type TFT according to a conventional technique.
  • BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described focusing on a method of forming a polysilicon layer on a substrate.
  • a silicon layer is formed at the stage where silicon particles are deposited on a substrate by using silicon particles that are excited and ionized by adding energy.
  • the most important feature is that it is With this method, there is no need to raise the substrate temperature when forming the polysilicon layer, and in each of the following examples, an inexpensive glass substrate having a heat resistance of 600 ° C. or less is used.
  • the present invention does not exclude the use of a quartz substrate that withstands a temperature exceeding 600 ° C. instead of such a glass substrate.
  • FIG. 1 is a cross-sectional view schematically showing a cross section of the substrate in each step.
  • 101 is a glass substrate
  • 102 is No.
  • buffer layer
  • 104 is a polysilicon layer
  • 105 is a gate insulating layer
  • 106 is a gate electrode
  • 107 is a source region
  • 108 is a gate region.
  • the drain region, 109 indicates a contact hole
  • 110 indicates a source electrode
  • a SiO 2 layer having a thickness of, for example, 500 OA is formed as a buffer layer 102 on a glass substrate 101.
  • a polysilicon layer 104 is formed on this buffer layer 102 by using a pressure gradient plasma gun described later (FIG. 1 (a)). The details of the method of forming the polysilicon layer 104 will be described later.
  • the polysilicon layer 104 is etched using a photolithography method to form a pattern of a predetermined shape, and then the pattern-like polysilicon layer 104, A gate insulating layer 105 of, for example, SiO.sub.i having a thickness of 150 A is formed thereon. Further, on the gate insulating layer 105, a gate electrode 106 made of, for example, 600 O Mo is formed. Then, using this gate electrode 106 as a mask, for example, a line ion is implanted into the polysilicon layer 104 (FIG. 1B).
  • the gate insulating layer 105 is etched to form contact holes 109 and 109 reaching the source region 107 and the drain region 108, respectively, and these contact holes are formed.
  • the source electrode 110 and the drain electrode 111 are formed by embedding A1 having a thickness of 300 A in 109.
  • the manufacturing procedure of only one TFT (thin film transistor) is shown, but the poly-Si type TFT array substrate has Many TFTs manufactured by the same method have been formed. Further, in the poly-Si type TFT array substrate according to the first embodiment, the poly-Si type TFT is formed not only as a pixel part but also as a peripheral driving circuit. A gate, a line, and a source bus line that connect to the switch TFT are formed. Further, a pixel electrode made of, for example, indium tin oxide is formed on the drain electrode 111.
  • a driving circuit section composed of a pixel section 4 13 and a gate driving circuit section 4 14 and a source driving circuit section 4 15 on a single glass substrate 4 12 are provided.
  • a large number of pixels are formed in a matrix in the pixel section 413, and a TFT for pixel switching for switching these pixels is provided for each pixel. The number is formed corresponding to the number of pixels.
  • a gate drive TFT and a source drive TFT for driving the pixel switch TFT are formed in the gate drive circuit section 4 14 and the source drive circuit section 4 15. .
  • Example 1 the polysilicon layer was formed using a thin film forming apparatus shown in FIG. 2 incorporating a pressure gradient plasma gun manufactured by Sumitomo Heavy Industries, Ltd.
  • This device belongs to the category of the ion plating method and has been newly developed.
  • FIG. 2 is a conceptual diagram for explaining a thin film forming apparatus.
  • reference numeral 2 12 denotes a vacuum vessel which is a main body of the apparatus
  • reference numeral 2 17 denotes a glass substrate for depositing polysilicon
  • reference numeral 2 18 denotes a mounting table on which a glass substrate 2 17 is placed
  • 219 is the evaporation source for forming the polysilicon layer-In this example, a polysilicon cone is used.
  • 222 indicates silicon ions that are excited and ionized.
  • Reference numeral 220 denotes a pressure gradient plasma gun as a means for generating excited ionized particles constituting a main part of this apparatus.
  • This pressure gradient plasma gun 220 includes an evaporative particle generation unit 2. 2 3 and a plasma region 2 2 1. Then, in the apparatus of the first embodiment, the evaporating particle generator 22 3 causes the thermal energy of the DC arc discharge to act on the evaporating source 2 19 to evaporate the silicon particles. In the plasma region 221, the Ar gas is excited to form a high-density plasma atmosphere.
  • This device guides the silicon particles generated in the evaporating particle generation section 22 to the plasma area section 221, where they are excited and ionized, and then on the mounting table 2 18 It is designed to irradiate the glass substrate 217 installed in the room.
  • the ionized silicon particles are irradiated on the glass substrate 217, the silicon particles are deposited on the substrate, and the polycrystallization proceeds simultaneously with the deposition process. .
  • the Si0 2 (No. 5) layer of 50,000 A in advance As a specific condition for forming the polysilicon layer, as a glass substrate 217, an undercoat was made on the Si0 2 (No. 5) layer of 50,000 A in advance. A borosilicate glass substrate was used. The degree of vacuum of the vacuum vessel 2 16 was set to 3 ⁇ 10 -4 Torr, and the discharge current of the pressure gradient plasma gun 220 was set to about 10 OA. Then, while heating the glass substrate 217 placed on the mounting table 218 to 200 ° C. under these conditions, the excited and ionized silicon particles 222 are scattered. The substrate 21 was irradiated for 20 seconds. As a result, a polysilicon layer of about 100 OA was formed on the glass substrate 21. Therefore, the steps shown in FIGS. 1 (b) to (d) were performed on this polysilicon layer to produce an n-channel type poly-Si type TFT array substrate.
  • the field-effect mobility was 5 cm 2 / V ⁇ s. This value is about 10 times the field-effect mobility of amorphous silicon, and is used as a switching element for an active matrix liquid crystal display device. It has sufficient performance for practical use.
  • the silicon particles excited and ionized by the pressure gradient plasma gun have high energy. Therefore, most of them reach the glass substrate in a sufficiently ionized state and retain energy after that, so that they move in the sedimentary layer to a stable point where the energy state becomes more stable (migration) ). For this reason, when the deposited layer is crystallized at the stage when the silicon particles are deposited on the substrate, and when microscopic defects are generated in the crystal during the progress of the crystallization, the defect is The silicon particles move to eliminate defects and form aggregates of crystal grains with few crystal defects. In addition, the migration forms a polysilicon layer with higher density. A polysilicon layer made of crystal grains having excellent density and few crystal defects has excellent electric field effect mobility.
  • the present inventors can form a polysilicon thin film composed of crystal grains of 500 to 700 nm by the manufacturing method of Example 1 and use this polysilicon thin film to obtain n —When you make a channel TFT, 5 ⁇ 2 5 cm 1 / V . Field-effect mobility of the s are sure that can be realized.
  • the evaporation area can be increased, and the evaporation area can be increased. This makes it possible to irradiate the excited and ionized silicon particles onto the glass substrate from various directions. Therefore, according to the manufacturing method of the present invention, a polysilicon layer having excellent uniformity can be formed.
  • a silicon layer is formed simultaneously with the deposition of silicon particles on a substrate. Therefore, unlike the conventional method, it is not necessary to recrystallize after forming a silicon layer (amorphous layer) once, so that productivity is improved accordingly.
  • the method of irradiating and depositing the evaporated silicon particles can form a uniform polysilicon layer, so that a large-screen, high-definition liquid crystal display device can be manufactured at a low cost.
  • the glass substrate 217 is arranged outside the plasma region 221, but in such an apparatus, the glass substrate 217 is not provided. Since the plasma particles (Ar> particles) do not collide, there is no increase in the substrate temperature due to the collision of the plasma particles. In other words, by using the thin film forming apparatus shown in FIG. 2, a polysilicon layer can be formed at a low substrate temperature. Therefore, an inexpensive glass substrate can be used. The present inventors have confirmed that a polysilicon layer can be formed even at a substrate temperature of 100 ° C. or lower.
  • the peripheral driving circuit is also formed of the po1y-Si type TFT, but in the second embodiment, a driving circuit is formed instead of the peripheral driving circuit formed of the po1y-Si type TFT.
  • a poly-Si type TF array substrate for a liquid crystal display device was fabricated by attaching an IC chip to the substrate. Elements other than the peripheral driving circuit are the same as those in the first embodiment. Note that the term “post-installation” in this specification refers to incorporating a separately manufactured element into a substrate.
  • the field-effect mobility of the poly-Si TFT for pixel switch formed in Example 2 was 5 cm 2 / V ⁇ s. This mobility is about 10 times that of an amorphous TFT.
  • the IC chip used in this example has an M0S transistor formed on a single-crystal silicon layer, and is compatible with the above-mentioned poly-Si type TFT for pixel switch. It has a much faster drive speed than the ones in comparison. Therefore, the substrate of Example 2 in which a poly-Si TFT having sufficient performance as a pixel switch element and an IC chip were combined was compared with an amorphous TFT array substrate. However, it has become possible to obtain extremely high-definition images.
  • Example 3 the liquid crystal display device shown in FIG. 5 was manufactured using the poly-Si type TFT array substrate manufactured in Example 1.
  • FIG. 5 is a schematic cross-sectional view of the liquid crystal display device according to the third embodiment.
  • 501 is a first substrate manufactured using the poly-Si type TFT array substrate manufactured in the first embodiment. is there.
  • the first substrate 501 has a matrix-shaped pixel electrode group 502 formed by the method described in Embodiment 1 and a TFT group 502 for driving these pixel electrodes. 3, and a liquid crystal alignment film 504 is formed on the pixel electrode group 502.
  • reference numeral 505 denotes a second substrate opposed to the first substrate 501, and the second substrate 505 is provided with a G (green) on a separately prepared transparent glass substrate.
  • B bullet
  • R red
  • a color filter group 506, a counter electrode (common electrode) 507 and a liquid crystal alignment film 508. I have.
  • the first substrate and the second substrate have their liquid crystal alignment films opposed to each other so that the alignment direction of the liquid crystal is twisted 90 degrees, and a gap between the two substrates is provided. They are overlaid with a gap of about 5 micron with 10 and adhesive 511 interposed. Twisted nematic liquid crystal (ZLI4792; manufactured by Merck) 509 is sealed in the above-mentioned gap, and furthermore, polarizing plates 512, 5 It has a structure with 13 arranged.
  • the IPS (ex. In-plane-switching) type poly-Si type TFT array substrates were fabricated. Further, a known liquid crystal alignment film was formed on the surface of the substrate. This substrate is referred to as a first substrate.
  • a liquid crystal alignment film similar to the above was formed on a separately prepared transparent glass substrate, and this was used as a second substrate.
  • the first substrate and the second substrate are overlapped with any gap with the liquid crystal alignment film inside, and the nematic liquid crystal is sealed in the gap to produce an IPS liquid crystal display. did.
  • a TFT array substrate for a liquid crystal display device was manufactured in the same manner as in Example 1 except that the thin film forming apparatus shown in FIG. 3 was used instead of the apparatus shown in FIG.
  • the apparatus shown in FIG. 3 uses a pressure gradient plasma gun (manufactured by Sumitomo Heavy Industries, Ltd.) as in FIG. 2, and in FIG. 3, reference numeral 32 3 denotes a vacuum vessel and reference numeral 32 4 denotes a poly.
  • a glass substrate on which a silicon layer is deposited 325 is a mounting table on which the glass substrate 324 is set, 328 is a voltage applying means, 330 is a glass substrate 324 and a plasma region 3 It is an insulator for electrically separating 29 from the other.
  • 32 6 is a silicon evaporation source (here, a silicon tablet is used), which is a raw material of the polysilicon layer, and 33 1 is excited and ionized. It is a silicon particle.
  • Reference numeral 327 denotes a pressure gradient type plasma gun used for evaporating the evaporation source 326 and exciting the evaporated silicon particles by plasma.
  • the pressure gradient type plasma gun 327 has an evaporating particle generating section 332 and a plasma region section 229.
  • the evaporating particle generating section 33 The thermal energy of the DC arc discharge acts on the silicon particles to evaporate the silicon particles.In the plasma region 329, Ar gas is excited and the high-density plasma atmosphere is excited. Are formed.
  • the evaporating particle generating section 332 is arranged between the plasma area section 329 and the substrate 324.
  • the glass substrate 324 is placed in a direction (downward) different from the evaporation direction of silicon particles (the plasma region side). Therefore, in the device having this structure, the silicon particles generated in the evaporating particle generating section 332 first evaporate in the direction opposite to the substrate 324 and enter the plasma area section 329. After being excited and ionized here, the substrate 324 is irradiated by the action of the electric field applied by the voltage applying means 328.
  • Example 6 is different from Example 6 in that a step of forming a polysilicon layer on a substrate and then selectively heating and recrystallizing only a specific region of the polysilicon layer was added.
  • a polySi TFT array substrate was manufactured in the same manner as in Example 1 except for the above.
  • a polysilicon layer is formed on a transparent glass substrate, and then an excimer laser is applied to a polysilicon region where a peripheral drive circuit is to be formed. Irradiate light (anneal treatment) to the area Only recrystallized. Is the irradiation conditions of the excimer laser first light for the recrystallization, were irradiated with 3 5 0 m J / cm J excimer, single The first light of. Note that items other than the selective heating process (specific region heating step) are the same as those in the first embodiment, and a description thereof will be omitted.
  • the field-effect mobility of the region (pixel region) not subjected to the heat treatment is ⁇ ⁇ / V ⁇ S, and the field-effect mobility of the region (drive circuit portion) subjected to the heat treatment.
  • a gate insulating film is formed on the polysilicon layer prepared above, a p-type or n-type impurity is diffused to form a source / drain region, and then a metal thin film is deposited.
  • a gate electrode and a gate bus line were formed, an interlayer insulating film was formed, and then a thin metal film was deposited again to form a source electrode and a source pass line.
  • a TFT group for the pixel switch and a driving TFT group for driving the TFT for the pixel switch are formed on the substrate, and a transparent pixel electrode group is formed on the substrate to form the TFT group for the liquid crystal display device. It became a ray board.
  • a known liquid crystal alignment film was formed on the surface of the pixel electrode group of the TFT array substrate for a liquid crystal display device, and this was used as a first substrate.
  • a counter electrode was formed on a transparent glass substrate prepared separately, and a liquid crystal alignment film was formed thereon to form a second substrate.
  • the liquid crystal display of Example 3 is obtained by a method in which the first substrate and the second substrate are overlapped with a fixed cap with the liquid crystal alignment film on the inside, and the liquid crystal is sealed in the gear. The device was completed.
  • the peripheral drive circuit section refers to a circuit for controlling and driving a TFT for a pixel switch, and specifically, a gate drive circuit section 4 14 shown in FIG. Refers to the circuit section 415.
  • an excimer laser beam of 300 to 450 mJ / cm ! May be generally used for the heat treatment on the planned area of the peripheral drive circuit section. It has been confirmed that the field effect mobility of the peripheral drive circuit can be increased to 100 to 500 cm ! / V ⁇ s by irradiation with one laser beam.
  • the transparent pixel electrode of the first substrate in the sixth embodiment is a pair of first and second comb-shaped pixel electrodes as shown in FIG. 6, and the transparent substrate is provided on the second substrate facing the first substrate.
  • An IPS (inplain switching) liquid crystal display device in which liquid crystal molecules were rotated by an in-plane horizontal electric field was manufactured in the same manner as in Example 6 except that the counter electrode was not formed.
  • the first pixel electrode and the second pixel electrode are formed separately, and then the liquid crystal alignment film is formed. Was formed.
  • Example 8 is characterized in that not only the polysilicon layer but also the gate insulating layer were formed using a thin film forming apparatus using a pressure gradient plasma gun, and other features were described. Is the same as in the first embodiment. That is, the method of manufacturing the thin film transistor of the eighth embodiment is the same as that of the first embodiment with respect to the steps (a), (c), and (d) of FIG. Only the steps of are different.
  • a thin film forming apparatus having the same structure as that of FIG. A solid SiN or Si0 having the same material composition as in Example 5 was placed, and the other conditions were the same as the thin film forming conditions in Example 1, and the silicon was placed on the substrate. An oxide film layer was formed.
  • the same material as the constituent material of the gate insulating layer is used as the evaporation source, and this material is excited to deposit on the polysilicon layer.
  • formation can be, for example, S i 0, it is the this to N ss (the interface state density) to 1 0 12 / cm! or less in the case of a film. Therefore, according to the present embodiment, dehydration treatment for removing impurities is unnecessary.
  • SiO 2 As a gate insulating layer, a silane-based gas is used or TEOS is used.
  • Si 3 N 4 and Sioi can be efficiently evaporated over a large area, similarly to the case of forming a polysilicon layer.
  • a uniform and dense gate insulating layer can be formed.
  • the polysilicon layer which is the active layer of the TFT, is exposed to the air.
  • a gate insulating layer can be continuously formed on a polysilicon layer. Therefore, the policy Contamination at the interface between the silicon layer and the gate insulating layer can be prevented, and as a result, the variation in Vt characteristics of each TFT can be significantly reduced.
  • the amorphous silicon can be obtained without performing laser annealing.
  • a polysilicon layer having a field-effect mobility about 2 to 50 times higher than that of silicon can be formed.
  • the polysilicon layer formed by this method has high in-plane uniformity and maintains high uniformity even in a large area. Therefore, the poly-Si type TFT array substrate for a liquid crystal display device using such a polysilicon layer according to the present invention can provide a high-definition display, and furthermore, has an electric field effect. Since the mobility is uniform in the plane, a high-quality image with little display unevenness can be obtained even when the screen is enlarged. Therefore, the present invention is an extremely useful technique for increasing the screen size and definition of a liquid crystal display device, and the industrial significance of the present invention is great.

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Abstract

L'invention concerne un substrat de groupements de transistors à couches minces (TFT) en poly-Si, produit à l'aide d'un procédé dans lequel une couche de polysilicium de grande surface et de qualité élevée est formée au cours d'un procédé basse température sans recuit laser. Le substrat entraîne la formation de petites irrégularités d'écran même si l'écran est grand et de haute définition. Le procédé de production d'un tel substrat de groupements TFT pour écran à cristaux liquides comporte un procédé de fabrication de TFT en poly-Si constitués d'une couche de semi-conducteur en polysilicium dans des zones de canal, et comporte en outre l'étape qui consiste à former la couche de polysilicium en laissant des particules de silicium excitées par un apport d'énergie préalable frapper le substrat et déposer des particules de silicium sur le substrat.
PCT/JP1999/001646 1998-03-31 1999-03-30 Substrat de groupements tft pour ecran a cristaux liquides et son procede de production, et ecran a cristaux liquides et son procede de production WO1999052013A1 (fr)

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US09/647,397 US6472297B1 (en) 1998-03-31 1999-03-30 Method of producing TFT array substrate for liquid crystal display device
EP99909351A EP1069465A1 (fr) 1998-03-31 1999-03-30 Substrat de groupements tft pour ecran a cristaux liquides et son procede de production, et ecran a cristaux liquides et son procede de production
KR1020007010478A KR20010071123A (ko) 1998-03-31 1999-03-30 액정표시장치용 ｔｆｔ 어레이기판과 그 제조방법 및그것을 이용한 액정표시장치와 그 제조방법

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JP8572698A JP3288968B2 (ja) 1998-03-31 1998-03-31 薄膜トランジスタの製造方法およびそれを用いた液晶表示装置の製造方法
JP8569998A JPH11282013A (ja) 1998-03-31 1998-03-31 液晶表示装置用ｔｆｔアレイとその製造方法およびそれを用いた液晶表示装置とその製造方法
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JP3872363B2 (ja) * 2002-03-12 2007-01-24 京セラ株式会社 Ｃａｔ−ＰＥＣＶＤ法
TWI302625B (en) 2003-06-26 2008-11-01 Au Optronics Corp Polysilicon thin film transistor liquid crystal display having a plurality of common voltage drivers
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US7184106B2 (en) * 2004-02-26 2007-02-27 Au Optronics Corporation Dielectric reflector for amorphous silicon crystallization
TWI393942B (zh) * 2008-10-01 2013-04-21 Chunghwa Picture Tubes Ltd 主動元件陣列基板
CN103700665B (zh) * 2013-12-13 2016-03-02 京东方科技集团股份有限公司 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208823A (ja) * 1984-04-02 1985-10-21 Matsushita Electric Ind Co Ltd 薄膜の製造方法
JPS63219123A (ja) * 1987-03-09 1988-09-12 Nippon Telegr & Teleph Corp <Ntt> 薄膜トランジスタの製造方法
JPH04318973A (ja) * 1991-04-17 1992-11-10 Seiko Epson Corp 薄膜トランジスタ及びその製造方法
JPH0584180A (ja) * 1991-09-25 1993-04-06 Mitsubishi Electric Home Appliance Co Ltd 電気掃除機用床ブラシ
JPH06175103A (ja) * 1992-12-10 1994-06-24 Sharp Corp アクティブマトリクス表示装置
JPH07335900A (ja) * 1994-06-09 1995-12-22 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH09105908A (ja) * 1995-10-09 1997-04-22 Hitachi Ltd アクティブマトリクス型液晶表示装置
JPH09237762A (ja) * 1995-12-28 1997-09-09 Stanley Electric Co Ltd シリコン薄膜の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584180A (ja) 1981-06-30 1983-01-11 セイコーエプソン株式会社 アクテイブマトリクス基板
JPH07147245A (ja) * 1993-11-24 1995-06-06 Asahi Glass Co Ltd 結晶質シリコン薄膜の形成方法
JP2908692B2 (ja) 1994-03-07 1999-06-21 株式会社日立製作所 伝票受付端末システム
JPH07335906A (ja) * 1994-06-14 1995-12-22 Semiconductor Energy Lab Co Ltd 薄膜状半導体装置およびその作製方法
JP3715996B2 (ja) * 1994-07-29 2005-11-16 株式会社日立製作所 液晶表示装置
JPH0864824A (ja) * 1994-08-24 1996-03-08 Toshiba Corp 薄膜トランジスタおよびその製造方法
US5618758A (en) * 1995-02-17 1997-04-08 Sharp Kabushiki Kaisha Method for forming a thin semiconductor film and a plasma CVD apparatus to be used in the method
US5980999A (en) * 1995-08-24 1999-11-09 Nagoya University Method of manufacturing thin film and method for performing precise working by radical control and apparatus for carrying out such methods
KR100381865B1 (ko) * 1995-12-29 2003-07-18 삼성전자주식회사 액정표시장치용박막트랜지스터기판의제조방법
JP2697730B2 (ja) * 1996-09-10 1998-01-14 セイコーエプソン株式会社 アクティブマトリクス基板の製造方法
US5950078A (en) * 1997-09-19 1999-09-07 Sharp Laboratories Of America, Inc. Rapid thermal annealing with absorptive layers for thin film transistors on transparent substrates

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60208823A (ja) * 1984-04-02 1985-10-21 Matsushita Electric Ind Co Ltd 薄膜の製造方法
JPS63219123A (ja) * 1987-03-09 1988-09-12 Nippon Telegr & Teleph Corp <Ntt> 薄膜トランジスタの製造方法
JPH04318973A (ja) * 1991-04-17 1992-11-10 Seiko Epson Corp 薄膜トランジスタ及びその製造方法
JPH0584180A (ja) * 1991-09-25 1993-04-06 Mitsubishi Electric Home Appliance Co Ltd 電気掃除機用床ブラシ
JPH06175103A (ja) * 1992-12-10 1994-06-24 Sharp Corp アクティブマトリクス表示装置
JPH07335900A (ja) * 1994-06-09 1995-12-22 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH09105908A (ja) * 1995-10-09 1997-04-22 Hitachi Ltd アクティブマトリクス型液晶表示装置
JPH09237762A (ja) * 1995-12-28 1997-09-09 Stanley Electric Co Ltd シリコン薄膜の製造方法

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