WO1999023696A1 - Dispositif a semi-conducteur et son procede de fabrication - Google Patents
Dispositif a semi-conducteur et son procede de fabrication Download PDFInfo
- Publication number
- WO1999023696A1 WO1999023696A1 PCT/JP1997/003969 JP9703969W WO9923696A1 WO 1999023696 A1 WO1999023696 A1 WO 1999023696A1 JP 9703969 W JP9703969 W JP 9703969W WO 9923696 A1 WO9923696 A1 WO 9923696A1
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- semiconductor device
- wiring
- chip
- elastomer layer
- elastomer
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Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technology effective when applied to a chip size package (CSP) type semiconductor device in which a semiconductor chip is mounted on a substrate via bump electrodes.
- CSP chip size package
- a BGA (Ball Grid Array) type LSI package in which a semiconductor chip is flip-chip mounted on a substrate using ball-shaped bump electrodes mounted on electrodes (pads), is easy to increase the number of pins and has a small mounting area. Therefore, it is increasingly used not only as a package for mounting a logic LSI with a large number of lZO (Input / Output) pins, but also as a package for mounting a memory LSI.
- lZO Input / Output
- the BGA described in U.S. Pat. No. 5,216,278 is wire-bonded on a plastic package substrate having a bump electrode made of Pb—Sn alloy solder on the back surface. It has a package structure in which a chip is mounted by a method and the chip is sealed with a mold resin.
- the BGA has a structure in which dissimilar members with different coefficients of thermal expansion, such as a semiconductor chip made of single-crystal silicon, a package substrate made of plastic (or ceramic), and a bump electrode made of Pb—Sn alloy solder, are joined. Has become. Therefore, if the semiconductor chip repeats the temperature cycle of heating and cooling after mounting the BGA on the printed wiring board, stress will be concentrated on the bump electrodes due to the difference in the thermal expansion coefficient of each member, and the bump life will be shortened. Shorter lengths reduce the reliability of electrical connection and, in some cases, may cause bump electrode destruction.
- each member should be made of a material with a similar thermal expansion coefficient, or a member that relaxes and absorbs stress applied to the bump electrode should be interposed in the gap between the chip and the substrate. Is required.
- Japanese Patent Application Laid-Open No. H08-102446 discloses a method in which bump electrodes are formed in a grid pattern in each chip region of a semiconductor wafer, and thereafter, the wafer is divided into a large number of chips.
- this method first, wiring connected to pads formed on the periphery of each chip area of the wafer is routed inside the chip area, and then the entire surface of the wafer is covered with a cover coat made of polyimide or the like. The coat is opened in a grid pattern to expose the wiring, and a bump electrode is formed thereon. After that, the wafer is diced along the scribe line and divided into many chips. According to such a manufacturing method, the operation of arranging the bump electrodes in a lattice pattern inside the chip is performed by a wafer process, so that a large number of chips having the bump electrodes formed thereon can be produced.
- Japanese Unexamined Patent Publication (Kokai) No. 1-2383843 discloses that a thermoplastic resin (for example, polymethyl methacrylate), which relieves stress applied to a bump electrode, is applied to the surface of a wafer (excluding a region where a bump electrode is formed). It discloses a method of coating and then dicing the wafer to divide it into many chips. According to this method, it is easier to repair the chip after mounting than in a method in which a chip is mounted on a substrate via bump electrodes and then a gap is filled with a resin, and the chip and the substrate are connected to each other. There is also an advantage that no air bubbles remain in the gaps.
- a thermoplastic resin for example, polymethyl methacrylate
- Japanese Patent Application Laid-Open No. Hei 4-284048 describes that a chip and a substrate are sealed by sealing the chip with a rubber-like elastic body having projections on its surface (for example, silicone rubber having an elastic modulus of 10 OMPa or less).
- a rubber-like elastic body having projections on its surface for example, silicone rubber having an elastic modulus of 10 OMPa or less.
- an LSI package that absorbs and reduces the stress caused by the difference in thermal expansion coefficient with a rubber-like elastic material.
- On the surface of the rubber-like elastic body one end is connected to the pad of the chip, and the other end is formed with wiring extending to the surface of the protrusion. When mounting this package on a board, the wiring on the surface of the protrusion is soldered to the electrode on the board.
- H08-111114 discloses a low-elasticity elastomer (for example, for reducing stress caused by a difference in thermal expansion coefficient between a chip and a substrate) between a chip and a bump electrode. It discloses a BGA type package in which a siloxane polymer having a glass transition temperature of 150 ° C or lower is interposed. The elastomer is adhered to the surface of the chip with an adhesive, and the pads of the chip and the bump electrodes are electrically connected via a conductive wire embedded in the elastomer.
- Nikkei Micro Devices (p92-p98), published by Nikkei BP (October 19, 1996), has an elastic resin layer and a polyimide substrate layer laminated on the surface of a wafer and provided on the polyimide substrate layer. It discloses a method (wafer level packaging) for manufacturing a large number of chip size packages (CSP) by dicing the wafer after connecting bump electrodes on the Cu wiring. The pads on the wafer and the wiring on the polyimide substrate layer are electrically connected via leads or bonding wires embedded in the elastic resin layer on the chip surface.
- CSP chip size packages
- Japanese Patent Application Laid-Open No. Hei 2-7717138 discloses that a thin spiral wiring (called a micro lead) having a panel property or a free deformability in all directions, horizontal and vertical, is used to connect a bump electrode of a chip to a bump electrode. It discloses a technique for reducing the stress applied to the bump electrode by connecting the electrode to the substrate.
- the microlead is formed by laminating a plurality of different kinds of metal films on a substrate by a sputtering method, etching these metal films and spirally patterning them, and then lifting off the lowermost metal film.
- 5,476,211 discloses that a loop-shaped projection is formed by bonding both ends of a wire on the same pad of a chip, and a semiconductor chip is mounted on a substrate via the projection. Disclosure technology. In another aspect of the publication, after one end of the wire is bonded onto a chip pad, the entire wire is formed into an S-shape or linear shape, and the other end is connected to a substrate. I have. Japanese Patent Application Laid-Open No. 63-1777743 discloses that a bump electrode formed on a chip pad and a substrate are collectively formed on an insulating sheet, and the height is less than a minimum lateral dimension. A mounting structure in which a spiral conductive panel is inserted is disclosed.
- This conductive panel is formed by etching a Cu alloy or the like on a thin plate adhered to an insulating sheet made of polyimide or the like, and one end thereof is fixed on the insulating sheet. According to this mounting structure, When multiple chips are mounted on the same board, even if the board is warped, the height of the back of each chip can be aligned, so when the cooling plate is placed on the back of the chip, The chip can be brought into close contact with the cooling plate.
- Japanese Patent Application Laid-Open No. 9-112772 discloses that the back and side surfaces of a chip are used as a part of a package, and a passivation film covering the element forming surface of the chip is used as a part of the package. Also disclosed is a chip scale package in which the step of assembling a package after dividing a wafer into chips is reduced. To manufacture this package, for example, each chip area of the wafer is covered with a two-layer passivation film, and electrodes for connecting bump electrodes are arranged in a grid on the chip area. Each electrode is electrically connected to a corresponding pad via a through hole formed by opening the upper passivation film and a wiring formed on the lower passivation film. The wafer is subjected to functional testing and burn-in testing in this state, and is then divided into many chips by dicing. Then, bump electrodes are connected to the electrodes of each chip.
- Japanese Patent Application Laid-Open No. Hei 8-250498 discloses that a bump electrode is formed on a predetermined position of a wiring drawn from a pad in order to form a bump electrode without being limited by the position of the pad and the interval between the bump electrodes.
- the surface of the wiring drawn out from the pad is covered with an interlayer insulating layer such as a photosensitive polyimide, and a bump electrode is formed via a conductor layer above the wiring exposed through the opening formed in the interlayer insulating layer. Is done.
- the bump electrode can be formed at an arbitrary height, so that the thermal fatigue of the bump electrode caused by the difference in the coefficient of thermal expansion between the chip and the substrate can be suppressed, and the life of the bump electrode can be extended.
- the present inventor has conducted various studies on a conventional semiconductor device in which a semiconductor chip is flip-chip mounted on a substrate using the above-described bump electrodes and a method for manufacturing the same. As a result, a new CSP structure with a structure that can effectively reduce and absorb the stress concentrated on the bump electrode and a method of manufacturing the same at low cost have been found.
- An object of the present invention is to provide a structure capable of effectively relaxing and absorbing stress that is concentrated on a bump electrode, which is a joint between the semiconductor chip and the substrate, due to a difference in thermal expansion coefficient between the semiconductor chip and the substrate.
- An object of the present invention is to provide a CSP type semiconductor device and a technique for manufacturing the same at low cost.
- a low-elasticity elastomer is formed on the main surface of the chip for relaxing and absorbing the stress concentrated on the bump electrode, and the wiring connected to the pad is formed through a through-hole opened in the elastomer. It is pulled out to the upper surface and connected to one end with a bump electrode.
- the wiring drawn out on the upper surface of the elastomer is formed in a curved pattern, and the stress concentrated on the bump electrode is absorbed and alleviated by the elastic deformation of the elastomer and the expansion and contraction of the wiring. It is like that.
- the process up to the connection of the bump electrode to the wiring is performed in a wafer process. In this state, testing such as burn-in is performed, and then the wafer is diced and divided into chips. This eliminates the need for the package assembly process.
- the semiconductor device of the present invention has an elastomer layer formed over a plurality of semiconductor elements and bonding pads formed in a plurality of chip regions on a main surface of a semiconductor wafer, and one end is opened in the elastomer layer.
- the bump electrode is electrically connected to the bonding pad through the through hole, and the other end is connected to a wiring disposed above the elastomer layer.
- the semiconductor device of the present invention is a semiconductor device of a chip size package type comprising semiconductor chips obtained by dividing a chip region of the semiconductor wafer.
- a protective layer is formed on a side surface of the semiconductor chip.
- the semiconductor device according to the present invention wherein the wiring is bonded to an upper portion of the elastomer layer.
- the wiring and the bonding pad are formed on one surface of an insulating tape, and are electrically connected to each other through an Au bump bonded on the bonding pad. 5.
- a plurality of stages of Au bumps are bonded on the bonding pads.
- the Au bump is sealed with a resin filled in a through hole of the elastomer layer.
- the semiconductor device of the present invention comprises a photosensitive resist in which the elastomer layer is applied on the main surface of the semiconductor wafer, or a photosensitive film adhered on the main surface of the semiconductor wafer.
- the elastic modulus of the elastomer layer is 1 to 500 OMPa.
- the elastic modulus of the elastomer layer is 1 to 100 OMPa.
- the elastic modulus of the elastomer layer is about 1 to 50 OMPa.
- the thickness of the elastomer layer is 0.005 to 0.15 mm.
- the thickness of the elastomer layer is 0.01 to 0.1.
- the interval between the bump electrodes is wider than the interval between the bonding pads.
- unevenness is provided on the surface of the elastomer layer.
- a slit is provided in the elastomer layer near the bump electrode.
- At least a part of the wiring arranged above the elastomer layer is formed in a curved pattern.
- at least a part of the wiring arranged above the elastomer layer is composed of a plurality of wirings.
- the method for manufacturing a semiconductor device according to the present invention includes the following steps.
- the method for manufacturing a semiconductor device of the present invention includes the following steps.
- the method for manufacturing a semiconductor device of the present invention includes a step of dicing a chip area of the semiconductor wafer to divide the chip area into semiconductor chips. 23.
- the plurality of chip regions are converted into non-defective products and defective products by performing testing prior to the step of dicing the chip regions into semiconductor chips. Including the step of sorting.
- a method of manufacturing a semiconductor device comprising the steps of: forming a fuse with at least a part of a wiring disposed above the elastomer layer; and cutting a fuse in a chip area determined to be defective by the testing. Contains.
- the method for manufacturing a semiconductor device according to the present invention includes a step of forming a slit on the main surface or the back surface of the semiconductor wafer at the boundary of the chip region, and forming a protective layer inside the slit. I have.
- the method for manufacturing a semiconductor device of the present invention includes the following steps.
- the elastomer layer is formed of a photosensitive film, and the through-hole is formed by photolithography and etching.
- the method for manufacturing a semiconductor device according to the present invention further comprising: a step of forming the conductor layer; (d) a step of forming a metal layer on the entire surface of the elastomer layer including the inside of the through hole; and a step of patterning the metal layer. And forming a wiring layer.
- FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention
- FIG. 2 is a cross-sectional view of the semiconductor device
- FIG. 3 is a cross-sectional view of the semiconductor device mounted on a substrate
- FIG. 5 is a perspective view showing a lower surface of the insulating tape
- FIGS. 7 to 18 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention
- FIG. 19 is a semiconductor device according to an embodiment of the present invention.
- 20 to 23 are cross-sectional views of a semiconductor device according to another embodiment of the present invention
- FIG. 24 is a semiconductor device according to another embodiment of the present invention.
- FIG. 25 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention
- FIG. FIG. 27 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention
- FIG. 28 is a wiring pattern which is a component of the semiconductor device.
- FIG. 29 is a plan view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.
- FIGS. 30 to 38 are other embodiments of the present invention.
- FIG. 39 is a cross-sectional view showing a method of manufacturing a semiconductor device
- FIGS. 39 and 40 are cross-sectional views showing a semiconductor device according to another embodiment of the present invention
- FIG. 41 is another embodiment of the present invention.
- FIGS. 42 and 43 are cross-sectional views illustrating a semiconductor device according to another embodiment of the present invention.
- FIGS. 44 to 48 are cross-sectional views illustrating another embodiment of the present invention.
- FIG. 49 to FIG. 51 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
- FIG. 52 is an enlarged plan view showing wiring of a semiconductor device according to another embodiment of the present invention, and
- FIGS. 53 and 54 are diagrams of a semiconductor device according to another embodiment of the present invention.
- FIG. 55 is a cross-sectional view showing a Sting method
- FIG. 55 is a plan view showing a semiconductor device according to another embodiment of the present invention, and FIG.
- FIGS. 56 is a wiring diagram of a semiconductor device according to another embodiment of the present invention.
- FIGS. 57 and 58 are cross-sectional views showing wirings of a semiconductor device according to another embodiment of the present invention.
- FIG. 1 is a perspective view showing a CSP (chip size package) of the present embodiment
- FIG. 2 is a cross-sectional view of the CSP
- FIG. 3 is a cross-sectional view of the CSP mounted on a printed wiring board.
- the CSP of the present embodiment mainly includes a semiconductor chip 1, an elastomer 1 covering the main surface (element forming surface) of the semiconductor chip 1, an insulating tape 3 provided on an upper portion of the elastomer 2, and one surface (a lower surface) of the insulating tape 3.
- the wiring 4 is formed of a plurality of wirings 4 and solder bumps 5 connected to one ends of these wirings 4.
- the semiconductor chip 1 is made of, for example, single crystal silicon having a thickness of about 0.28 to 0.55 mm, and has a main surface formed of a surface protection film (such as a silicon oxide film or a silicon nitride film) made of an insulating film.
- a passivation film 6 is formed.
- a plurality of bonding pads 7 are formed on the periphery of the semiconductor chip 1. These bonding pads 7 are arranged in a row along the four sides of the semiconductor chip 1, and Au bumps 8 for electrically connecting the bonding pads 7 to the wiring 4 are bonded to the surface of each bonding pad 7. Have been.
- the elastomer 2 covering the main surface of the semiconductor chip 1 is, for example, a low-elasticity photosensitive resist applied on the main surface of the semiconductor chip 1 or a low-elasticity photosensitive film laminated on the main surface of the semiconductor chip 1.
- the thickness is about 0.05 to 0.15 thigh, preferably about 0.01 to 0.1 mm, and more preferably about 0.02 to 0.1 thigh.
- the vertical and horizontal dimensions of the elastomer 1 are the same as those of the semiconductor chip 1.
- the elastomer 1 has a single-layer structure of a polymer elastomer made of, for example, silicone rubber, epoxy, polyimide, polyurethane, fluorine, or the like, or a laminated structure in which about 2 to 3 layers of these are laminated. ing.
- Elastomer 2 reduces the stress caused by the difference in thermal expansion coefficient between semiconductor chip 1 and the substrate on which it is mounted.
- it is formed for the purpose of protecting the chip surface and has an elastic modulus of about 1 to 500 OMPa, preferably:! It is about 100 MPa, more preferably about 1 500 MPa.
- a plurality of through holes 10 are formed in the peripheral portion of the elastomer 12.
- the positions of these through holes 10 correspond to the positions of bonding pads 7 formed on the main surface of semiconductor chip 1. That is, the through hole 10 is formed directly above the corresponding bonding pad 7, and the Au bump 8 is arranged inside the through hole 10.
- the insulating tape 3 disposed on the upper part of the elastomer 2 is made of, for example, a resin such as polyimide, glass epoxy, or polyester, and has a thickness of about 0.05 to 0.125 mm, and a dimension in the vertical and horizontal directions. Is the same as the semiconductor chip 1.
- This insulating tape 3 is bonded to the upper surface of the elastomer 12 by a bonding agent or the like.
- the plurality of wirings 4 formed on one surface of the insulating tape 3 are formed by etching an electrolytic copper foil (or a rolled copper foil) attached to the insulating tape 3, and the surfaces of both ends thereof include, for example, A u / N i plating is applied.
- FIG. 4 is a perspective view showing the upper surface of the insulating tape 3
- FIG. 5 is a perspective view showing the lower surface.
- a plurality of openings 9a are formed in the peripheral portion of the insulating tape 3.
- the positions of these openings 9 a correspond to the positions of the bonding pads 7 of the semiconductor chip 1 and the through holes 10 of the elastomer 12.
- the same number of openings 9b as the openings 9a are formed in the center of the insulating tape 3.
- These openings 9 b are arranged in a grid along the longitudinal and lateral directions of the insulating tape 3.
- the same number of wires 4 as the openings 9a and 9b are formed.
- One end of each wiring 4 extends inside the corresponding opening 9a, and the other end extends inside the corresponding opening 9b.
- one end of the wiring 4 is electrically connected to the Au bump 8 through a through hole 10 formed in the elastomer 12.
- the inside of the through hole 10 is filled with a sealing material 11 for protecting a connection portion between the wiring 4 and the Au bump 8.
- This sealing material 11 is made of, for example, an epoxy resin.
- a spherical solder bump 5 is electrically connected to the other end of each wiring 4.
- Solder bump Reference numeral 5 is made of, for example, a Pb—Sn eutectic alloy, a high melting point solder, a Ni alloy with Au plating, and the like, and has a diameter of about 0.25 to 0.7 mm.
- solder bumps 5 are temporarily formed on the printed wiring board 40 footprint (electrodes) 41 using solder paste or flux. After attaching, reflow solder bumps 5 in a heating furnace.
- the CSP is caused by a difference in thermal expansion coefficient between the semiconductor chip 1 and the printed wiring board 40.
- the stress can be relaxed and absorbed by the elastic deformation of the elastomer 12.
- the reliability of the connection between the CSP and the printed wiring board 40 can be ensured for a long period of time because the temperature cycle life of the solder bumps 5 is prolonged.
- the printed wiring board 40 on which the CSP of the present embodiment is mounted does not need to be an expensive material designed to have a coefficient of thermal expansion close to that of the semiconductor chip 1, and has a larger thermal expansion coefficient than the semiconductor chip 1. It can be made of inexpensive materials having an expansion coefficient (for example, glass epoxy resin).
- the elastomer 12 is formed on the main surface of the semiconductor chip 1 and the insulating tape 3 is bonded to the upper portion of the elastomer 12, so that the elastomer 2 and the insulating tape 3 Functions as a protective layer for protecting the main surface of the semiconductor chip 1. Therefore, it is not necessary to separately form a protective layer such as polyimide resin or epoxy resin on the main surface of the semiconductor chip 1, and the semiconductor chip 1 can be mounted on the printed wiring board 40 as it is.
- FIG. 6 is an overall plan view of the semiconductor wafer
- FIGS. 7 to 18 are cross-sectional views taken along line AA ′ of FIG.
- a semiconductor wafer 50A made of single crystal silicon as shown in FIGS. 6 and 7 is prepared.
- Each chip area 1A on the main surface of the semiconductor wafer 5OA is previously formed by a well-known wafer process combining oxidation, ion implantation, diffusion, insulating film deposition, conductive film deposition, and photolithographic processing.
- An LSI not shown is formed in advance.
- the passivation film 6 on the periphery of each chip area 1A is opened.
- the bonding pad 7 is formed by exposing a part of the uppermost layer wiring.
- the uppermost layer wiring is made of, for example, an A1 alloy film.
- Au bumps 8 are connected to the bonding pads 7 in each chip area 1A.
- the connection of the Au bumps 8 is performed by using, for example, a ball bonding method in which the ends of the Au wires are processed into a ball shape.
- a low-elastic photosensitive resist (or film) is spin-coated (or laminated with an adhesive) on the main surface of the semiconductor wafer 5 OA to form an elastomer 12.
- a predetermined area of the elastomer 2 is selectively exposed using a photomask 20 and then developed, so that the bonding pad 7 is formed as shown in FIG.
- a through-hole 10 is formed in the elastomer 12 directly above the Au bump to expose the Au bump 8.
- the through holes 10 can be formed by using a method of irradiating the elastomer 12 with a laser beam having a fine spot diameter.
- an insulating tape 3 is attached to the upper surface of the elastomer 1 using an adhesive or the like. At this time, the positioning is performed so that the opening 9 a of the insulating tape 3 and one end of the wiring 4 are accurately arranged above the through hole 10 of the elastomer 1. Also, in order to ensure the close contact between the elastomer 2 and the insulating tape 3, the insulating tape 3 is pressed against the upper surface of the elastomer 2 to embed the wiring 4 in the elastomer 1, and the upper surface of the wiring 4 is The upper surface of 2 is made almost the same height.
- the bonding tool 21 heated to about 500 ° C. is crimped to one end of the wiring 4 through the opening 9 a of the insulating tape 3 so that the wiring 4 and A
- the sealing material 11 is injected into the through holes 10 of the elastomer 12 through the openings 9 a of the insulating tape 3 as shown in FIG. This sealing material 11 is thermally cured.
- the solder bump 5 is connected to the other end of the wiring 4 exposed inside the opening 9 b of the insulating tape 3.
- the solder bumps 5 previously formed into a spherical shape are temporarily attached to the surface of the wirings 4 using a solder paste ⁇ flux, and then the solder bumps 5 are heated in a heating furnace. Reflow.
- testing of chip area 1A electrical property inspection and burn In).
- a thin film-like inspection jig 17 is prepared, for example, as shown in FIG.
- the detection jig 17 has a size substantially the same as that of the semiconductor wafer 5 OA, and a large number of probes 18 are formed on one surface thereof. Then, as shown in FIG. 17, a test is performed by applying the probe 18 of the inspection jig 17 to the solder bumps 5 of each chip area 1 A, thereby performing a non-defective chip area 1 A and a defective chip area. 1 A is sorted out.
- FIG. 18 shows the overall flow of the above-described CSP manufacturing process.
- the method of manufacturing the CSP according to the present embodiment is such that after the Au bump 8 is connected to the bonding pad 7 in the chip area 1 A, the probe 1 is connected to the solder bump 5 connected to the wiring 4 of the insulating tape 3.
- the entire process up to the application of test 8 is performed in a wafer process (so-called pre-process), and then the semiconductor wafer 5 OA is diced to obtain the semiconductor chip 1 having the CSP structure from the chip area 1 A.
- these semiconductor chips 1 are covered with the elastomer 1 and the insulating tape 3 when the semiconductor wafer 5 OA is diced, and are sorted into non-defective products and defective products. It can be mounted on the printed wiring board 40 as a CSP, and the packaging step of the semiconductor chip 1 (so-called post-process), which has been performed after dicing the semiconductor wafer 5OA, is almost unnecessary.
- the wiring 4 is arranged on the lower surface side of the insulating tape 3 adhered to the upper surface of the elastomer 1, for example, as shown in FIG. 20, the upper surface of the insulating tape 3 Wiring 4 may be arranged on the side.
- the contact area between the elastomer 1 and the insulating tape 3 is increased and the adhesion between them is improved, so that the work of embedding the wiring 4 in the elastomer 1 is not required.
- the surface of the wiring 4 excluding the region (terminal portion) to which the solder bump 5 is connected is covered with the solder resist 16.
- an insulating tape 3 having an elastic modulus enough to relieve stress generated between a chip and a substrate is used as a semiconductor chip 1 May be directly pasted on the main surface of the.
- the elastomer 12 since the elastomer 12 is not required, the number of CSP components can be reduced, and the number of manufacturing steps can be reduced.
- the flatness of the main surface of the semiconductor chip 1 is improved because the elastomer 2 is not used, the variation in the height of the solder bump 5 connected to the wiring 4 is reduced, and the CSP and the printed wiring board 40 are not connected to each other. Connection reliability is further improved.
- the wiring 4 may be formed directly on the surface of the elastomer 12 as shown in FIG. 22, for example.
- a metal film is deposited on the surface by electroless plating or vapor deposition, and then This metal film is patterned using a lithography technique.
- the number of components of the CSP can be reduced and the number of manufacturing steps can be reduced, and the flatness of the chip surface can be improved.
- the Au bump 8 connected to the bonding pad 7 may have a multi-stage structure. In this way, the diameter of the Au bump 8 in the height direction is effectively increased, so that the Au bump 8 itself can have a certain level of stress absorbing ability.
- the surface of the elastomer 1 (or the insulating tape 3 or both) is provided with corrugated irregularities.
- the wiring 4 may have elasticity. In this way, a part of the stress applied to the solder bumps 5 is reduced or absorbed by the expansion and contraction of the wiring 4, so that the connection reliability between the CSP and the printed wiring board 40 is further improved.
- FIG. 26 is a perspective view showing the CSP of the present embodiment
- FIG. 27 is a cross-sectional view of the CSP.
- the main surface of the semiconductor chip 1 is covered with an elastomer 12, and wiring 12 is formed on the upper surface of the elastomer 12.
- the elastomer 12 is made of the same low-elasticity photosensitive resist (or film) as that used in the first embodiment, and one end of the wiring 12 formed on the upper surface thereof is connected to the elastomer 12.
- Through the formed through holes 13 electrically connect with the bonding pads 7 of the semiconductor chip 1. It is connected.
- the other end of the wiring 12 is connected to the same solder bump 5 as in the first embodiment.
- the bonding pads 7 are arranged in a grid at the center of the main surface of the semiconductor chip 1, similarly to the solder bumps 5, instead of at the periphery of the main surface of the semiconductor chip 1.
- the wiring 12 on the top surface of the elastomer 1 has an arc-shaped pattern instead of a straight line from the through hole 13 to the terminal (the area where the solder bump 5 is connected). ing. Further, as shown in FIG. 27, the surface of the wiring 12 is covered with the solder resist 16 except for the terminals. Further, the side surface of the semiconductor chip 1 is covered with a sealing material 14 made of an epoxy resin or the like, so that foreign matter such as moisture does not easily enter the chip through the side surface from outside.
- the stress generated between the chip and the substrate is not only the elastic deformation of the elastomer 12 but also the expansion and contraction of the wiring 12
- the reliability of the connection between the CSP and the substrate is further improved.
- the wiring 12 has a stress absorbing ability, the connection reliability between the CSP and the substrate can be maintained even when the elastomer 1 is made thinner (that is, the stress absorbing ability of the elastomer 1 is made smaller). Therefore, a thin CSP can be realized.
- the bonding pad 7 can be arranged in an arbitrary region on the main surface of the semiconductor chip 1 including the element formation region. Further, the height of the Au bumps 8 does not need to be considered when forming the elastomer 12 on the main surface of the semiconductor chip 1, so that the thickness of the elastomer 12 can be easily reduced.
- the pattern of the wiring 12 may be an arc-shaped pattern as shown in FIG. 28 (a), an S-shaped pattern as shown in FIG. 28 (b), or an L-shaped pattern as shown in FIG. 28 (c). Any curved pattern such as a character pattern can be used.
- FIG. 4D by forming the curved portion of the wiring 12 with a plurality of fine wiring patterns, the elasticity of the curved portion is further improved and the wiring resistance is reduced. In addition, even if one of the wires is broken, it is possible to ensure continuity with another wire. Also At this time, when adjacent fine wirings are connected in some places to form a mesh-like pattern, an increase in wiring resistance can be minimized even if the fine wiring is broken at one location.
- FIG. 29 is an overall plan view of the semiconductor wafer
- FIGS. 30 and 31 are cross-sectional views showing about one chip area of the semiconductor wafer.
- a semiconductor wafer 50B made of single crystal silicon as shown in FIG. 29 is prepared.
- LSI (not shown) is formed in each chip area 1B on the main surface of the semiconductor wafer 50B.
- a plurality of bonding pads 7 made of, for example, an A1 alloy film are formed in a lattice pattern.
- an elastomer 2 was formed by spin-coating (or laminating with an adhesive) a photosensitive resin (or film) having low elasticity on the main surface of the semiconductor wafer 50B.
- the boundary (scribe line) of the chip region 1B is etched from the back side of the semiconductor wafer 50B to form a slit 15 reaching the elastomer 12, and then the slit 15 is formed.
- the sealing material 14 By filling the inside of the slit 15 with the sealing material 14 from the back surface side, the chip regions 1B adjacent to each other are electrically insulated from each other.
- This sealing material 14 becomes a protective layer on the side surface of the semiconductor chip 1 after dicing the chip area 1B into semiconductor chips 1 in a later step.
- a predetermined area of the elastomer 12 is selectively exposed using a photomask 25, and then developed, so that the elastomer 12 is exposed as shown in FIG. Then, a through hole 13 is formed to expose the bonding pad 7. At this time, dicing in the final step is facilitated by simultaneously removing the elastomer 12 near the scribe line.
- a plating layer 12A such as Au or Cu was deposited on the surface of the elastomer 12 including the inside of the through hole 13 and then the photoresist film was used as a mask.
- the plating layer 12A By patterning the plating layer 12A by etching, one end is connected to the bonding pad 7 and the other end is extended to the upper surface of the elastomer 12 through the through hole 13 as shown in Fig. 35.
- the wiring 12 to be formed is formed.
- the wiring 12 on the top surface of the elastomer 1 is shown in FIG. 26 or FIG. It is formed in such a curved pattern.
- the solder resist 16 is coated on the surface of the elastomer 12 including the inside of the through-hole 13 and the wiring 1 excluding the terminal portion to which the solder bump 5 is connected is formed. 2 is coated with a solder resist 16. Further, the solder resist 16 embedded in the through hole 13 functions as a sealing material for protecting the connection between the bonding pad 7 and the wiring 12.
- solder bumps 5 are connected to the terminals of the wirings 12.
- the solder bumps 5 can be connected in the same manner as in the first embodiment by temporarily soldering the solder bumps 5 which have been previously formed into spherical shapes onto the wirings 12 using a solder paste or a flux, and then reflowing in a heating furnace. Good.
- testing electrical characteristic inspection and burn-in
- a non-defective chip area 1B and a defective chip area 1B are tested, and then, as shown in FIG.
- a dicing tape 22 is adhered to the back surface of B, and the boundary (scribe line) of each chip region 1B is diced and divided into a plurality of semiconductor chips 1, whereby the CSP of the present embodiment is completed.
- the through holes 13 are arranged directly above the bonding pads 7, but for example, as shown in FIG.
- the through holes 13 may be arranged, and the wiring 19 formed on the surface protection film (passivation film) 6 may be routed from the bonding pads 7 to the through holes 13.
- a through hole 13 is formed between the elastomer 2 and the surface protective film 6 in a region away from the bonding pad 7.
- a wiring 23 formed of a conductive film (for example, an A1 alloy film) in the same layer as the bonding pad 7 may be routed to the through hole 13.
- the semiconductor chip 1 in which the bonding pads 7 are arranged on the peripheral edge, as used in the first embodiment can also be used.
- a slit 27 is attached to the elastomer 12 near the terminal portion to which the solder bump 5 is connected. You can set it. In this way, the slit 27 expands and contracts. Therefore, the elastomer 12 near the terminal portion is easily elastically deformed, so that the stress applied to the solder bump 5 can be further reduced.
- a pair of slits 27 are formed so as to sandwich each terminal portion, and one of them is arranged on the chip center side, and the other is arranged on the opposite side.
- each slit 27 is oriented in a direction orthogonal to the direction connecting the terminal portion and the center portion of semiconductor chip 1. In this way, a stress component caused by expansion and contraction of the semiconductor chip 1 along the direction connecting the terminal portion and the chip center portion can be effectively reduced.
- the wiring 33 formed on the insulating tape 30 is formed into a curved pattern as shown in FIG. May be configured.
- Fig. 43 Shown in Fig. 43 is manufactured by the following method, for example.
- the surface of the wiring 33 is covered with the solder resist 16 except for a region (terminal portion) to which the solder bump 5 is connected in a later step.
- the insulating tape 30 is laminated on the upper surface of the elastomer 12 using an adhesive or the like, and the Au bumps 8 on the bonding pads 7 and the through holes 31 are formed.
- the solder bump 5 is connected to one end (terminal) of the wiring 33 formed on the upper surface of the insulating tape 30.
- a dicing tape 22 is adhered to the back surface of the semiconductor wafer 50B as shown in FIG.
- the CSP shown in Fig. 43 is obtained by dicing the boundary part (scribe line) of the semiconductor chip into a plurality of semiconductor chips 1.
- a slit 34 may be formed in the elastomer 1 at the boundary of the region 1B, and the inside thereof may be filled with a sealing material 35 made of resin or the like harder than the elastomer 2.
- a sealing material 35 made of resin or the like harder than the elastomer 2.
- the sealing material 35 functions as a protective layer on the side surface of the semiconductor chip 1 after dicing the boundary of the chip region 1B, but is harder than the elastomer 1-2. Because of its quality, it also has the function of preventing the elastomer 12 from being excessively deformed during dicing.
- the slit 34 may be formed deeply so that its bottom reaches the inside of the semiconductor wafer 50B.
- the side surface protection function of the semiconductor chip 1 by the sealing material 35 can be further enhanced.
- the semiconductor material 50B is anisotropically etched so that the diameter of the bottom of the slit 34 is made larger than the vicinity of the wafer surface, so that the sealing material 35 is hardly peeled off from the side surface of the semiconductor chip 1. ( Figure (b)).
- a slit 34 is formed in a semiconductor wafer 50B at a boundary portion of a chip area 1B, and thereafter, a slit 34 is formed as shown in FIG. ),
- the elastomer 12 may be applied on the main surface of the semiconductor wafer 50B including the inside of the slit 34. By doing so, the elastomer 12 can be used as a protective layer on the side surface of the semiconductor chip 1 as shown in FIG. The step of filling is unnecessary.
- the CSP for example, as shown in FIG. 52, at least a part of the wiring 12 formed on the upper surface of the elastomer or one surface of the insulating tape may be used as the fuse 36.
- the defective chip area can be eliminated by cutting the fuse 36 formed in the chip area where a short-circuit failure or the like has been found in the electrical characteristic inspection prior to burn-in or during burn-in.
- the solder bumps 5 in the chip area 1B where a short-circuit failure or the like is found in the electrical characteristic test are scraped off. As shown in Fig.
- FIG. 55 shows that the wiring 12 formed on the top of the elastomer 12 is oriented so as to be orthogonal to the direction connecting the solder bump 5 connected to the wiring 12 and the center of the semiconductor chip 1.
- the wirings 12 arranged at the periphery of the semiconductor chip 1 are formed longer than the wirings 12 arranged at the center of the semiconductor chip 1.
- the wiring 12 does not necessarily have to be a linear pattern.
- the cumulative length of the wiring component in a direction orthogonal to the chip center direction depends on the distance from the chip center. It only has to be proportionally longer.
- the wiring 12 formed on the elastomer 12 bonded to the main surface of the semiconductor chip 1 may have a multilayer structure. In this case, noise may be reduced by arranging the power supply wiring 12 and the signal wiring 12 on different layers of the elastomer 12. Further, when bonding the insulating tape 3 to the upper surface of the elastomer 12, as shown in FIG. 58, the insulating tape 3 having the wiring 33 formed on both sides may be used. Industrial applicability
- a CSP in which a stress applied to a bump electrode due to a difference in thermal expansion coefficient between a semiconductor chip and a substrate is reduced or absorbed by elastic deformation of an elastomer or expansion and contraction of wiring. Therefore, it is possible to provide a CSP suitable for use in small and lightweight electronic devices, for example, portable information terminals such as mobile phones, PDAs, and HPCs.
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97909706A EP1030357A4 (en) | 1997-10-30 | 1997-10-30 | SEMICONDUCTOR ARRANGEMENT AND PRODUCTION METHOD |
JP2000519463A JP3768817B2 (ja) | 1997-10-30 | 1997-10-30 | 半導体装置およびその製造方法 |
PCT/JP1997/003969 WO1999023696A1 (fr) | 1997-10-30 | 1997-10-30 | Dispositif a semi-conducteur et son procede de fabrication |
KR1020007004653A KR20010031602A (ko) | 1997-10-30 | 1997-10-30 | 반도체 장치 및 그 제조 방법 |
AU47263/97A AU4726397A (en) | 1997-10-30 | 1997-10-30 | Semiconductor device and method for manufacturing the same |
TW086116916A TW395001B (en) | 1997-10-30 | 1997-11-13 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1997/003969 WO1999023696A1 (fr) | 1997-10-30 | 1997-10-30 | Dispositif a semi-conducteur et son procede de fabrication |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999023696A1 true WO1999023696A1 (fr) | 1999-05-14 |
Family
ID=14181398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1997/003969 WO1999023696A1 (fr) | 1997-10-30 | 1997-10-30 | Dispositif a semi-conducteur et son procede de fabrication |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1030357A4 (ja) |
JP (1) | JP3768817B2 (ja) |
KR (1) | KR20010031602A (ja) |
AU (1) | AU4726397A (ja) |
TW (1) | TW395001B (ja) |
WO (1) | WO1999023696A1 (ja) |
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WO2002063681A1 (en) * | 2001-02-08 | 2002-08-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and its manufacturing method |
EP1143515A3 (en) * | 2000-04-06 | 2002-09-25 | Shinko Electric Industries Co. Ltd. | Wiring substrate, method of manufacturing the same and semiconductor device |
JP2002299510A (ja) * | 2001-03-30 | 2002-10-11 | Sumitomo Bakelite Co Ltd | 半導体装置 |
US6515372B1 (en) | 1999-02-26 | 2003-02-04 | Hitachi, Ltd. | Wiring board and its production method, semiconductor device and its production method, and electronic apparatus |
US6624504B1 (en) | 1999-10-29 | 2003-09-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
US6661093B2 (en) | 2000-11-30 | 2003-12-09 | Renesas Technology Corporation | Semiconductor device |
US6720591B2 (en) | 2001-04-23 | 2004-04-13 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US6770547B1 (en) | 1999-10-29 | 2004-08-03 | Renesas Technology Corporation | Method for producing a semiconductor device |
US6822317B1 (en) | 1999-10-29 | 2004-11-23 | Renesas Technology Corporation | Semiconductor apparatus including insulating layer having a protrusive portion |
US6828174B2 (en) | 2001-06-07 | 2004-12-07 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US6861742B2 (en) | 2001-01-18 | 2005-03-01 | Renesas Technology Corp. | Wafer level chip size package having rerouting layers |
US7038322B2 (en) | 2000-10-05 | 2006-05-02 | Hitachi, Ltd. | Multi-chip module |
JP2007524249A (ja) * | 2004-02-26 | 2007-08-23 | シーメンス アクチエンゲゼルシヤフト | 電気的な構成要素と該構成要素の電気的な接続導体とを有するシステム並びに該システムを製造する方法 |
US7591651B2 (en) | 2006-09-27 | 2009-09-22 | Epson Imaging Devices Corporation | Substrate with helically curved terminals superimposed and connected to identical terminals on a second substrate |
WO2009139153A1 (ja) * | 2008-05-16 | 2009-11-19 | 住友ベークライト株式会社 | 半導体部品の製造方法および半導体部品 |
US7786564B2 (en) | 2007-07-18 | 2010-08-31 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing semiconductor device |
US7964962B2 (en) | 2007-07-18 | 2011-06-21 | Elpidia Memory, Inc. | Method of manufacturing a semiconductor apparatus |
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US20120112336A1 (en) * | 2010-11-05 | 2012-05-10 | Guzek John S | Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package |
US9351436B2 (en) | 2013-03-08 | 2016-05-24 | Cochlear Limited | Stud bump bonding in implantable medical devices |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277138A (ja) * | 1987-10-28 | 1990-03-16 | Hitachi Ltd | 電子部品の接続構造及びそれを用いた電子装置 |
JPH0878574A (ja) * | 1994-09-08 | 1996-03-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH08102466A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 半導体装置の製造方法及び半導体ウエハー |
JPH08250498A (ja) * | 1995-03-09 | 1996-09-27 | Sony Corp | 半導体装置とその製造方法 |
JPH08330355A (ja) * | 1995-03-24 | 1996-12-13 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH09139401A (ja) * | 1995-11-16 | 1997-05-27 | Shinko Electric Ind Co Ltd | 回路シート及びその製造方法並びに半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5029325A (en) * | 1990-08-31 | 1991-07-02 | Motorola, Inc. | TAB tape translator for use with semiconductor devices |
US5258330A (en) * | 1990-09-24 | 1993-11-02 | Tessera, Inc. | Semiconductor chip assemblies with fan-in leads |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5518964A (en) * | 1994-07-07 | 1996-05-21 | Tessera, Inc. | Microelectronic mounting with multiple lead deformation and bonding |
US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
-
1997
- 1997-10-30 EP EP97909706A patent/EP1030357A4/en not_active Withdrawn
- 1997-10-30 AU AU47263/97A patent/AU4726397A/en not_active Abandoned
- 1997-10-30 KR KR1020007004653A patent/KR20010031602A/ko not_active Application Discontinuation
- 1997-10-30 JP JP2000519463A patent/JP3768817B2/ja not_active Expired - Fee Related
- 1997-10-30 WO PCT/JP1997/003969 patent/WO1999023696A1/ja not_active Application Discontinuation
- 1997-11-13 TW TW086116916A patent/TW395001B/zh not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0277138A (ja) * | 1987-10-28 | 1990-03-16 | Hitachi Ltd | 電子部品の接続構造及びそれを用いた電子装置 |
JPH0878574A (ja) * | 1994-09-08 | 1996-03-22 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH08102466A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 半導体装置の製造方法及び半導体ウエハー |
JPH08250498A (ja) * | 1995-03-09 | 1996-09-27 | Sony Corp | 半導体装置とその製造方法 |
JPH08330355A (ja) * | 1995-03-24 | 1996-12-13 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH09139401A (ja) * | 1995-11-16 | 1997-05-27 | Shinko Electric Ind Co Ltd | 回路シート及びその製造方法並びに半導体装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1030357A4 * |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
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US6515372B1 (en) | 1999-02-26 | 2003-02-04 | Hitachi, Ltd. | Wiring board and its production method, semiconductor device and its production method, and electronic apparatus |
US6998713B2 (en) | 1999-02-26 | 2006-02-14 | Hitachi, Ltd. | Wiring board and method for producing same |
US6770547B1 (en) | 1999-10-29 | 2004-08-03 | Renesas Technology Corporation | Method for producing a semiconductor device |
US6822317B1 (en) | 1999-10-29 | 2004-11-23 | Renesas Technology Corporation | Semiconductor apparatus including insulating layer having a protrusive portion |
US6624504B1 (en) | 1999-10-29 | 2003-09-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
US7057283B2 (en) | 1999-10-29 | 2006-06-06 | Hitachi, Ltd. | Semiconductor device and method for producing the same |
US6660942B2 (en) | 2000-04-06 | 2003-12-09 | Shinko Electric Industries Co., Ltd. | Semiconductor device with an exposed external-connection terminal |
EP1143515A3 (en) * | 2000-04-06 | 2002-09-25 | Shinko Electric Industries Co. Ltd. | Wiring substrate, method of manufacturing the same and semiconductor device |
US7038322B2 (en) | 2000-10-05 | 2006-05-02 | Hitachi, Ltd. | Multi-chip module |
US6661093B2 (en) | 2000-11-30 | 2003-12-09 | Renesas Technology Corporation | Semiconductor device |
US6861742B2 (en) | 2001-01-18 | 2005-03-01 | Renesas Technology Corp. | Wafer level chip size package having rerouting layers |
US6946327B2 (en) | 2001-01-18 | 2005-09-20 | Renesas Technology Corp. | Semiconductor device and manufacturing method of that |
WO2002063681A1 (en) * | 2001-02-08 | 2002-08-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and its manufacturing method |
US6867123B2 (en) | 2001-02-08 | 2005-03-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and its manufacturing method |
JP2002299510A (ja) * | 2001-03-30 | 2002-10-11 | Sumitomo Bakelite Co Ltd | 半導体装置 |
JP4639505B2 (ja) * | 2001-03-30 | 2011-02-23 | 住友ベークライト株式会社 | 半導体装置 |
US6720591B2 (en) | 2001-04-23 | 2004-04-13 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US6949416B2 (en) | 2001-04-23 | 2005-09-27 | Renesas Technology Corp. | Method of manufacturing a semiconductor integrated circuit device |
US6841881B2 (en) | 2001-06-07 | 2005-01-11 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US6828174B2 (en) | 2001-06-07 | 2004-12-07 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
US7388295B2 (en) | 2001-11-19 | 2008-06-17 | Renesas Technology Corp. | Multi-chip module |
JP2007524249A (ja) * | 2004-02-26 | 2007-08-23 | シーメンス アクチエンゲゼルシヤフト | 電気的な構成要素と該構成要素の電気的な接続導体とを有するシステム並びに該システムを製造する方法 |
US7591651B2 (en) | 2006-09-27 | 2009-09-22 | Epson Imaging Devices Corporation | Substrate with helically curved terminals superimposed and connected to identical terminals on a second substrate |
US7786564B2 (en) | 2007-07-18 | 2010-08-31 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing semiconductor device |
US7964962B2 (en) | 2007-07-18 | 2011-06-21 | Elpidia Memory, Inc. | Method of manufacturing a semiconductor apparatus |
US8441126B2 (en) | 2007-07-18 | 2013-05-14 | Elpida Memory, Inc. | Semiconductor device |
WO2009139153A1 (ja) * | 2008-05-16 | 2009-11-19 | 住友ベークライト株式会社 | 半導体部品の製造方法および半導体部品 |
US8247270B2 (en) | 2008-05-16 | 2012-08-21 | Sumitomo Bakelite Co., Ltd. | Method of manufacturing semiconductor component, and semiconductor component |
JP5682308B2 (ja) * | 2008-05-16 | 2015-03-11 | 住友ベークライト株式会社 | 半導体部品の製造方法 |
TWI799226B (zh) * | 2022-04-07 | 2023-04-11 | 頎邦科技股份有限公司 | 薄膜覆晶封裝 |
Also Published As
Publication number | Publication date |
---|---|
TW395001B (en) | 2000-06-21 |
EP1030357A4 (en) | 2004-10-20 |
KR20010031602A (ko) | 2001-04-16 |
AU4726397A (en) | 1999-05-24 |
JP3768817B2 (ja) | 2006-04-19 |
EP1030357A1 (en) | 2000-08-23 |
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