Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/00007—Time or data compression or expansion
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
  • G11B20/1806—Pulse code modulation systems for audio signals
  • G11B20/1809—Pulse code modulation systems for audio signals by interleaving
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
  • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
  • G11B20/10—Digital recording or reproducing
  • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
  • G11B20/1806—Pulse code modulation systems for audio signals
  • G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S358/00—Facsimile and static presentation processing
  • Y10S358/906—Hand-held camera with recorder in a single unit

Definitions

• the present invention relates to a digital information signal recording / reproducing apparatus and method for recording a digital information signal such as a digital video signal on a recording medium and reproducing the digital video signal from the recording medium.
• a signal processing device used for a digital VTR video tape recorder
• a digital VTR video tape recorder
• a digital VTR video tape recorder
• the compression-encoded video signal is subjected to an error correction encoding process and recorded on, for example, a video tape.
• the reproduced signal is subjected to error correction processing and compression encoding decoding processing, and is output as a reproduced video signal.
• the error correction code a product code that double-codes a predetermined number of data words with an inner code and an outer code is often used.
• a preview is usually made to confirm the finish of the edited result.
• a preview is performed by a method of switching between an input video signal to be inserted and a reproduction signal reproduced from a tape at an editing point and confirming the switching result on a monitor.
• FIG. 1 shows a conventional configuration for performing this preview.
• 1 is a compression encoding encoder
• 2 is an ECC encoder that performs error correction encoding.
• the output of ECC encoder 2 is supplied to the recording head via a recording driver, etc., and is recorded as a diagonal track on magnetic tape.
• the recording head is mounted on a rotating drum, and the reproducing head is provided on the rotating drum.
• the playback head includes an advance playback head (referred to as an ADV head) provided at a position preceding the recording head in the rotation direction, and a playback head (immediately provided after the recording head). CNF head).
• Normal playback is performed by the ADV head.
• the ADV head also enables insert editing in which the video data recorded on the tape and the video data input from the outside are synchronized, and the material is inserted into the already recorded base.
• the CNF head reads the data recorded by the recording head immediately when recording is performed so that the background is erased by the full erase head, and it is recording that the normal recording is being performed. Is provided for confirmation.
• a reproduced signal of an ADV head indicated by ADVPBBRF is supplied to an inner code decoder 3 for performing error correction of an inner code.
• the data subjected to the error correction by the inner code is supplied to the outer code decoder 5 and subjected to the outer code error correction processing.
• the inner code decoder 3 is written with the corrected data, and is connected to a RAM 4 for rearranging the data order to the outer code sequence.
• the outer code decoder 5 is written with the corrected data, and connected to the RAM 6 for rearranging the data order to the inner code sequence.
• the reproduced data that has been subjected to the error correction processing is supplied to the decoder 7 of the compression code.
• the reproduced data indicated by CNF PB RF reproduced from the CNF head is also subjected to error correction using the inner code in the inner code decoder 9 and RAMI 0, and then to the outer code decoder 11 and The error correction using the outer code is performed by the RAM 12.
• Each decoder 9, 11 1 RAMs 10 and 12 are connected to rearrange the data order. Then, it is supplied to the compression code decoder 7.
• one of the output and 11 of the outer code decoder 5 is selectively decompressed in accordance with the operation mode (recording mode and reproduction mode) of the VTR, and becomes a reproduction video signal.
• FIG. 2 is a timing chart in the case of performing the insert editing or the preview thereof according to FIG. 1 described above.
• FIG. 2 focuses on the signal of the frame corresponding to the frame 0 of the input video signal, and the signal of one frame is represented by a rectangle substantially equal to the length of one frame period.
• One frame divided into six equal parts represents compressed data composed of six segments.
• the reproduced signal of the ADV head is processed by the inner code decoder 3, and output data having a one-segment delay appears. Further, the outer code decoder 5 corrects the error by the outer code, and the outer code decoder 5 outputs a corrected output with a time delay of the processing.
• the output of the outer code decoder 5 is decompressed by the compression decoder 7, and the reproduced video signal is output with a delay of one frame.
• the reproduced video signal is a signal of frame 0, and is synchronized with the input video signal passing through the EE system at the stage where it is supplied to the selector 8.
• Selector 8 outputs Select the video signal.
• the preview is monitored by the output of the selector 8, and the edit mode is switched from the reproduction mode to the recording mode, and the output is overwritten on the background on the tape.
• the input video signal is compressed by the compression encoder 1, it is output from the compression encoder 1 one frame later.
• the product code is encoded by the ECC encoder 2, and the output of the ECC encoder 2 is generated with a time delay required for the encoding. This is recorded on the tape by the recording head.
• the recorded signal is reproduced by the CNF head with a delay of about 0.5 segment.
• the present invention provides a digital information signal recording / reproducing apparatus which records a digital information signal on a recording medium and reproduces the digital information signal from the recording medium.
• a recording signal path including compression encoding means for performing compression encoding on the input digital information signal, and error correction encoding means for performing error correction encoding on the compressed signal from the compression encoding means;
• Recording means for recording a signal passing through a recording signal path on a recording medium; reproducing means for reproducing a signal from the recording medium;
• a reproduction signal path including a reproduction signal supplied from a reproduction unit and performing error correction encoding decoding, and a compression decoding unit supplied with an output of the error correction unit and decompressing the encoding;
• a digital information signal recording / reproducing apparatus characterized by having a selection means for selectively outputting a signal passed through a reproduction signal path and a signal passed through a bypass signal path.
• the error correction means has an input section for the reproduced signal and an input section for the bypass signal passing through the bypass signal path, and is provided between the output of the error correction encoding means and the input of the error correction means.
• a bypass signal path is provided.
• This error correction means has a memory for rearranging the signal order, assigns independent addresses to the reproduction signal and the bypass signal, and writes the reproduction signal and the bypass signal to independent areas of the memory. Is inserted. Then, one of the reproduction signal and the bypass signal stored in the memory is selected and read from the memory. By setting the read phase to be the same for the reproduction signal and the bypass signal, reproduction at the time of writing to the memory is performed. Eliminate the phase difference between the signal and the bypass signal.
• the present invention relates to a digital information signal recording / reproducing method for recording a digital information signal on a recording medium and reproducing the digital information signal from the recording medium.
• a digital information signal recording / reproducing method comprising a step of selecting a signal subjected to a reproduction signal processing and a bypassed signal.
• FIG. 1 is a block diagram showing an example of a configuration for previewing a conventional digital VTR
• FIG. 2 is a timing chart for explaining one preview operation of a conventional digital VTR
• FIG. FIG. 4 is a block diagram showing an example of the configuration of the main part of the embodiment of the present invention.
• FIG. 4 is a timing chart for explaining the operation of the main part of the embodiment of the present invention.
• FIG. 6 is a block diagram showing an example of a recording / reproducing structure of an example of a digital VTR to which the present invention can be applied.
• FIG. 6 is a diagram showing a recording / reproducing structure of another example of a digital VTR to which the present invention can be applied.
• FIG. 7 is a schematic diagram showing an example of a one-track data format
• FIG. 8 is a schematic diagram used for describing an error correction code and a sync block
• FIG. 10 is a schematic diagram showing an example of a data format inside the error correction decoder ⁇ C
• FIG. 11 is a schematic diagram showing a RAM external to the error correction decoder IC
• FIG. 12 is a schematic diagram showing an example of a read / write data format.
• FIG. 12 is a schematic diagram showing an example of an assignment of a RAM address external to the error correction decoder IC. Is a schematic diagram showing an example of an assignment of a column address of a RAM external to the error correction decoder IC
• FIG. 14 is a diagram for explaining an access operation of the RAM external to the error correction decoder IC.
• FIG. 15 is a timing chart for explaining the time-division operation of the RAM externally attached to the error correction decoder IC.
• FIG. 1 is a compression encoding encoder
• 2 is an ECC encoder that encodes an error correction code (product code).
• the output of the ECC encoder 2 is supplied to a recording head via a recording driver or the like, and is recorded on a magnetic tape as an oblique track.
• the recording head is mounted on a rotating drum, and the playback head is provided on the rotating drum.
• the playback head has an ADV head provided at a position preceding the recording head in the rotation direction, and a CNF head provided immediately after the recording head. .
• the ADV head is normally used for playback.
• insert editing is performed to synchronize the playback data with the video data input from the outside and insert the material into the already recorded background.
• the CNF head is used to immediately read the data recorded by the recording head, and to confirm during recording that normal recording has been performed. Further, in one embodiment of the present invention, a reproduction signal of the CNF head is used at the time of editing work.
• the playback signal AD VPB RF of the AD V head is supplied to the ECC decoder 13.
• the ECC decoder 13 is an IC that can process both the inner code and the outer code.
• a memory (DRAM) 14 is externally connected to the ECC decoder 13 IC. The arrangement of the data array is performed by the memory 14. Then, the reproduced data subjected to the error correction processing is supplied to the decoder 15 of the compression code.
• the ADV head has a DT (dynamic tracking) function. CNF head does not have DT function. The DT function scans tracks on the tape. This function controls the position of the head in the height direction so as to draw a trajectory.
• the ADV head can obtain a playback signal with better SZN compared to the CNF head, and also scans the track even during special playback where the tape is stopped or the tape speed is made different from that during recording. be able to.
• the playback signal of the ADV head having such a DT function is used as a normal playback output.
• reproduction data CNF P B 1 from the CNF head is supplied to the same decoder 16 and error correction is performed.
• An external memory 17 is provided for the ECC decoder 16.
• the reproduction data having been error-corrected by the ECC decoder 16 is supplied to a compression decoder 18 of a compression code.
• the ECC decoder 16 is capable of receiving two inputs. Reproduction data CNF P BRF is supplied to one input system, and output data of the ECC encoder 12 is supplied to the other input system.
• the ECC decoder 16 writes these two input data to independent areas of the memory 17 and selectively outputs one of the data from the memory 17 when outputting from the ECC decoder 16. Read.
• the reproduced video signals from the compression decoders 15 and 18 are supplied to the selector 19.
• the selector 19 selects one of the data of the decoders 15 and 18 and outputs it as a reproduced video signal.
• the normal playback video signal passing through the PB system including the compression decoder 15 and the output passing through the ECC decoder 16 and the compression decoder 18 (ie, data passing through the EE system or the CNF PB system) are supplied to the selector 19.
• the selector 19 one of the output of the normal PB system and the output of the compression decoder 18 is selected in response to an external control signal. In other words, when editing and previewing The output of the compression decoder 18 is selected.
• the output of the selector 19 is used as an output video signal. Switching between editing and preview is performed by switching between CNF PB output (hereinafter simply referred to as CNF) and EE output in the ECC decoder 16.
• FIG. 4 is a timing chart when insert editing or previewing is performed according to the present invention described above.
• FIG. 4 focuses on the signal of the frame corresponding to the frame 0 of the input video signal, and the signal of one frame is represented by a rectangle substantially equal to the length of one frame period.
• One frame divided into six equal parts represents compressed data composed of six segment forces.
• the input video signal from the outside is supplied to the compression encoder 1 at frame 0, and is output from the compression encoder 1 one frame later.
• the product code is encoded by the ECC encoder 2, and the output of the ECC encoder 2 is generated with a time delay required for the encoding. This is recorded on the tape by the recording head, and is input to the reproduction system ECC decoder 16 as EE system data.
• the recorded signal is reproduced by the CNF head with a delay of about 0.5 segment, for example, corresponding to the delay of the CNF head with respect to the recording head.
• CNF PBRF is playback data of CNF head.
• This reproduced data is also supplied to the ECC decoder 16.
• the ECC decoder 16 writes the two inputs to independent areas of memory 17.
• the VTR does not know whether it is a preview or editing until immediately before the in-point, but outputs data after CNF-based error correction and compression has been released until before the in-point.
• the output of the ECC decoder 16 output at frame + 2 is CNF-based reproduced video data.
• the selector 19 is used for the compression decoder 18 when editing. Select the output of
• the output of the playback video data through the CNF system is continued as it is.
• the EE data passed through the compression encoder 1 and the ECC encoder 2 is selected and output by the ECC decoder 16.
• the output of the ECC decoder 16 is output via the compression decoder 18 and the selector 19.
• CNF-based playback video data is selected by the PB (CNF PB) ZEE selection function of the ECC decoder 16.
• the ECC decoder 16 reads data from the memory 17 so as to absorb a phase shift between the EE-system reproduced data and the CNF-system reproduced data. Therefore, in the compression decoder 18 or later connected to the ECC decoder 16, data may be processed at the same timing without regard to the EE system and the CNF system.
• the video signal that has passed through the compression encoder 1 and the compression decoder 18 can be seen in the preview.
• image degradation occurs.
• the editing process goes through a similar process. Therefore, the original purpose of the preview, that is, checking the finish of editing, can be achieved.
• the editing operator can perform the editing operation while checking the record. Furthermore, regardless of editing, it is possible to confirm to what extent image quality deteriorates through the process of compression encoding and its decoding using the EE system.
• FIG. 5 shows an example of the configuration of a recording / reproducing system of such a digital VTR.
• Figure 5 shows a four-head system with four recording heads and four playback heads.
• the reproduction system including the CNF head, the EE system, the selector, and the like, which are features of the present invention, are omitted.
• a high-resolution digital video signal is input to an input terminal 21.
• This digital video signal is supplied to the input filter 22.
• the input filter 22 performs a filtering process for compressing the (4: 2: 2) signal into the (3: 1: 1) signal. Also, the clock frequency is changed from 74.25 MHz to 46.40625 MHz.
• the input filter 22 converts the (3: 1: 1) signal into data of two channels.
• the data for each channel has a data rate of 46.40625 MHz.
• the data of these two channels are subjected to compression encoding by BRR (Bit Rate Reduction) encoders 23 and 24 and encoding processing of error correction by error correction encoders (ECC encoders) 25 and 26.
• BRR Bit Rate Reduction
• ECC encoders error correction encoders
• the 81 shakuen encoders 23 and 24 are configured to adaptively switch between intra-field compression and intra-frame compression, and further perform shuffling in units of DCT blocks.
• the DCT block is constituted by the data in the field.
• the DCT block is constituted by the data in the frame.
• In-field compression Switching between encoding and intra-frame compression encoding is performed, for example, using one frame as a minimum unit.
• the product code is encoded, and the recording data in which the sync blocks are continuous is generated.
• the outer code is encoded, and then, for each sync block recorded on the tape, an ID section including the order of the sync blocks and various flags is added. Then, encoding of the inner code is performed.
• the coding range of the ⁇ code includes this ID portion.
• One sync block includes the parity of the inner code and the sync signal indicating the head of the sync block.
• One sync block is the minimum unit of data to be recorded and reproduced.
• the outputs of the ECC encoders 25 and 26 are supplied to a recording equalizer 27.
• the recording data of two channels from the recording equalizer 27 is supplied to the recording head driver 29 R via the rotary transformer 28.
• the recording head driver 29 R has a recording amplifier and a switching circuit for switching supply of a recording signal to the head.
• Recording heads 30, 31, 32, and 33 are connected to the recording head driver 29 R, and recording data is recorded on the magnetic tape 34 by the recording heads 30 to 33.
• the signals recorded on the magnetic tape 34 are reproduced by the reproducing heads 35 to 38.
• the playback signal is supplied to the playback head driver 29P, and a two-channel playback signal is obtained from the playback head driver 29P.
• This reproduction signal is supplied to the reproduction equalizer 40 via the rotary transformer 28.
• Reproduction equalization is performed by the reproduction equalizer 40, and the reproduction serial data is completed.
• a clock synchronized with the reproduction signal is generated and supplied to the ECC decoders 41 and 42 together with the data.
• the output signal of each channel of the playback equalizer 40 (playback serial data Is supplied to the ECC decoders 41 and 42.
• the ECC decoders 41 and 42 detect the synchronization of the input data, switch from the recording rate to the system clock, and correct various errors that occur on the tape. That is, the ECC decoders 41 and 42 correct the inner code of the error correction code configured in advance.
• the inner code is completed in one sync block. If the magnitude of the error is within the correction capability of the inner code, the correction is performed. If it is larger than that, the error flag is set at the error position. Then, the process proceeds to the correction of the outer code, and the erasure correction is performed with reference to the error flag. Most errors can be corrected by this, but in rare cases, such as long errors along the length of the tape, the errors cannot be corrected. At that time, detection is performed within the detection capability range of the outer code, and an error flag is set at the position of the error code.
• the ECC decoder 41, 42 outputs a clock of 46.406 25 MHz, outputs data in sync block units, and outputs a ⁇ -dela flag.
• the outputs of the ECC decoders 41 and 42 are supplied to an 8-length 1 ⁇ 4 decoder 43 and 44, respectively.
• the BRR decoders 43 and 44 perform decoding of variable length coding, inverse DCT conversion and deshuffling, and decode compression codes. Further, corresponding to the intra-field encoding / intra-frame encoding performed by the BRR encoders 23 and 24, the 811 decoders 43 and 44 perform intra-field decoding and intra-frame decoding.
• the output signals of the decoders 43 and 44 are supplied to the concealing circuit 45 together with the concealing error flag.
• the concealing circuit 45 conceals an error in the reproduced signal that exceeds the error correction capability of the ECC decoders 41 and 42. For example, missing without error correction
• the interpolated portion is interpolated by a predetermined method. For example, in the BRR decoders 43 and 44, at the time of decompression, it is determined from the code error flag set at the error position which order of the DCT coefficient has an error. If there is an error in the DC coefficient or lower-order AC coefficient that is relatively important, give up the decoding of that DCT block, pass the concealing flag to the next concealing circuit 45, and An interpolation process is performed.
• the output signal of the concealing circuit 45 is supplied to the output filter 46.
• the output filter 46 changes the clock frequency (from 46.40625 MHz to 74.25 MHz), and also converts the two-channel (3: 1: 1) signal to (4: 2: 2). Convert to a signal.
• the output video signal is output from the output filter 46.
• the input audio data is subjected to predetermined processing by an audio processor 39 and supplied to ECC decoders 25 and 26.
• product code is encoded for each audio data of one channel recorded on one track.
• the recording heads 30 to 33 described above are mounted on a rotating drum that rotates at, for example, 90 Hz.
• the pair of recording heads 30 and 32 and the pair of recording heads 31 and 33 are provided in close proximity.
• the azimuths of recording heads 30 and 32 will be different.
• the azimuths of record heads 31 and 33 will be different.
• the pair of recording heads 30 and 31 facing each other at 180 ° are regarded as having the same azimuth.
• the rotating drum is provided with regeneration heads 35, 36, 37 and 38.
• the arrangement of these reproduction heads 35, 36, 37 and 38 and the relationship between azimuths are the same as those of the recording heads 30, 31, 32 and 33 described above.
• a magnetic tape is wound around the rotating drum at a winding angle of 180 °, and recording data is sequentially recorded on the magnetic tape as oblique tracks.
• the recording head driver 29R is provided with a switching circuit for switching the recording signal in synchronization with the rotation of the head, together with the recording amplifier.
• the reproduction head driver 29 P is provided with a reproduction amplifier and a switching circuit.
• a switching pulse 49 synchronized with the rotation of the head is supplied from the servo circuit 48 as shown by a broken line.
• the switching pulse 29 is also supplied to the J-coders 25 and 26 and the ECC decoders 41 and 42.
• recording heads 30 to 33 and playback heads 35 to 38 are assigned to recording heads 30 to 33 and playback heads 35 to 38, respectively, as shown in Fig. 5, the recording is started. Heads 30 and 32 form recording heads A and B and the corresponding track cards at the same time, and then heads 31 and 33 turn recording heads KC and D and the corresponding tracks C and D is formed simultaneously.
• recording data of one frame (1/30 second) of a video signal is recorded on continuous 12 tracks.
• a segment is composed of two adjacent tracks (A and B channels and C and D channels) with different azimuths. Therefore, one frame of the video signal is composed of six segments. Segment numbers from 0 to 5 are assigned to each of these six segments. Note that audio data of four channels is recorded, for example, at the center of each track so as to be sandwiched by video data.
• the playback heads 35 to 38 are advance (ADV) heads for normal playback, and a CNF head is provided immediately after the recording heads 30 to 33. Will be.
• FIG. 6 shows another example of a digital VTR to which the present invention can be applied.
• FIG. 6 shows an eight-head system in which a video camera and a digital VTR are integrated, and each has eight recording heads and eight reproducing heads.
• a color image is picked up by the CCD indicated by 81 and is converted into a two-channel video signal by the A / D converter and camera processor 82.
• the video signal of each channel is compression-coded by the BRR encoders 83 and 84 and supplied to the ECC encoders 50 and 51.
• Each channel is further divided into two channels by ECC encoders 50 and 51, and recording data of four channels is formed.
• Eight recording heads 55, 56, 57, 58, 59, 60, 61, via recording equalizer 52, rotary transformer 53, and recording head driver 54R 62 is supplied with recording data, and is recorded on the magnetic tape 34 as an oblique track.
• Reproduction heads 63, 64, 65, 66, 67, 68, 69, 70 similar to the recording head are provided, and the output signal of the reproduction head is supplied to the reproduction head driver 54P. And a 4-channel playback signal.
• This reproduction signal is supplied to the reproduction equalizer 72 via the rotary transformer 53.
• the output of the reproduction equalizer 72 is supplied to the ECC decoders 73 and 74, and error correction processing is performed.
• the ECC decoders 73 and 74 two channels of reproduced data are generated, and these are decoded by the BRR decoders 75 and 76.
• the switching pulse 77 from the servo circuit 78 is supplied to the ECC encoders 50, 51, ECC decoders 73, 74, the recording head driver 54R and the reproducing head driver 54P, and the Timing control synchronized with rotation is performed.
• the playback data that has been compressed and encoded by the decoders 75 and 76 is supplied to the concealing circuit 79 and interpolation of uncorrectable errors is performed. .
• the output of the concealing circuit 79 is supplied to the output filter 80.
• the output filter 80 converts the (3: 1: 1) signal into a (4: 2: 2) signal and extracts it as an output video signal.
• the number of recording heads and the number of reproduction heads are twice as many as those in the configuration of FIG. 5 (ie, eight). This is to reduce the number of drum revolutions to half that of the 4-head system in Fig. 5 to reduce noise. That is, the four recording heads 55 to 58 in FIG. 6 have the same azimuth, and the recording heads 59 to 62 also have the same azimuth.
• the set of record heads 55-58 and the set of record heads 59-62 are reverse azimuths.
• the pair (F) and the pair of recording heads 61 (D) and 62 (H) are mounted on the rotating drum 180 degrees opposite each other.
• recording heads 55, 57, 59, 61 trace magnetic tape 34 almost simultaneously, and then recording heads 56, 58, 60, 62 almost simultaneously tape magnetic tape.
• recording heads 55, 57, 59, 61 trace magnetic tape 34 almost simultaneously, and then recording heads 56, 58, 60, 62 almost simultaneously tape magnetic tape.
• the recording signal passing through the rotary transformer 53 has four systems, and the opposite head is selected by the switching pulse 77 supplied from the servo circuit 78.
• the playback heads 63 to 70 have the same relationship as the recording head.
• the number of playback signals is four, which is twice the number in the configuration in Fig. 5, but the data rate is half. Processing can be performed with exactly the same circuit as in the case of FIG. Also, Since the same circuit can be used for the reverse azimuth, the ECC decoders 41 and 42 (Fig. 5) and the ECC decoders 73 and 74 can all be realized by the same IC.
• the present invention can be applied to both the above-mentioned 4-head system digital VTR (FIG. 5) and the 8-head system digital VTR (FIG. 6). In the following description, the present invention is applied to a 4-head digital VTR.
• Fig. 7 shows the format of one track formed on a magnetic tape. This track represents the data arrangement along the direction that the head traces.
• One track is roughly divided into video sectors v l and V 2 and audio sectors A 1 to A 4.
• the product code is encoded in units of video data and audio data recorded in one track.
• ⁇ 1, OP 2 indicates the parity of the outer code that occurs when video data is product-coded.
• the parity of the outer code generated when product coding of audio data is recorded in audio sector No.
• Each track is divided into 233 bytes at regular intervals, each of which is called a sink block.
• Fig. 7 shows an example of the length of each data recorded in one track.
• 275 sync blocks + 124 bytes of data are recorded in one track.
• the video sector is 226 sync blocks.
• the time length of one track is about 5.6 ms.
• a non-recorded part is sandwiched between the sectors. This gap is called an edit gap, and is provided so that adjacent sectors are not erased when recording in sector units.
• FIG. 8A is an example of the configuration of an error correction code for video data. Error correction coding is performed for each amount of video data recorded on one track. That is, the video data for one track is (2 1 7 X 226).
• the (226, 226) Reed-Solomon code (encoding of the outer code) is applied to 226 codes (one code here is 1 byte) aligned in the vertical direction of this array.
• the parity of the outer code of 24 words is added.
• an outer code for example, error correction of up to 10 words and erasure correction of up to 24 words are performed.
• a 2-word ID is added to 2 17 words (video data or parity of the outer code) arranged in the horizontal direction of the two-dimensional array.
• parity of the inner code of 12 words is generated.
• audio data is encoded with a product code in the same manner as video data, although the data amount in one track is different.
• the outer code is encoded, and the encoded output of the outer code including the ID is encoded with the inner code.
• On the magnetic tape data with successive sink blocks is recorded after being subjected to scramble processing.
• a 2-byte ID (ID 0 and ID 1) is inserted after the sync pattern.
• ID 0 indicates a sync block number.
• the sync block in one track is set to the sync block number.
• ID 1 a flag for distinguishing an audio sector / video sector, a track number for distinguishing adjacent tracks having different azimuths, and information of a segment number from 0 to 5 are inserted.
• flags for the parameters of compression coding are also inserted into ID1.
• the first word (indicated by HD) of the data of the 217-word in each sync block is a data header.
• a 1-bit sinker flag is inserted along with information indicating the data quantization characteristics and the like.
• the ECC decoder 73 (or 74) in the 8-head system has the same configuration as that of FIG. 9 except that the input system is doubled.
• 90 indicates an IC circuit portion of the ECC decoder.
• This ECC decoder IC90 basically has an inner code error correction function, an outer code error correction function, an audio signal processing function, an error counting function, and an auxiliary data reading function.
• serial data reproduced at a recording rate of 94 Mbps and a clip generated from the serial data are input in parallel, and input to the SP converter 91, 8-bit data converted from serial to parallel data and 1/8 frequency-divided data.
• the high-speed 1-bit wide data is simply reduced to an 8-bit width of 11 Mbps, so the byte and sync block breaks are appropriate. Yes, they are converted to regular data strings by the synchronization detection function of the synchronization detection circuit 92. Part-Time Job
• the break of the sync block is defined by the bit assignment of the output terminal of the synchronization detection circuit 92, and the break of the sync block is defined by the strobe pulse added by the synchronization detection circuit 92.
• the rate is changed to 46 MHz by the rate converter 93.
• the above is the circuit for the input through the PB system, but the same configuration is provided for the input of the EE system.
• the inputs for the EE system are required for signal processing in the case of a camcorder (8-head system), as described above.
• an S / P converter 112 To process the reproduction data of the EE system, an S / P converter 112, a synchronization detection circuit 113, and a rate converter 114 are provided as in the PB system.
• the data packets output from these circuits are mixed into one system by the OR circuit of the mixer 94. A signal originally coming at a rate of 11 Mbps is converted to a rate of 46 Mbps. Therefore, since there is a gap between each packet, it is possible to mix EE data and PB data.
• the input head switching signal is delayed by the timing generator 107 for the delay time of the internal circuit, and information indicating the tape running direction is similarly delayed. It is embedded in the packet at 14.
• the rate converters 93 and 114 are initialized at the timing of head switching and are formatted in a data non-recording section (hereinafter referred to as a gap) by a counter which is initialized by a strobe pulse. Judgment is made and the information is inserted into the packet.
• the bucket output from the mixer 94 is output to the inner code decoder 95.
• the inner code is corrected. Error correction information is embedded in the bucket from the data from the inner code decoder 95 and input to the ID restoration circuit 96. If the inner code cannot be corrected by the inner code decoder 95, the ID cannot be trusted. However, since the memory controller 98 determines the sequence and order of outer code correction with reference to the ID, it is necessary to reproduce the ID.
• the function of the ID restoration circuit 96 is to reproduce the ID of the uncorrectable bucket in anticipation of the IDs of the non-correctable buckets before and after.
• the ID restoration circuit 96 has RAMs for storing three packets in each of the PB system and the EE system in order to refer to a packet that comes later. Utilizing the RAM, conversion to a 16-bit width and start-up with the outer video code decoder 100 are performed.
• the data output from the ID restoration circuit 96 is subjected to a descrambling process by a descrambling circuit 97.
• the main line data output from the descrambling circuit 97 is stored in an SDRAM (Synchronous Dynamic Random Access Memory) 99 external to the IC via the memory controller 98 and is received.
• SDRAM Serial Dynamic Random Access Memory
• the memory controller 98 performs a timing control of data coming from the descrambling circuit 97 and an address control port for separately writing video data and audio data for each segment to the SDRAM 99.
• PB video data is accumulated in one error correction code block (for one track)
• read control is performed on the SDRAM99 in order to perform outer code correction processing by the video outer code decoder 100, and in the outer code direction.
• the memory controller 98 performs a write operation for returning the data after the outer code processing to the SDRAM 99 again.
• the memory controller 98 selects PBZEE data for the data for which the outer code for one track has been decoded, reads the data in the inner code direction, and sends it to the ID renumbering circuit 101.
• the data read phase of the SDRAM99 is the same between the PB data and the EE data.
• the ID renumbering circuit 101 changes IDs for interfacing with the compression decoder.
• audio data is sent to the multiplexer 102 when one field (one error correction coding unit of audio data) is accumulated in the SDRAM 99.
• the data is combined with audio data from the ECC decoder that processes the other azimuth track, and this data is subjected to an outer code correction process in the audio outer code decoder 103.
• the data is changed to the clock rate (256 fs) of the audio data by the rate converter 104, deshuffling and time-base expansion processing is performed by the shirt shirting circuit 105, and error interpolation is performed by the concealing circuit 106 to perform IC interpolation.
• Output as serial data.
• an interface 108 with a microcomputer of the system control (hereinafter referred to as “Syscon”) is provided so that various settings and error information can be read by the Syscon.
• a circuit 110 for extracting video auxiliary data other than video data and a circuit 111 for extracting audio auxiliary data other than audio data are provided, and the extracted auxiliary data is provided via an interface 108.
• an error counter 109 for counting the number of errors is provided.
• One sync block is handled as one package unit.
• Figure 10 shows one sync block when data is handled inside the IC. Indicates the lock data format. This format will be described.
• a sync block number is assigned inside the ECC decoder IC 90 to identify each sync block, and ID 0 contains a sync block number.
• ID 1 includes a segment number, a flag for identifying a video sector and an audio sector, and the like.
• Data numbers 0 to 2 16 contain video data.
• ID 2 contains auxiliary information such as the running direction of the tape.
• the EF contains information on errors in sync block units.
• R count is information indicating how many times video data has been output without any data update due to an error or the like during shuttle playback.
• CRCC is a code for error detection.
• PID 0 contains the sync block number predicted from the head switching pulse.
• Fig. 11 shows the format when data of one sync block is stored in SDRAM99. Since the data width of the RAM 99 is 16 bits, the width of the read / write data of the RAM 99 is also 16 bits. While the internal data format in Fig. 10 is 8 bits wide, the data format of RAM 9.9 is 16 bits, twice as wide, and the number of words is 1 1 2 Words and halves.
• FIGS. 12 and 13 are diagrams of the RAM 99 address assignment.
• the address is divided into a mouth address and a column address.
• Fig. 12 shows the lower dress assignment.
• the video data assignments and audio data assignments are shown in FIG. With (10 to 8) bits, video data is divided into segments, and audio data is fixed at 6. Here, the video data and the audio data are prevented from colliding on the address assignment.
• the PB data and EE data can be stored separately in the RAM 99 at the 7th bit.
• the sixth bit of the data on the video side indicates the tape running direction (1 in the forward direction and 0 in the reverse direction). Bits 5 to 0 of the video data are assigned to bits 7 to 2 (B7 to B2) of the sync block number.
• the sixth bit of the address of the audio side data is fixed to 0. Addresses 5 to 4 of the audio data are assigned to fields 0 to 3. This is because, since one error correction code unit of audio is one field, it is convenient to divide it into fields. Address 3 to 2 bits of audio side data allocate audio channel. Addresses 1 and 2 of the audio data are assigned 3 and 2 bits (B3 and B2) of the sync block number.
• FIG. 13 shows the assignment of the column address.
• the address is set in a format in which the data of four sync blocks in which bits 1 to 0 (B1 to B0) of the sync block number are 0, 1, 2, and 3 are mixed.
• Data is allocated to two banks, bank A and bank B.
• S0, S1, S2, and S3 are the sync block data of bits 1 to 0 (B1 to B0) of the sync block number SO, 1, 2, and 3, respectively.
• Err 0 to Err 216 are assigned to addresses 224 to 251 of bank A and link B in Fig. 13. This is where the error flag after outer code error correction is stored. It is.
• the address sign and data format do not change from the writing of data after decoding of the inner code to the reading of data after decoding of the outer code.
• FIG. 14 is a timing chart showing the access processing to the RAM 99 during preview and editing.
• One frame is composed of 6 segments, and segments 0 to 5 are RAM areas corresponding to each segment of the video.
• the RAM area is divided into a PB system and an EE system, each of which is independent, and each processing is performed simultaneously.
• a PB system and an EE system is selected and processed.
• Each process can be performed simultaneously because the internal clock rate is sufficiently high and each process can be performed in a time-division manner.
• There is no outer code correction processing for the EE system because there is no error in the EE system and it is not necessary.
• the phases of the inputs of the PB system and the EE system are different, when reading the data, the data is read in the same phase.
• each clock access process is performed in a time-division manner in each break, with one clock as one break. Since only the necessary time is given for each process, the clock number differs depending on the process.
• the present invention is applied to a system of 1125 lines / 60 Hz, but this is not limited to this example.
• the present invention can be easily applied to an NTSC system having a field frequency of 59.94 Hz.
• the present invention can be similarly applied to recording / reproduction of only a video signal and only an audio signal.
• the compressed image can be output later from the edit point (in point). What is actually recorded is a compressed image, and the present invention can achieve the original purpose of the preview of confirming the finish of the edited result. Further, according to the present invention, since the bypass signal path is provided, it is possible to confirm how much the input image is degraded when compression-encoding the input image, regardless of the editing operation.
• the ECC decoder has two inputs, such as main and sub, these inputs can be used to supply bypass and playback signals to the ECC decoder, reducing the number of IC pins and reducing cost. Can be realized.
• the playback signal and the bypass signal are written to another area of the connected memory, and one of the playback signal and the bypass signal is selected and read, and the read phase is always set to the same phase.
• the phase of the image does not shift at the in point, and switching between the bypass signal and the playback signal is possible.
• the playback signal and the bypass signal are output in the same phase from the ECC decoder. Therefore, the processing after the ECC decoder can be performed with a fixed phase, and the circuit and processing can be simplified.

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• Engineering & Computer Science (AREA)
• Signal Processing (AREA)
• Multimedia (AREA)
• Signal Processing For Digital Recording And Reproducing (AREA)
• Television Signal Processing For Recording (AREA)

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• 1997
  • 1997-03-31 JP JP9081298A patent/JPH10275417A/ja active Pending
• 1998
  • 1998-03-27 WO PCT/JP1998/001381 patent/WO1998044502A1/ja not_active Ceased
  • 1998-11-27 US US09/200,699 patent/US6370324B1/en not_active Expired - Fee Related

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