WO1998041354A1 - Procede de soudage d'elements en phase solide - Google Patents

Procede de soudage d'elements en phase solide Download PDF

Info

Publication number
WO1998041354A1
WO1998041354A1 PCT/JP1997/000841 JP9700841W WO9841354A1 WO 1998041354 A1 WO1998041354 A1 WO 1998041354A1 JP 9700841 W JP9700841 W JP 9700841W WO 9841354 A1 WO9841354 A1 WO 9841354A1
Authority
WO
WIPO (PCT)
Prior art keywords
bonding
alloy
less
insert layer
oxygen
Prior art date
Application number
PCT/JP1997/000841
Other languages
English (en)
Japanese (ja)
Inventor
Mitsuo Katou
Mamoru Sawahata
Ryoichi Kajiwara
Jin Onuki
Kazuji Yamada
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/000841 priority Critical patent/WO1998041354A1/fr
Publication of WO1998041354A1 publication Critical patent/WO1998041354A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/10—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/16—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01016—Sulfur [S]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Definitions

  • the present invention relates to a solid-state bonding method used for mounting semiconductor devices, electronic devices, and the like.
  • fusion bonding such as soldering or brazing
  • solid-state bonding such as thermocompression bonding or bonding
  • solder bumps and Au bumps are used as disclosed in Japanese Patent Publication Nos. 3-30349, 3-44933 and 3-18452. It is electrically connected by soldering or thermocompression bonding.
  • the parts to be bonded are made of low melting point metal (In, Au-Ge, Au-Sn, Au_Si, Sn, Pb, Pb-Sn)
  • a thin film is used for joining, or Au, Ag, After performing Cu and Ni plating to remove oxides on the surface and diffusion bonding at a bonding temperature of 425 to 500 ° C in a hydrogen, nitrogen, or vacuum atmosphere, solder other parts. Attached.
  • solders such as high and low melting points
  • solders such as high and low melting points
  • heating to a high temperature of about 230 ° C. is required several times during bonding, so that thermal distortion or warpage occurs in the semiconductor element, electronic component, and substrate, and the semiconductor element is inclined and bonded.
  • void defects are often generated in each of the solder layers, and the thermal resistance is large.
  • An object of the present invention is to minimize the thermal damage at the time of mounting in semiconductor devices, power modules, packages, electronic components, and the like, to enable bonding at low temperatures, and to provide a new highly reliable low-temperature solid-state device. It is to provide a phase joining method.
  • Another object of the present invention is to manufacture a pressure-contact type semiconductor device capable of uniformly interrupting a current and preventing damage to a silicon wafer due to current concentration occurring at the time of the current interruption.
  • Still another object of the present invention is to manufacture a semiconductor device, a power module, and a package that can reduce the thermal resistance and enable high-density mounting.
  • the above object is to provide a method of joining members to be joined, wherein a joining surface of the members to be joined is selected from Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy.
  • a joining surface of the members to be joined is selected from Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy.
  • the surface of the insert layer for bonding is 20 at% or less, 10 at% for sulfur, and 5 at% or less for oxygen on the surface of the insert layer for joining.
  • the solid phase bonding may be performed while applying ultrasonic waves.
  • the crystal size of the bonding insert layer is preferably 10 ⁇ m or less.
  • an intermediate buffer layer of any of 1 n, I ⁇ alloy, Cu and Cu alloy is provided to form a two-layer structure, and the hardness of the intermediate buffer layer is HV80 or less.
  • heat treatment at a temperature of 250 to 400 ° C. in the air or in an atmosphere containing 20% or more of oxygen is performed as a pre-bonding treatment on the insert layer for bonding, or Alternatively, heat treatment is preferably performed at a temperature of 250 to 400 ° C. by irradiation with infrared rays in an atmosphere containing 20% or more oxygen.
  • the method includes contacting a plurality of electrode surfaces mounted on both main surfaces of the semiconductor element of the pressure contact type semiconductor device with a plurality of electrodes mounted on both main surfaces of the semiconductor element.
  • a bonding insert layer of any of Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy is provided, and the surface of the bonding insert layer is made of 20 at%.
  • the content of sulfur is set to 10 at% and the content of oxygen is set to 5 at% or less, and the surfaces of the plurality of electrodes mounted on both main surfaces of the semiconductor element and the surface of the bonding insert layer formed on the surface of the thermal buffer plate are overlapped.
  • Solid phase bonding is performed in an atmosphere containing 20% or more at a bonding temperature of 150 to 300 ° C.
  • Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd are formed on the back surface of the Si pellet of the semiconductor device and the stage surface of the lead frame.
  • An insert layer is provided, and the surface of the insert layer for bonding is made of 20 at% or less of carbon, 10 at% of sulfur, and 5 at% or less of oxygen.
  • the surfaces of the bonding sensor layers formed on the stage surface of the frame are superimposed on each other, and solidified at a bonding temperature of 150 to 300 ° C in the air or in an atmosphere containing 20% or more oxygen. Join.
  • Au, Au alloy, Ag, Ag alloy, and the like are formed on the back surface of the Si pellet of the power module and the surface of the heat buffer plate or the wiring substrate on the ceramic plate.
  • a joining insert layer of any one of Pt, Pt alloy, Pd, and Pd alloy is provided, and the surface of the insert layer for joining is made of 20 at% or less of carbon and 10% or less of sulfur.
  • the manufacturing method of the BGA package of the present invention comprises the steps of forming Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd on the surface of the bump electrode of the semiconductor element and the surface of the pad of the wiring board.
  • a bonding insert layer of any of the Pd alloys is provided, and the surface of the bonding insert layer is made of 20 at% or less of carbon, 10 at% of sulfur, and 5 at% or less of oxygen.
  • the surface of the bump electrode portion of the semiconductor element and the surface of the bonding insert layer formed on the pad surface of the wiring substrate are overlapped, and the bonding temperature is set at 150 ° C. in the air or in an atmosphere containing 20% or more of oxygen. Solid phase bonding is performed within the range of ⁇ 300 ° C.
  • Au, Au alloy is applied to the surface of the electrode pad of the wiring pattern of the liquid crystal panel, the surface of the electrode pad of the driver IC, the inner lead and the outer lead of the TAB tape.
  • a g, A bonding insert layer of any of Ag alloy, Pt, Pt alloy, Pd and Pd alloy is provided, and the surface of the bonding insert layer is made of 20 at% or less, The sulfur content is 10 at% or less, and the oxygen content is 5 at% or less.
  • the surface of the insert layer for bonding formed on the surface of the electrode pad of the wiring pattern of the liquid crystal panel and the surface of the outer lead of the TAB tape, and the driver The electrode pad surface of the LSI and the inner lead surface of the TAB tape are overlapped with each other, and solid phase bonding is performed at a bonding temperature of 150 to 300 ° C in the air or in an atmosphere containing 20% or more oxygen. I do.
  • Au, Au alloy, Ag, and Au are formed on the joining surface of a thin plate head component such as an orifice and an ink passage constituting the ink jet head.
  • a bonding insert layer of any of g alloy, Pt, Pt alloy, Pd and Pd alloy is provided, and the surface of the insert layer for bonding is 20 at% or less.
  • Sulfur at 10 at% and oxygen at 5 at% or less and a bonding insert layer formed on a bonding surface of a thin plate head component such as an orifice or an ink passage constituting the ink jet head.
  • solid-phase bonding is performed at a bonding temperature of 150 to 300 ° C. in the air or in an atmosphere containing 20% or more of oxygen.
  • any surface of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy has carbon, sulfur rather than oxidation. A lot of dirt. If there is a large amount of carbon and sulfur deposits, joint defects such as unjoined parts will occur at the joints. For this reason, traditionally, In addition, the welding temperature and pressure are increased and the time is lengthened.
  • any one of Au, Au alloy, Ag, Ag alloy, Pt :, Pt alloy, Pd, and Pd alloy provided on the joining surface of the member to be joined By controlling the amount of carbon and sulfur adhering to the surface of the insert layer, solid-state bonding at low temperatures becomes possible.
  • any one of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd, and Pd alloy provided on the joining surface of the members to be joined is used as a joining sensor.
  • Solid-state bonding at a thermocompression bonding temperature of 150 to 300 ° C by using a clean surface with a carbon layer of 20 at% or less, sulfur of 10 at% or less, and oxygen of 5 at% or less on the surface of the single layer This makes it possible to prevent occurrence of bonding defects such as non-bonding.
  • the material of the bonding insert layer of any of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy is also important.
  • the crystal grain size of the bonding insulator layer of any of Au alloy, Ag and Ag alloy, Pt and Pt alloy, Pd and Pd alloy is as small as 10 ⁇ or less. By doing so, the recrystallization temperature is lowered, and the junction temperature can be further lowered.
  • an intermediate buffer layer of any of Au, Au alloy, Ag, Ag alloy, In, In alloy, Cu and Cu alloy is provided between the member to be joined and the insert insert layer.
  • the hardness of the intermediate buffer layer is HV80 or less
  • the deformability of the entire bonding insert layer is improved, and the bonding interface is in close contact. The degree is increased, and the bondability is improved.
  • the bonding insert layer may be formed before bonding by sputtering, plating or vapor deposition, but when storing after forming the insert layer for bonding. There are many. In this case, the surface of the bonding insert layer is likely to be contaminated by carbon, sulfur, or the like. Therefore, according to the present invention, even when contaminated with carbon, sulfur, or the like during storage, Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd, and Pd alloy before joining.
  • Heat treatment at a temperature of 250 to 400 ° C in the air or in an atmosphere containing 20% or more oxygen or Alternatively, by irradiating infrared rays in an atmosphere containing 20% or more of oxygen and performing heat treatment in a temperature range of 250 to 400 ° C., it is possible to remove attached carbon and sulfur.
  • a plurality of electrode surfaces mounted on both main surfaces of a semiconductor element of the pressure-bonded semiconductor device and both main surfaces of the semiconductor element are mounted.
  • the surface of the thermal buffer plate in contact with the plurality of electrodes is connected to any one of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd and Pd alloy.
  • a low-temperature solid-phase bonding structure is formed by the heat layer.
  • the pressure-bonded semiconductor device with this structure is subjected to low-temperature solid-state bonding at a bonding temperature of 150 to 300 ° C, so there is no heat distortion or warping due to heating during bonding, and it is generated in the semiconductor element.
  • the press-contact type semiconductor device according to the low-temperature solid-state bonding method of the present invention has a structure in which a plurality of electrodes mounted on both main surfaces of a semiconductor element and a thermal buffer plate are subjected to low-temperature solid-state bonding. Therefore, the pressing force applied to the press-contact type semiconductor device can be reduced, and the current interruption characteristics of the press-contact type semiconductor device can be improved.
  • the back surface of the Si pellet and the stage of the lead frame are composed of Au, Au alloy, Ag, Ag alloy, Pt, Pt.
  • the structure is a low-temperature solid-phase bonding by the bonding insulator layer of any one of the alloy, Pd and Pd alloy.
  • This semiconductor device has a low-temperature solid-state bonding at a bonding temperature of 150 to 300 ° C. As a result, there is no thermal distortion or warpage due to heating during bonding, cracks or the like that occur in the semiconductor element can be prevented, and the semiconductor element does not tilt and join, resulting in defects such as voids and poor bonding. And a semiconductor device having a small thermal resistance can be obtained.
  • the back surface of the semiconductor element and the substrate, the heat sink, and the like are made of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd, and Pd.
  • a low-temperature solid-phase bonding structure is formed by any of the bonding insert layers of the Pd alloy.
  • the power module according to the present invention includes a bonding between the back surface of the Si pellet of the power module and the surface of the thermal buffer plate, a direct bonding between the back surface of the Si pellet of the power module and the surface of the wiring board on the ceramic plate, It is possible to join the surface of the wiring board on the ceramic plate to the connection terminals and also to join them together.
  • the BGA package by the low-temperature solid-state bonding method according to the present invention is characterized in that the surface of the bump electrode of the semiconductor element and the surface of the pad of the wiring board are made of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy.
  • a low-temperature solid-phase bonding is achieved by the bonding insert layer of any of Pd, Pd, and Pd alloy. Since the present BGA package can perform low-temperature solid-state bonding at 200 ° C or less, a high-quality BGA package with less thermal damage to semiconductor elements and substrates can be obtained.
  • the display device using liquid crystal by the solid-state bonding method is the same as the electrode pad surface of the wiring pattern of the liquid crystal panel and the outer lead surface of the TAB tape, the inner surface of the electrode pad surface of the driver LSI and the TAB tape.
  • a low-temperature solid phase is formed by joining any one of Au, Au alloy, Ag, Ag alloy, Pt, Pt alloy, Pd, and Pd alloy. It becomes a joined structure. Since the present liquid crystal display device is capable of low-temperature solid-state bonding, thermal damage to semiconductor elements, substrates, and the like is small. The deformation of the lead during bonding is small, the pitch can be narrowed, and the connection resistance can be reduced.
  • thermal damage to a component to be joined can be reduced because the joining temperature is low. Also, when electronic components are used at high temperatures (for example, about 1 ° C), deterioration due to thermal cycling can be prevented, and the life can be extended.
  • the low-temperature solid-state bonding method of the present invention is also applicable to a method of bonding lead pins of a PGA package and a method of sealing a semiconductor package.
  • FIG. 1 is a cross-sectional view showing a bonding step of a low-temperature solid-state bonding method according to one embodiment of the present invention.
  • FIG. 2 shows an Auger analysis result of the Ag sputtered film surface.
  • Fig. 3 shows the relationship between the amount of contamination on the Ag sputtered film surface, the bonding rate, and the bonding strength.
  • FIG. 4 is a cross-sectional view showing a bonding insert layer according to the present invention.
  • FIG. 5 is a cross-sectional view of a main part of a GTO thyristor which is a press-contact type semiconductor device according to the present invention.
  • FIG. 6 is a cross-sectional view of a GTO thyristor which is a press-contact type semiconductor device according to the present invention.
  • FIG. 7 is a sectional view showing a manufacturing process of the power transistor according to the present invention. It is.
  • FIG. 8 is a cross-sectional view showing a structure of a power module according to the present invention.
  • FIG. 9 is a cross-sectional view showing a manufacturing process of a BGA package according to the present invention.
  • FIG. 10 is a cross-sectional view showing a manufacturing process of the liquid crystal display device according to the present invention.
  • FIG. 11 is a cross-sectional view of an ink jet printer head according to the present invention.
  • FIG. 1 is a cross-sectional view showing a bonding step of the low-temperature solid-state bonding method of the present invention.
  • a molybdenum plate (thickness 0.1 mm, width 15 thighs, long length), which is a member 1 to be joined, is Ni-plated (thickness ⁇ ). (15 mm) and Si pellet 2 (10 mm mouth).
  • an Ag sputtered film (thickness 5 ⁇ ) is provided as a bonding insert layer 3a, 3b by a sputtering method.
  • FIG. 2 shows the results of an Auger analysis of the surface of the Ag sputtered film left in the air in FIG.
  • eight types of bonding sputtered film insert layers 3b on the molybdenum plate 1 contaminated with carbon, sulfur, and oxygen were left in the air (sample numbers 2 to 9). Show. Sample No. 1 is a clean Ag sputter film surface.
  • the Ag sputtered film insert layer 3b and the Si pellet on the molybdenum plate 1 were left in the air as shown in the table.
  • Fig. 3 shows the relationship between the amount of contamination (C + S + 0) on the Ag sputtered film surface and the bonding rate and bonding strength.
  • FIG. 4 is a cross-sectional view showing a bonding insert layer according to the present invention.
  • the member 1 to be joined is a Ni-plated (thickness ⁇ ) molybdenum plate (thickness 0.1 mm, width 15 mm, length Prepare 15 mm) and Si ⁇ ⁇ let 2 (10 mm opening).
  • the molybdenum plate 1 is About 20 ⁇ of Cu plating is provided as the deformation layer 8 to promote deformation, and an Ag sputter film (thickness of 2 ⁇ ) is provided as the bonding insert layer 3a by sputtering. .
  • the hardness of the Cu plating film as the deformation layer 8 is about 75 ⁇ ⁇ , and the hardness of the Ag spitter film is about 55 HV.
  • the surface of the Ag sputtered film is composed of 12 at% of carbon and 2 at% of oxygen. Then, as shown in Fig.
  • the Cu-plated deformation layer 7 is provided on the molybdenum plate 1
  • the low-temperature solid-phase joint has a joining rate of about 100%, and a sound joint without any unjoined defects is formed.
  • FIG. 5 is a cross-sectional view of a main part of a GTO thyristor as a press-contact type semiconductor device according to the present invention
  • FIG. 6 is a cross-sectional view of a GTO thyristor as a press-contact type semiconductor device according to the present invention.
  • the force of the silicon wafer 9 (4 inches) of the GT 0 thyristor was used as the bonding insert layer 3 a on the source electrode 10 and the anode electrode 11. Then, an Ag sputtered film is formed to a thickness of 3 ⁇ m by a sputtering method.
  • the bonding insulator layer 3a and the surface 4a are 10 at% carbon and 2 at% oxygen.
  • a bonding insert layer is provided on the first Mo heat buffer plates 13 and 14 which are in contact with the cathode electrode 10 and the anode electrode 11 mounted on both main surfaces of the silicon wafer 9.
  • an Ag plating film of about 15 ⁇ m is formed by a plating method.
  • the surface 4b of the insert layer 3b of the Ag plating film for bonding has 13 at% of carbon, 4 at% of sulfur, and 2 at% of oxygen.
  • the bonding insert layer 3b which is the Ag plating film on the first Mo thermal buffer plate 13, the silicon wafer of the GTO thyristor, and the Ag sputtered film on the 9 cathode electrodes 10
  • the bonding insulator layer 3a is overlapped with the bonding insulator layer 3a, which is an Ag sputter film on the anode electrode 11 of the silicon wafer 9 of the GTO thyristor, and the IM layer.
  • the bonding insert layer 3b which is the Ag plating film on the heat buffer plate 14, is overlaid and set in the air between the heating block 5 and the pressure rod 6, and the bonding temperature is 230.
  • Bonding time 3 Oniin
  • Pressure 1.5kgfZmm 2
  • Low-temperature solid-state bonding Low-temperature solid-state bonding, and bonding of IM o heat buffer plates 13 and 14 to silicon wafer 9 via Ag bonding layer 7 Manufacture the body.
  • the bonded body of the first Mo heat buffer plates 13 and 14 and the silicon wafer 9 is connected to the second Mo heat buffer plates 16 and 1 through the Ag bonding layer 7. 7 and then assembled between the post electrodes 18 and 19, and the Cu gate electrode 20 is arranged and sealed and welded to produce a GT ⁇ thyristor.
  • the O-thyristor is composed of the cathode electrode 10 and the anode electrode 11 of the silicon wafer 9 and the first Mo heat buffer plates 13 and 14 formed of the Ag sputtering film and the Ag plating film.
  • the GTO thyristor formed by the low-temperature solid-state bonding method according to the present invention has a uniform structure because the IM o heat buffer plates 13 and 14 and the silicon wafer 9 are bonded to each other via the Ag bonding layer 7.
  • the current can be cut off in a short time, and damage to the silicon wafer 9 due to current concentration occurring at the time of the current cutoff can be prevented. Also, the pressure applied to the GTO thyristor can be reduced.
  • FIG. 7 is a cross-sectional view showing a process for manufacturing a power transistor according to the present invention.
  • the power transistor 24 with a 2 ⁇ Ag deposited film formed on the back surface of the Si pellet as a bonding sensor layer 3a was bonded to the stage surface 25.
  • a lead frame 26 having an Ag plating film formed at 5 ⁇ m is prepared.
  • AES analysis of the Ag plating film surface before and after the low-temperature solid-state bonding pretreatment revealed that the surface 4 b of the bonding Ag plating film insert layer 3 b formed on the stage surface 25 of the lead frame 26 was
  • the carbon is 64 at%
  • the sulfur is 16 at%
  • the oxygen is 5 at%. Therefore, when the pre-bonding treatment according to the present invention is performed, the Ag plating film, which is the bonding insulator layer 3b, has 16 at% of carbon, 5 at% of sulfur, and 3 at% of oxygen. Is removed, Be clean.
  • the Ag vapor-deposited film insert layer 3a on the back surface of the power transistor 24 has a surface 4a of 8 at% carbon and 2 at% oxygen.
  • the obtained power transistor is solid-phase bonded at a low temperature of 230 ° C., there is no heat distortion or warpage due to heating during bonding, and cracks generated in the power transistor can be prevented.
  • the low-temperature solid-phase joint has few defects such as poor joints and does not use solder.Therefore, the power transistor does not tilt and join, the occurrence of void defects is small, and the heat resistance is lower than before. small.
  • FIG. 8 is a sectional view showing the structure of the power module according to the present invention. As shown in FIG. 8, an Ag vapor-deposited film is formed on the back surface of the power transistor 24 as a bonding insert layer 3a. A molybdenum buffer plate 28 having an Ag plating film formed at 5 ⁇ as a bonding insulator layer 3 b on the stage 24 and the power transistor 24 having approximately 2 ⁇ formed is prepared.
  • the molybdenum buffer plate 28 on which a 5 m Ag-plated film was formed as the bonding insert layer 3b on the stage surface 25 was heated in air. Heat treatment: 250 ° C, time: 15 min.
  • the surface 4 b of the Ag plating film insert layer 3 b formed on the stage surface 25 of the molybdenum buffer plate 28 has a carbon content of 64 at% and a sulfur content of 16 at. %, Oxygen is 5 at%, which is very dirty. Therefore, when the pre-bonding treatment of the present invention is performed, the Ag plating film, which is the bonding insert layer 3b, has carbon
  • the Ag vapor deposited film insulator layer 3a on the back surface of the power transistor 24 has a surface 4a of 8 at% of carbon and 2 at% of oxygen.
  • the ceramic module 30 provided with the wiring board 29 and the wiring board 29 and the connection terminal 32 and the connection terminal 32 and the connection terminal 32 and the connection terminal 32 and the connection terminal 32 are connected together by the solder layer 33, and the power module To manufacture.
  • the resulting power module is solid-phase bonded at a low temperature of 230 ° C or less, so that it does not generate much distortion or warpage due to heating during bonding, and cracks generated in the power transistor 27 are small. Can be prevented.
  • the low-temperature solid-state joint has few defects such as poor joints and does not use solder.Therefore, the power transistor 27 is not inclined and joined, there is no void defect, and the thermal resistance is lower than before. small.
  • the power module according to the present invention is applicable only to the bonding between the back surface of the power transistor 24 and the surface of the molybdenum buffer plate 28 of the power module. Instead, the direct connection between the back surface of the power transistor 24 of the power module and the surface of the wiring board 29 b on the ceramic board 30, the wiring boards 29 a and 29 c on the ceramic board 30 and the connection terminals 3 In addition to joining with 2a and 32b, these joints can be made at the same time, and a power module with low maturation resistance can be manufactured.
  • FIG. 9 is a sectional view showing a manufacturing process of the BGA package according to the present invention.
  • an LSI chip 36 provided with an A1 electrode 35 on one side and a wiring board 38 provided with conductor wiring 37 are prepared.
  • a Au insert layer 3a for bonding is provided on the A1 electrode 35 of the LSI chip 36 at 0.5 ⁇ . Also, on the conductor wiring 37 provided on the wiring board 38, a protruding (diameter: 50 ⁇ m, thickness: 20 m) A1 deformable layer 39 is provided on the conductor wiring 37 provided on the wiring board 38. Layer 3 b is provided at 0.5 ⁇ . The surfaces 4a and 4b of these bonding Au insert layers 3a and 3b are clean surfaces with 8 at% carbon and 2 at% oxygen, as shown in Fig. 9 (C).
  • FIG. 10 is a cross-sectional view showing a manufacturing process of the liquid crystal display device according to the present invention.
  • a liquid crystal driver LSI 40 provided with an A1 electrode 35 on one side and a TAB tape 42 provided with an inner lead 41 are prepared.
  • a bonding Au insert layer 3a is provided on the A1 electrode 35 of the liquid crystal driver LSI 40 at 0.5 ⁇ .
  • a bonding Au insert layer 3b is provided on the inner lead 41 of the TAB tape 42 in a thickness of 0.5 ⁇ .
  • the surfaces 4a and 4b of these Au insert layers 3a and 3b for bonding are clean surfaces with 9 at% of carbon and 3 at% of oxygen.
  • the Au insert layer 3a for bonding on the A1 electrode 35 of the LCD driver LSI 40 and the inner lead 4 of the TAB tape 42 are shown in Fig. 10 (C). Align the upper Au insert layer 3b for bonding on 1 and bond in air under the conditions of bonding temperature: 150 ° C, bonding time: 1 s, pressure: 2.5kgfZ plate 2. At the same time, ultrasonic vibration (60 kHz, 0.5 W) is applied to perform low-temperature solid-state welding.
  • This liquid crystal display device is capable of low-temperature solid-state bonding, so that solid-state bonding is performed at low temperature, so there is little heat distortion or warpage due to heating during bonding, and cracks that occur in LSI chips can be prevented. Less thermal damage to the substrate. The deformation of the lead during joining is small, the pitch can be narrowed, and the connection resistance can be reduced.
  • FIG. 11 is a cross-sectional view of an ink jet printer head according to the present invention. It is an example.
  • the ink-jet printer head is composed of an orifice plate 44, a chamber plate 45, a filer plate 46, and a restrictor plate 47. , A diaphragm plate 48, a housing 49, a piezoelectric element 50, and a bonding agent 51, and an ink jet printer having a thin-plate laminated structure in which the respective components are connected by an Ag bonding layer 7. It is a head.
  • the sputtering method is applied to one side of the orifice plate 44, the chamber plate 45, the filter plate 46, the list plate plate 47, the both sides of the diaphragm plate 48 and one side of the housing 49.
  • an Ag sputtered film having a thickness of 10 ⁇ m is formed as a bonding insert layer.
  • the Ag sputtered film surface has 8 at% of carbon and 2 at% of oxygen.
  • the ink jet printer head manufactured by the low-temperature solid-state bonding method of the present invention has good corrosion resistance to a hot-melt type ink having high corrosivity, and has little occurrence of bonding defects such as unbonded. A good joint is formed.
  • low-temperature bonding at 150 to 300 ° C instead of solder bonding is possible, and thermal damage during bonding can be achieved.
  • One can be reduced as much as possible.
  • the press-contact type semiconductor device manufactured according to the present invention can uniformly cut off the current, and can prevent damage to the silicon wafer due to current concentration that occurs when the current is cut off. Further, the pressing force applied to the pressure contact type semiconductor device can be reduced.
  • the semiconductor device, power module and package manufactured by the present invention have low thermal resistance and can be mounted at high density.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

L'invention concerne une couche rapportée de soudage, qui est constituée d'Au, d'alliages Au, d'Ag, d'alliages Ag, de Pt, d'alliages Pt, de Pd ou d'alliages Pd. Ladite couche est fournie sur la surface de chacun de deux éléments qui vont être soudés, la surface de chaque couche rapportée de soudage ne contenant pas plus de 20 % at de carbone, 10 % at de soufre et pas plus de 5 % at d'oxygène. Les surfaces des couches rapportées de soudage sont mises en contact, et les deux éléments sont soudés l'un à l'autre en phase solide dans l'air atmosphérique ou dans une atmosphère ne contenant pas moins de 20 % d'oxygène à une température variant entre 150 et 300 °C.
PCT/JP1997/000841 1997-03-17 1997-03-17 Procede de soudage d'elements en phase solide WO1998041354A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/000841 WO1998041354A1 (fr) 1997-03-17 1997-03-17 Procede de soudage d'elements en phase solide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/000841 WO1998041354A1 (fr) 1997-03-17 1997-03-17 Procede de soudage d'elements en phase solide

Publications (1)

Publication Number Publication Date
WO1998041354A1 true WO1998041354A1 (fr) 1998-09-24

Family

ID=14180224

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/000841 WO1998041354A1 (fr) 1997-03-17 1997-03-17 Procede de soudage d'elements en phase solide

Country Status (1)

Country Link
WO (1) WO1998041354A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002239752A (ja) * 2001-02-15 2002-08-28 Yazaki Corp 金属同士の接合方法
JP2002353378A (ja) * 2001-05-22 2002-12-06 Fuji Electric Co Ltd 半導体装置
JP2003520685A (ja) * 2000-01-31 2003-07-08 ピコジェット インコーポレイテッド ミクロ流体装置及び超音波結合プロセス
JP2009028729A (ja) * 2007-07-24 2009-02-12 Bondtech Inc 超音波振動接合方法およびこの方法により形成されたデバイス並びに超音波振動接合装置
JP2011235300A (ja) * 2010-05-07 2011-11-24 Musashino Eng:Kk 原子拡散接合方法
JP2013140849A (ja) * 2011-12-28 2013-07-18 National Institute Of Advanced Industrial & Technology 半導体チップ、半導体モジュール、及び半導体チップ実装方法
KR20150060666A (ko) * 2012-09-28 2015-06-03 에베 그룹 에. 탈너 게엠베하 기판을 코팅 및 본딩하기 위한 방법
KR20180101034A (ko) 2017-03-03 2018-09-12 주식회사 엘지화학 박판을 이용한 리드 단선을 개선하는 파우치형 이차전지 및 그 제조방법
WO2021071060A1 (fr) * 2019-10-11 2021-04-15 삼성디스플레이 주식회사 Élément adhésif, dispositif d'affichage le comprenant, et procédé de fabrication de dispositif d'affichage

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541740A (en) * 1978-09-20 1980-03-24 Hitachi Ltd Airtight seal device
JPH01256140A (ja) * 1988-03-03 1989-10-12 Siemens Ag 基板に半導体デバイスを固着する方法及び装置
JPH06244342A (ja) * 1993-02-16 1994-09-02 Hitachi Cable Ltd 複合リードフレームおよびその製造方法
JPH06509908A (ja) * 1991-08-14 1994-11-02 ベル　コミュニケーションズ　リサーチ　インコーポレーテッド 半導体のパラジウム溶接
JPH07211722A (ja) * 1994-01-26 1995-08-11 Toshiba Corp 半導体装置及び半導体装置実装構造体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541740A (en) * 1978-09-20 1980-03-24 Hitachi Ltd Airtight seal device
JPH01256140A (ja) * 1988-03-03 1989-10-12 Siemens Ag 基板に半導体デバイスを固着する方法及び装置
JPH06509908A (ja) * 1991-08-14 1994-11-02 ベル　コミュニケーションズ　リサーチ　インコーポレーテッド 半導体のパラジウム溶接
JPH06244342A (ja) * 1993-02-16 1994-09-02 Hitachi Cable Ltd 複合リードフレームおよびその製造方法
JPH07211722A (ja) * 1994-01-26 1995-08-11 Toshiba Corp 半導体装置及び半導体装置実装構造体

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003520685A (ja) * 2000-01-31 2003-07-08 ピコジェット インコーポレイテッド ミクロ流体装置及び超音波結合プロセス
JP4795601B2 (ja) * 2000-01-31 2011-10-19 ネクストジェット エルエルシー ミクロ流体装置及び超音波結合プロセス
JP2002239752A (ja) * 2001-02-15 2002-08-28 Yazaki Corp 金属同士の接合方法
JP2002353378A (ja) * 2001-05-22 2002-12-06 Fuji Electric Co Ltd 半導体装置
JP2009028729A (ja) * 2007-07-24 2009-02-12 Bondtech Inc 超音波振動接合方法およびこの方法により形成されたデバイス並びに超音波振動接合装置
JP2011235300A (ja) * 2010-05-07 2011-11-24 Musashino Eng:Kk 原子拡散接合方法
JP2013140849A (ja) * 2011-12-28 2013-07-18 National Institute Of Advanced Industrial & Technology 半導体チップ、半導体モジュール、及び半導体チップ実装方法
KR20150060666A (ko) * 2012-09-28 2015-06-03 에베 그룹 에. 탈너 게엠베하 기판을 코팅 및 본딩하기 위한 방법
JP2016500750A (ja) * 2012-09-28 2016-01-14 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板をコーティングする方法及び基板を接合する方法
KR101963933B1 (ko) 2012-09-28 2019-03-29 에베 그룹 에. 탈너 게엠베하 기판을 코팅 및 본딩하기 위한 방법
KR20180101034A (ko) 2017-03-03 2018-09-12 주식회사 엘지화학 박판을 이용한 리드 단선을 개선하는 파우치형 이차전지 및 그 제조방법
WO2021071060A1 (fr) * 2019-10-11 2021-04-15 삼성디스플레이 주식회사 Élément adhésif, dispositif d'affichage le comprenant, et procédé de fabrication de dispositif d'affichage
US12061399B2 (en) 2019-10-11 2024-08-13 Samsung Display Co., Ltd. Adhesive member and display device comprising adhesive member and method for manufacturing

Similar Documents

Publication Publication Date Title
TW592871B (en) Solder foil and semiconductor device and electronic device
TWI428967B (zh) 熱機械倒裝晶片接合法
JP3736452B2 (ja) はんだ箔
EP2006895A1 (fr) Module de composant electronique
US20110042815A1 (en) Semiconductor device and on-vehicle ac generator
TW200829361A (en) Connecting material, method for manufacturing connecting material, and semiconductor device
JP2004174522A (ja) 複合はんだ、その製造方法および電子機器
JP2007152385A (ja) 高温半田及び高温半田ペースト材、及びそれを用いたパワー半導体装置
JP2006032888A (ja) 半導体装置および半導体装置の製造方法
US6255002B1 (en) Soldering of a semiconductor chip to a substrate
JPH07169875A (ja) 電子回路装置及びその製造方法及び回路基板及び液晶表示装置及びサーマルヘッド及びプリンタ
JP3627591B2 (ja) パワー半導体モジュールの製造方法
WO2000019514A1 (fr) Boitier de semiconducteur et procede correspondant de soudage de puce
WO1998041354A1 (fr) Procede de soudage d'elements en phase solide
JP3447690B2 (ja) 半導体チップの積層実装方法
JP3356649B2 (ja) 半導体装置及びその製造方法
JP2005311284A (ja) パワー半導体素子およびこれを用いた半導体装置
JP4432541B2 (ja) 電子機器
JPH04196333A (ja) 固相接合方法および装置
JPH11307596A (ja) 低温接合方法
JP2003092306A (ja) 半導体装置及びその製造方法
JP3284055B2 (ja) 半導体素子、半導体装置、および半導体装置の検査方法
JP2001110823A (ja) 半導体装置の製造方法
JPH10308415A (ja) 電極、電子部品、電子装置および電子部品の実装方法
JPH11145188A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase