Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
  • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73201—Location after the connecting process on the same surface
  • H01L2224/73203—Bump and layer connectors
  • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01047—Silver [Ag]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01058—Cerium [Ce]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/014—Solder alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/06—Polymers
  • H01L2924/078—Adhesive characteristics other than chemical
  • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
  • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10734—Ball grid array [BGA]; Bump grid array
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
  • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the present invention relates to a surface-mount type semiconductor device, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted.
• BGA ba11 grid array
• BGA packages are classified into several types depending on the base material of the substrate.In particular, there is a need to mount semiconductor elements with narrow pitch pads, and continuity can be achieved by manufacturing in the form of tape in manufacturing.
• BGA package using a flexible tape that uses a flexible (flexible) substrate as the substrate of the substrate due to the demand for manufacturing efficiency.
• bumps which are external terminals, are arranged in an array on a flexible substrate so that they can be surface-mounted.
• the wiring pattern that connects the chip electrodes to the bumps is formed exposed on the flexible substrate, and when mounted on a circuit board, care must be taken not to degrade the quality of the wiring pattern. It needed to be handled.
• connection state of the bump and the pad of the circuit board not only cannot the connection state of the bump and the pad of the circuit board be confirmed and inspected, but also the connection cannot be repaired even if there is a connection failure, so that high precision mounting is required.
• the flexible substrate used for the BGA package may be warped due to its flexibility, making it difficult to mount.
• the conventional BGA package has various problems during mounting.
• An object of the present invention is to solve this problem, and an object of the present invention is to provide a surface-mount type semiconductor device which enables easy mounting, a method of manufacturing the same, a method of mounting the same, and a circuit board on which the same is mounted. It is in. Disclosure of the invention
• a semiconductor device includes: a semiconductor element
• An external terminal provided on the other surface side of the insulating film and electrically connected to the wiring pattern via the through hole;
• a holding plate made of a member having conductivity and maintaining flatness, provided on the opposite side of the surface of the wiring pattern on which the insulating film is provided, so as to cover at least a part of the wiring pattern.
• the holding plate is attached to the insulating film via an insulating adhesive, and is connected to a constant potential portion of the wiring pattern.
• the wiring pattern forming surface side and the bump forming surface side are different from each other with the insulating film as a boundary, there is no obstacle other than the wiring pattern on the wiring pattern forming surface side. Therefore, since the holding plate can be used as it is without special processing (patterning) to cover the wiring pattern, the manufacturing operation becomes extremely easy.
• the insulating plate is not only capable of protecting the surface of the wiring pattern but also having sufficient strength to maintain flatness and covering the insulating film, the flexible insulating film is not distorted, and the planar stability of the bump is improved. The yield of mounting on a circuit board is improved.
• the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern.
• the constant potential portion is a portion having a potential that does not change during operation of the semiconductor device. Minutes.
• a short circuit between the conductive holding plate and the wiring pattern can be prevented by the insulating adhesive.
• the holding plate has a constant potential
• a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that an ideal transmission path is formed, and the impedance, particularly the inductance, is reduced. Small transmission is possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
• a protective layer covering the wiring pattern may exist between the holding plate and the wiring pattern.
• a protective layer such as a resist is provided in advance on the entire surface of the wiring pattern on the side where the insulating film is not provided and on which the holding plate is to be attached, and the holding plate is further attached thereon with an adhesive. May be attached. Also in this case, since a protective layer is provided on the surface opposite to the surface on which the external terminals are formed in the wiring pattern, it is easy to apply a resist or the like. In addition, when the holding plate is provided, since the wiring pattern is protected in advance by the protective layer, there is no occurrence of a defect in the wiring pattern such as disconnection.
• the constant potential section may be one of a power supply potential and a ground potential.
• the wiring pattern may have a curved portion at least in part, and the curved portion may be connected to the holding plate.
• the holding plate may be connected to a fixed potential portion of the wiring pattern by at least one of a solder and a conductive adhesive.
• a semiconductor device includes a semiconductor element, an insulating film, a wiring pattern formed on the insulating film and connected to the semiconductor element, and an external terminal formed on the wiring pattern.
• a holding plate made of a member having conductivity and maintaining flatness, and holding a part of the insulating film;
• the holding plate is connected to a constant potential portion of the wiring pattern.
• the provision of the holding plate allows the flexible insulating film to be warped. Can be prevented, and reliable mounting becomes possible.
• the holding plate has conductivity and is connected to a constant potential portion of the wiring pattern.
• the constant potential portion is a portion having a potential which does not change during operation of the semiconductor device.
• the holding plate has a constant potential
• a signal is transmitted to the wiring pattern along the planar constant potential formed by the holding plate, so that it becomes an ideal transmission path, and the impedance is particularly high. Transmission with small inductance becomes possible. Then, the delay and dullness of the high-frequency signal are reduced, the transmission characteristics are improved, and a highly reliable semiconductor device can be obtained.
• the holding plate a member having a thermal expansion coefficient larger than that of the insulating film may be used.
• the holding plate may have a slit or a groove, and an end of the insulating film may be inserted into the slit or the groove and held by the holding plate.
• the insulating film may have a slit, and the holding plate may be attached to an opposite side of the insulating film via the slit so that an end protrudes.
• a method for manufacturing a semiconductor device includes the steps of: forming a through hole in an insulating film;
• the bumps protrude from the side opposite to the wiring pattern, and the holding plate covers the wiring pattern.
• the holding plate has the same potential as a part of the wiring pattern, and the holding plate is planar, so that electrical connection with low impedance is possible.
• the holding plate may be attached to the insulating film via an insulating adhesive.
• the insulating film has an opening corresponding to the wiring pattern
• a part of the wiring pattern may be bent and connected to the holding plate by pushing a pressing jig from the other surface of the insulating film through the opening.
• a step of forming a wiring pattern on an insulating film a step of connecting a semiconductor element to the wiring pattern and providing the semiconductor element on the insulating film, and holding an end of the insulating film Attaching a holding plate, and electrically connecting a part of the wiring pattern to the holding plate.
• the semiconductor device manufactured by this method warpage of the flexible insulating film can be prevented, and reliable mounting becomes possible. Further, since a part of the wiring pattern is electrically connected to the holding plate, a semiconductor device having a structure which is hardly affected by external noise can be obtained.
• a circuit board according to the present invention includes: the semiconductor device described above; and a substrate on which a desired conductive pattern is formed.
• the external terminal of the semiconductor device is connected to the conductive pattern.
• the semiconductor device since the holding plate has a constant potential, the semiconductor device is arranged on a plane having a constant potential. As a result, the semiconductor device has a structure that is less susceptible to external noise, such as a coaxial cable.
• a circuit board includes: a semiconductor element; an insulating film; a wiring pattern formed on the insulating film and connected to the semiconductor element; A semiconductor material comprising: a bump formed on the substrate; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
• this circuit board at least the end of the insulating film is fixed, so that the warpage is prevented. Further, since the wiring pattern and the holding plate are electrically connected, a structure that is not easily affected by external noise can be obtained.
• a mounting method of a semiconductor device includes: an insulating film on which solder bumps are formed; and a holding member made of a member having conductivity and maintaining planarity and electrically connected to the wiring pattern.
• electrical connection by solder can be performed after the insulating film is fixed with an adhesive to eliminate the warpage of the insulating film. Also, since the wiring pattern and the holding plate are electrically connected, a structure that is less susceptible to external noise can be obtained.
• FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment
• FIG. 2 is a diagram illustrating a semiconductor device according to a second embodiment
• FIGS. 3A and 3B are diagrams illustrating a third embodiment
• FIG. 4 is a diagram showing a semiconductor device according to a modification of the fourth embodiment.
• FIG. 4 is a diagram showing another modification of the fourth embodiment.
• FIGS. 5A to 5C are diagrams showing the fifth embodiment and its modifications.
• FIG. 6 is a diagram illustrating a semiconductor device according to an example
• FIG. 6 is a diagram illustrating a semiconductor device according to a sixth embodiment
• FIG. 7 is a diagram illustrating a semiconductor device according to a seventh embodiment
• FIG. 9 is a diagram illustrating a semiconductor device according to an eighth embodiment.
• FIG. 9 is a diagram illustrating a semiconductor device according to a ninth embodiment.
• FIG. 10 is a diagram illustrating a semiconductor device according to the tenth embodiment.
• FIG. 11 is a diagram showing a circuit board according to the first embodiment
• FIG. FIG. 12B is a diagram showing a circuit board according to an embodiment.
• FIG. 12B is a diagram showing a modification of the first embodiment.
• FIG. 13 is a diagram showing a semiconductor device manufactured by applying the method according to the present invention.
• FIG. 14 is a diagram illustrating a circuit board on which the device is mounted, and
• FIG. 14 is a diagram illustrating an electronic apparatus including the circuit board on which the semiconductor device manufactured by applying the method according to the present invention is mounted.
• FIG. 1 is a diagram illustrating a semiconductor device according to the first embodiment.
• This semiconductor device 10 is one to which a BGA package is applied. That is, in the figure, a large number of bumps 14 are formed on the insulating film 12, and a wiring pattern 20 that connects the electrodes 18 of the semiconductor chip 16 and the bumps 14 is formed.
• the insulating film 12 is obtained by punching a long film carrier, and uses TAB (Tape Automated Bonding) technology.
• the insulating film 12 has a through hole 12a.
• the through hole 12 a is formed on the wiring pattern 20 formed on one surface of the insulating film 12.
• the bumps 14 are formed so as to protrude from the wiring pattern 20 to the other surface of the insulating film 12 via the through holes 12a. That is, the bumps 14 protrude from the surface opposite to the wiring pattern 20. By doing so, the wiring pattern 20 is not exposed on the side where the bumps 14 are formed.
• the bump 14 is formed of, for example, solder and the upper portion is formed in a ball shape.
• the bumps 14 may be integrally formed using solder to the inside of the through-hole 12a, or another conductive member may be provided at least in the through-hole 12a and the solder may be mounted thereon. Further, other than solder, for example, copper or the like may be used.
• device holes 12b are formed in the insulating film 12, and the ends of the wiring patterns 20 project into the device holes 12b.
• the device hole 12 b is used for connecting the wiring pattern 20 and the electrode 18 of the semiconductor chip 16. That is, the side of the insulating film 12 where the wiring pattern 20 is formed
• the semiconductor chip 16 is arranged so that the electrode 18 is located on the surface and inside the device hole 12b, and the wiring pattern 20 and the electrode 18 are bonded.
• connection region between the semiconductor chip 16 and the insulating film 12 is sealed by the epoxy resin 22.
• a feature of the present embodiment is that a holding plate 24 is provided on the insulating film 12. Specifically, the holding plate 24 is attached onto the wiring pattern 20 via an insulating adhesive 26.
• the holding plate 24 may be made of stainless steel, but is preferably made of highly conductive copper or a copper-based alloy.
• the wiring pattern 20 is covered and protected by the insulating adhesive 26 and the holding plate 24.
• the insulating adhesive 26 becomes a protective layer similar to the solder resist.
• the insulating adhesive 26 may be formed as a thermosetting or thermoplastic film, and may be attached to the holding plate 24 in advance. Then, the holding plate 24 can be thermocompression-bonded to the surface of the insulating film 12 having the wiring pattern 20.
• the holding plate 24 By providing the holding plate 24 in this way, the distortion and undulation of the insulating film 12 are eliminated, the height of the bumps 14 becomes constant, the planar stability is improved, and the mounting yield on the circuit board is reduced. improves.
• the holding plate 24 may be provided with a resist on the wiring pattern 20 and then pasted thereon via an insulating adhesive. By doing so, it is possible to prevent the holding plate 24 from being stuck with the impurities remaining therein.
• a projection 24a is formed on the holding plate 24, and the projection 24a is connected to a constant potential of the wiring pattern 20, for example, a GND potential or a power supply potential.
• a GND potential or a power supply potential for example, a GND potential or a power supply potential.
• the protrusion 24a is shown only at one position in the drawing, it may be provided at all portions of the wiring pattern 20 where the potential is constant.
• the holding plate 24 has the same potential as the potential of the wiring pattern 20 connected via the projection 24a.
• the wiring pattern 20 is formed on the holding plate 24 via the insulating adhesive 26. Is disposed above a planar constant potential.
• the constant potential is the GND potential
• a high-frequency signal can be transmitted to the wiring pattern 20 along the planar GND potential, so that an ideal transmission path like a coaxial cable is obtained. That is, the impedance pattern of the wiring pattern 20 can be controlled.
• the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
• a wiring pattern 20 is formed on the surface of the insulating film 12 on the side of the holding plate 24 to reduce the distance between the two. By doing so, the distance between the wiring pattern 20 and the holding plate 24 is reduced.
• the capacitance is C
• the area of the wiring pattern 20 and the holding plate 24 facing each other is S
• the distance between the wiring pattern 20 and the holding plate 24 is d
• the dielectric constant in a vacuum is £.
• the relative permittivity £
• the portion of the wiring pattern 20 that becomes the power supply potential and the holding plate 24 may be connected by the projection 24a. Even in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 20 can be reduced.
• B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element. This point is common to all embodiments described later.
• the present embodiment is a back TAB type in which the semiconductor chip 16 is mounted on the same side of the insulating film 12 as the wiring pattern 20 forming surface, but the semiconductor chip 16 is provided on the opposite side of the wiring pattern 20 forming surface. Table with 16 mounted.
• the semiconductor chip 16 since the back surface of the semiconductor chip 16 comes into contact with the circuit board, if the semiconductor chip 16 is connected to the circuit board via a heat conductive adhesive such as silver paste, the heat dissipation of the semiconductor chip 16 can be reduced. Can be raised.
• a bump may be provided in the wiring pattern 20 without forming the through hole 12a in the insulating film 12, and a solder resist layer may be formed on the wiring pattern 20 side avoiding the bump.
• FIG. 2 is a diagram illustrating a semiconductor device according to the second embodiment.
• the semiconductor device 30 shown in FIG. 2 differs from the semiconductor device 10 shown in FIG. 1 in the structure of the electrical connection between the wiring pattern 32 and the holding plate 34. That is, in FIG. 2, the extended portion 32 a at the left end of the wiring pattern 32 is bent and connected to the holding plate 34.
• As a connection method there is a method shown in a third embodiment described later.
• the extension part 32 a is provided in a part of the wiring pattern 32 where the potential becomes the GND potential.
• the extension 32a is shown only at one end in the figure, it may be provided at any part of the wiring pattern 32 that is at the GND potential. It may be provided at any position.
• the holding plate 34 is made of copper or the like having high conductivity and good heat conductivity.
• the holding plate 34 has the same potential as the potential of the wiring pattern 32 connected via the extension 32a, that is, the GND potential. Then, the wiring pattern 32 is disposed above the planar GND potential formed by the holding plate 34 via the insulating adhesive 36. Then, a high-frequency signal can be transmitted to the wiring pattern 32 along the planar GND potential, so that an ideal transmission path is obtained as in a coaxial cable. That is, the impedance inductance of the wiring pattern 32 can be controlled. Since the impedance and inductance are caused by the adhesive and the resist layer (if provided), they can be controlled by changing the thickness. As a result of the control, the transmission characteristics can be improved by reducing the delay and dullness of the high-frequency signal.
• the part that becomes the power supply potential of the wiring pattern 32 may be connected to the extension plate 32a. Also in this case, since the power supply potential is constant, the influence on the signal transmitted to the wiring pattern 32 can be reduced.
• FIG. 3A and FIG. 3B are views showing a modified example viewed from the joining means of the second embodiment.
• a part of the wiring pattern 42 is bent to form a projection 42 a, and the projection 42 a is connected to the holding plate 44.
• the protrusion 42 a is formed in a portion of the wiring pattern 42 where the potential becomes a constant potential such as a GND potential or a power supply potential.
• the projection 42 a is formed by pressing the pressing jig 48 from the hole 46 a formed in the insulating film 46. That is, a hole 46 a is previously formed in the insulating film 46 corresponding to a portion of the wiring pattern 42 where the convex portion 42 a is to be formed, and the holding plate 44 4 is formed from the hole 46 a.
• the wiring pattern 42 is pressed by the pressing jig 48 to form a projection 42 a and is joined to the holding plate 44.
• the insulating adhesive 45 be removed from the region where the convex portion 42 a is to be formed. Further, when forming the projection 42 a, heat or ultrasonic vibration is applied from the pressing jig 48. Further, the wiring pattern 42 is plated with gold (A n). As the wiring pattern 42, a well-known tin plate or solder plate may be used other than the gold plating. On the other hand, if the metal plate is also provided on the holding plate 44, the joining between the projection 42 a and the holding plate 44 becomes easy.
• a wiring pattern 52 and a holding plate 54 are connected by a conductive adhesive 56.
• the insulating adhesive 55 is removed and a conductive adhesive 56 is provided corresponding to the portion of the wiring pattern 52 connected to the holding plate 54, and the holding plate 54 is insulated.
• solder may be used instead of the conductive adhesive 56. In this case, when the holding plate 54 and the insulating film 58 are thermocompression-bonded, they are heated to the melting point of the solder. Need to be
• B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
• FIG. 4 is a diagram showing another modified example of the third embodiment, and is an example of the so-called “B-TAB type” mentioned above.
• the wiring pattern 62 of the semiconductor device 60 shown in the figure includes a projection 62 for connecting to the electrode 64a of the semiconductor chip 64 and a projection 62 for connecting to the conductive holding plate 66. has b.
• the semiconductor chip 64 is molded with a resin 65. By doing so, it is possible to connect the GND potential or the power supply potential in the wiring pattern 62 to the holding plate 66.
• the projections 62b and the holding plate 66 are simultaneously connected when the holding plate 66 is attached to the insulating film 68 having the wiring pattern 62 by thermocompression bonding.
• the other configuration is the same as that of the embodiment shown in FIG.
• FIG. 5A to 5C are views showing a semiconductor device according to the fifth embodiment.
• the semiconductor device 100 shown in FIG. 5A has an insulating film 104, a wiring pattern 106, a bump 108 and a semiconductor chip 109, and has an insulating film 104 and a wiring pattern 106.
• the end is held by the holding plate 102.
• the holding plate 102 is made of a highly conductive material.
• the end of the insulating film 104 is held by inserting the end of the insulating film 104 into the groove 102 a formed in the holding plate 102.
• the wiring pattern 106 is held by the holding plate 102 and is electrically connected. Note that the portion of the wiring pattern 106 connected to the holding plate 102 is the same as in the first embodiment, and the effect of the electrical connection is the same, so the description is omitted.
• the holding plate 102 has the strength necessary to maintain the flatness, while the insulating film 104 has flexibility. Therefore, the end of the insulating film 104 is By holding the flexible insulating film 104, the flexible insulating film 104 can maintain flatness. Then, the warpage of the insulating film 104 can be suppressed, and the mounting can be performed reliably. Also,
• the tension is applied to the insulating film 104 by the holding plate 102 so that the insulating film 104 is stretched in one step of the riff opening when the semiconductor device 100 is mounted on the circuit board.
• flatness can be obtained, so that the bump 108 can be securely mounted on the circuit board.
• B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
• a space exists between the holding plate 102 and the insulating film 104, but the space may not exist.
• FIG. 5B shows a modification of the fifth embodiment.
• the semiconductor device 110 shown in the figure has a point that the insulating film 114 and the end of the wiring pattern 116 are inserted into the slit 112a formed on the holding plate 112. Different from the above semiconductor device 100 o
• FIG. 5C also shows a modification of the fifth embodiment.
• the semiconductor device 120 shown in the figure has the end of the insulating film 124 inserted into the slit 124 a formed on the insulating film 124 by inserting the end of the holding plate 122. Part is held. Specifically, the end of the holding plate 122 is inserted from one surface of the insulating film 124 through the slit 124a into the other surface by elastically deforming the end of the holding plate 122. The flatness of the insulating film 124 is maintained by the restoring force. Also, by doing so, the holding plate 122 and the wiring pattern 126 are electrically connected.
• B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
• the semiconductor device 70 shown in FIG. 6 differs from the above-described fourth embodiment in that the holding plate 72 and the insulating film 74 are entirely fixed by an adhesive 73.
• the insulating film 74 is tensioned by the holding plate 72, and the insulating film 74 is stretched. Therefore, the solder balls 75 can be securely mounted on the circuit board.
• the structure of the electrical connection between the wiring pattern 71 and the holding plate 72 is the same as the composition shown in FIG.
• the end 78 a of the holding plate 78 is caulked in the direction shown by the arrow with respect to the ends of the insulating film 80 and the wiring pattern 81.
• the holding plate 78 and the insulating film 80 are fixed, and the electrical connection between the wiring pattern 81 and the holding plate 78 is achieved.
• the holding plate 78 can be stably mounted without using an adhesive in the mass production process.
• the holding plate 84 has a projection 84 a such as a pin, a hole 86 a is formed in the insulating film 86, and a hole 87 a is formed in the wiring pattern 87. It is formed.
• the holding plate 84 is attached to the insulating film 86 by fitting the projection 84a with the hole 86a and the hole 87a. Further, the diameter of the hole 87a is formed slightly smaller than that of the hole 86a, so that the electrical connection between the wiring pattern 87 and the holding plate 87 can be ensured.
• the projection 84a may be formed by bending an end of the holding plate 84. Also in this case, the holding plate 84 can be stably mounted without using an adhesive in the mass production process.
• the semiconductor device 90 shown in FIG. 9 is different from the semiconductor device 10 shown in FIG. Predder) 9 1 is attached. More specifically, an adhesive 92 is applied to the back surface of the semiconductor chip 16 (the surface opposite to the electrode 18) and the holding plate 24, and the heat dissipation plate 91 is adhered.
• the adhesive 92 contains silver or the like and has high thermal conductivity and conductivity, and the heat sink 91 is also made of a material having high thermal conductivity and conductivity. By doing so, heat dissipation of the semiconductor chip 16 can be promoted by the heat sink 91, and the back surface of the semiconductor chip 16 can be connected to a constant potential. Then, malfunction of the semiconductor chip 16 is prevented, and reliability is improved.
• the semiconductor device 94 shown in FIG. 10 has a holding plate 93 in which these are integrated instead of the holding plate 24 and the heat radiating plate 91 of the semiconductor device 90 shown in FIG. That is, the holding plate 93 includes a portion to be attached to the insulating film 12 and a semiconductor chip.
• the part to be attached to the back of 16 has a shape that is bent so that it becomes more physical. Even when such a holding plate 93 is used, the same effect as in the above embodiment can be obtained.
• FIG. 11 is a diagram illustrating a circuit board according to the eleventh embodiment.
• a semiconductor device 132 is mounted on a circuit board 130 shown in FIG.
• the semiconductor device 13 2 has an insulating film 13 4, a wiring pattern 13 6, a bump 13 8, and a semiconductor chip 13 9, and a circuit board 13 0 for bonding the bump 13 8.
• a pad 130a is formed.
• a holding plate 133 is attached to the insulating film 134.
• the semiconductor device 132 is bonded to the circuit board 130 by an adhesive 128 provided at the end and the center of the insulating film 134. This bonding is performed one step before the lift opening. That is, the semiconductor device 132 is temporarily bonded to the circuit board 130 with an adhesive 128 to eliminate the warpage of the insulating film 134, and then the bump 133 and the pad 1 are removed. Join with 30a.
• adhesive 128 it reacts at a temperature below the solder melting temperature. It is preferable that an adhesive 128 connects the semiconductor device 132 first and then the solder is melted using a corresponding material. In this way, so-called temporary fixing is performed.
• the adhesive film 128 is used to eliminate the warpage of the insulating film 134, so that good mounting is possible.
• a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
• the present embodiment has the holding plate 133, flatness can be maintained even if the holding plate 133 is omitted.
• FIG. 12A is a diagram showing a circuit board according to the 12th embodiment.
• a semiconductor device 142 is mounted on a circuit board 140 shown in FIG.
• the semiconductor substrate 144 is the same as the semiconductor device 10 shown in FIG. 1 except for the holding plate 144, and therefore the description is omitted.
• the holding plate 144 is made of a highly conductive material such as copper-stainless steel or a copper-based alloy, and has a hole 144a through which the screw 144 passes. This screw 1 4 6 also has conductivity.
• the circuit board 140 also has a hole 140a through which the conductive screw 144 passes. On one surface, a ring-shaped pad 1 is formed around the hole 140a. 4 8 are formed. The pad 148 is connected to a constant potential such as a GND potential or a power supply potential on the circuit board 140. Then, the holding plate 144 and the circuit board 140 are fixed by screws 144 and nuts 149 that pass through the respective holes 144a and 140a.
• the planar holding plate 144 becomes a constant potential such as the GND potential or the power supply potential via the screw 144.
• a signal can be transmitted along a planar constant potential, so that the transmission characteristics of a high-frequency signal are improved.
• FIG. 12B is a diagram showing a modification of the 12th embodiment.
• a pad 152 formed on a circuit board 150 and a holding plate 154 are connected by wires 156.
• the pads 15 2 are connected to a constant potential. Therefore, the holding plate 154 also has a constant potential, and the transmission characteristics of high-frequency signals are improved.
• the wires 156 are provided by soldering or by a normal wire bonding method, for example, ultrasonic waves. After that, the wire may be protected with a resin. Note that a so-called B-TAB type in which a projection is integrally formed on the wiring pattern side may be used for bonding with the semiconductor element.
• FIG. 13 shows a circuit board 1000 on which a semiconductor device 110 to which the present invention is applied is mounted.
• an organic substrate such as a glass epoxy substrate is used for the circuit board.
• Wiring patterns made of, for example, copper are formed on the circuit board so as to form a desired circuit, and the electrical continuity is achieved by mechanically connecting the wiring patterns and the bumps of the semiconductor device.
• the semiconductor device described above is provided with a structure that absorbs the strain caused by the difference in thermal expansion with the outside, the reliability at the time of connection and thereafter can be improved even if the semiconductor device is mounted on a circuit board. Can be improved.
• the wiring of the semiconductor device is devised, the reliability at the time of connection and after the connection can be improved.
• the mounting area can be reduced to the area mounted with bare chips. For this reason, if this circuit board is used for an electronic device, the size of the electronic device itself can be reduced. Also, within the same area, more mounting space can be secured, and higher functionality can be achieved.
• FIG. 1 As an electronic apparatus including the circuit board 100, a notebook personal computer 1200 is shown in FIG.
• the present invention can be applied to any electronic device for surface mounting that requires a large number of bumps, similarly to a semiconductor device, regardless of whether it is an active component or a passive component.
• the electronic part P port P includes, for example, a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a ballis, a volume or a fuse,

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Wire Bonding (AREA)

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Cited By (1)

Citations (4)

• 1998
  • 1998-01-28 AU AU56782/98A patent/AU5678298A/en not_active Abandoned
  • 1998-01-28 JP JP53555498A patent/JP3586867B2/ja not_active Expired - Fee Related
  • 1998-01-28 WO PCT/JP1998/000338 patent/WO1998036450A1/ja active Application Filing
  • 1998-02-05 TW TW087101525A patent/TW393708B/zh not_active IP Right Cessation

Patent Citations (4)

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