KR20000048471A - 다수의 전원/접지면을 갖는 볼 그리드 어레이 패키지 - Google Patents
다수의 전원/접지면을 갖는 볼 그리드 어레이 패키지 Download PDFInfo
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- KR20000048471A KR20000048471A KR1019990065649A KR19990065649A KR20000048471A KR 20000048471 A KR20000048471 A KR 20000048471A KR 1019990065649 A KR1019990065649 A KR 1019990065649A KR 19990065649 A KR19990065649 A KR 19990065649A KR 20000048471 A KR20000048471 A KR 20000048471A
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Abstract
Description
Claims (21)
- 플립 칩 상호접속된 집적 회로용 캐비티 다운 볼 그리드 어레이(BGA) 패키지에 있어서,a) 평면 보강재 또는 패키지 베이스,b) 제2 패터닝된 도전층으로부터 유전체층에 의해 분리된 제1 패터닝된 도전층을 갖는 제1 표면을 갖춘 삽입 회로(interposer circuit) -제2 표면이 절연 접착제에 의해 상기 보강재에 부착되고, 상기 제1 표면은 플립 칩 커넥터에 정렬된 복수의 콘택트 패드 및 상기 삽입 회로 주변에 입력/출력 콘택트 패드의 어레이에의 전기적 상호접속을 포함함-,c) 상기 삽입 회로 주변에 상기 입력/출력 콘택트 패드의 어레이의 각 콘택트상의 납땜 볼,d) 외부 에지가 상기 보강재의 외부 에지에 수직으로 정렬되어 배치된 프레임 -상기 프레임은 정렬된 제1 표면을 갖고, 프레임 코어를 통해 도전성 비아에 대한 상기 삽입 회로의 주변에 납땜 볼의 어레이를 상기 프레임의 상기 제2 표면상의 외부 BGA 납땜 볼 콘택트에 접속시킴-,e) 플립 칩 범프 및 프레임 납땜 범프 커넥터를 둘러싸는 언더필(underfill) 재료,f) 상기 프레임 및 상기 보강재에 의해 형성되는 캐비티를 채우는 포장 화합물을 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 플립 칩 상호접속된 집적 회로 칩용 캐비티 다운 볼 그리드 어레이(BGA) 패키지에 있어서,a) 평면 보강재 또는 패키지 베이스,b) 플립 칩 커넥터에 정렬된 복수의 콘택트 패드 및 삽입 회로 주변에 입력/출력 콘택트 패드의 어레이에의 전기적 상호접속을 포함하는 제1 표면상에 도전성 트레이스(trace)를 갖는 삽입 회로 -상기 삽입 회로의 제2 표면은 절연 접착제에 의해 상기 보강재에 부착됨-,c) 상기 삽입 회로 주변에 상기 입력/출력 콘택트 패드의 어레이의 각 콘택트상의 납땜 볼,d) 외부 에지가 상기 보강재의 외부 에지에 수직으로 정렬되어 배치된 프레임 -상기 프레임은 정렬된 제1 표면을 갖고, 프레임 코어를 통해 도전성 비아에 대한 상기 삽입 회로의 주변에 납땜 볼의 어레이를 상기 프레임의 상기 제2 표면상의 외부 BGA 납땜 볼 콘택트에 접속시킴-,e) 플립 칩 범프 및 프레임 납땜 범프 커넥터를 둘러싸는 언더필 재료,f) 상기 프레임 및 상기 보강재에 의해 형성되는 캐비티를 채우는 포장 화합물을 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 유전체층에 의해 분리된 두 개의 도전층을 포함한 삽입 회로를 갖는 반도체 패키지에 있어서,신호, 전원과 접지 콘택트에 대한 전기적 상호접속은, 다수의 전원과 접지면을 제공하는 특정 경계를 갖는 선택적 평면 및 버스를 포함한 상기 두 개의 도전층상에 패터닝되는 것을 특징으로 하는 반도체 패키지.
- 제1항에 있어서, 신호, 전원과 접지 콘택트에 대한 전기적 상호접속은 다수의 전원 및 접지면에 대해 특정 경계를 갖는 선택적 평면 및 버스를 포함한 두 개의 도전층상에 패터닝되는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 삽입 회로의 상기 제1 패터닝된 도전층은 하나 이상의 전원면 및 버스를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 삽입 회로의 상기 제2 패터닝된 도전층은 접지면을 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제5항에 있어서, 상기 전원면은 상기 제1 패터닝된 도전층의 중심에 배치되고 상기 삽입 회로의 각 코너에 버스(bus)되는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제5항에 있어서, 상기 전원면은 외부 콘택트에의 라우팅 상호접속들 사이의 상기 삽입 회로의 상기 제1 패터닝된 층에 배치되는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 삽입 회로는 상기 제1 패터닝된 도전층 및 상기 제2 패터닝된 도전층 사이의 특정 콘택트를 접속시키는 도전성 비아를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 보강재는 상기 회로에서 대기로, 또는 2차 열 확산기로 방열하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 프레임은 상기 집적 회로보다 두꺼운 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 플립 칩 납땜 볼 커넥터의 것과 유사한 크기 및 구성의 삽입 회로 및 프레임 간의 납땜 볼 접속을 갖는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 삽입 회로는 플렉스(flex) 회로를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 삽입 회로는 BT 수지 코어를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 상기 프레임은 FR-4 수지를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제14항에 있어서, 상기 프레임은 BT 수지 코어를 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 플립 칩 상호접속된 집적 회로용 캐비티 다운 볼 그리드 어레이(BGA) 패키지에 있어서,a) 상기 회로에서 대기로, 또는 2차 열 확산기로 방열하는 평면 보강재 또는 패키지 베이스,b) 유전체층에 의해 분리된 두 개의 패터닝된 도전층을 포함한 삽입 회로 -신호, 전원과 접지 콘택트에 대한 전기적 라우팅은 하나 이상의 전원면을 형성하기 위해 특정 경계를 갖는 선택적 평면 및 버스를 포함한 상기 두 개의 도전층상에 패터닝되며, 제1 도전층은 상기 삽입 회로 주변에 입력/출력 콘택트 패드의 어레이에 전기적으로 상호접속시키는 플립 칩 커넥터에 정렬된 중심 영역내에 복수의 콘택트 패드를 포함하고, 접지면은 제2 도전층상에 포함되고, 도전성 비아는 상기 제1 및 제2 도전층상의 특정 콘택트들 간의 상호접속을 제공하고, 제2 표면은 절연 접착제에 의해 상기 보강재에 부착됨-,c) 상기 삽입 회로 주변에 상기 입력/출력 콘택트 패드 각각에 배치되는 플립 칩 커넥터와 유사한 크기 및 구성의 납땜 볼 어레이,d) 외부 에지가 상기 보강재의 외부 에지에 수직으로 정렬되어 배치되고, 정렬된 제1 표면을 갖고 프레임 코어를 통한 도전성 비아에 대한 상기 삽입 회로의 납땜 범프를 상기 프레임의 상기 제2 표면상의 외부 BGA 납땜 볼 콘택트에 접속시키는, 상기 집적 회로보다 더 두꺼운 프레임,e) 플립 칩 범프 및 프레임 납땜 범프 커넥터를 둘러싸는 언더필 재료,f) 상기 프레임 및 상기 보강재에 의해 형성되는 캐비티를 채우는 포장 화합물을 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제1항에 있어서, 제1 전원면은 상기 제1 패터닝된 도전층의 중심에 배치되고 상기 삽입 회로의 각 코너에 버스되고, 제2 전원면은 또한 외부 콘택트에의 라우팅 상호접속들 사이의 상기 삽입 회로의 상기 제1 패터닝된 도전층에 배치되는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
- 제3항에 있어서, 상기 삽입 회로의 상기 제1 패터닝된 도전층은 하나 이상의 전원면을 포함하는 것을 특징으로 하는 반도체 패키지.
- 삽입 회로를 갖는 캐비티 업 BGA 패키지에 있어서,신호, 전원과 접지 콘택트에 대한 전기적 라우팅은 다수의 전원 및 접지면을 제공하기 위해 특정 경계를 갖는 선택적 평면 및 버스를 포함한 두 개의 도전층상에 실현되는 것을 특징으로 하는 캐비티 업 BGA 패키지.
- 캐비티 다운 BGA 패키지에 있어서,플립 칩 상호접속된 집적 회로,보강재 또는 패키지 베이스,유전체층에 의해 분리된 두 개의 금속 도전층을 갖는 삽입 회로, 및상기 삽입 회로 및 외부 납땜 볼 단자 간의 전기적 상호접속, 및 상기 집적 회로 칩을 내장하기 위한 캐비티를 제공하는 이중 목적 기능을 하는 프레임을 포함하는 것을 특징으로 하는 캐비티 다운 BGA 패키지.
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- 1999-12-30 KR KR1019990065649A patent/KR100694739B1/ko active IP Right Grant
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KR100473336B1 (ko) * | 2002-05-06 | 2005-03-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
KR100861508B1 (ko) * | 2002-06-07 | 2008-10-02 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조방법 |
KR100588404B1 (ko) * | 2004-03-16 | 2006-06-12 | 삼성코닝 주식회사 | 반도체 박막 연마용 산화세륨 슬러리 |
Also Published As
Publication number | Publication date |
---|---|
US20010013654A1 (en) | 2001-08-16 |
US6396136B2 (en) | 2002-05-28 |
KR100694739B1 (ko) | 2007-03-14 |
JP2000200860A (ja) | 2000-07-18 |
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