WO1998022863A1 - Processeur a faible consommation d'energie - Google Patents
Processeur a faible consommation d'energie Download PDFInfo
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- WO1998022863A1 WO1998022863A1 PCT/JP1997/004253 JP9704253W WO9822863A1 WO 1998022863 A1 WO1998022863 A1 WO 1998022863A1 JP 9704253 W JP9704253 W JP 9704253W WO 9822863 A1 WO9822863 A1 WO 9822863A1
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- Prior art keywords
- circuit
- mode
- voltage
- substrate bias
- substrate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Definitions
- the present invention relates to a semiconductor integrated circuit device such as a processor, and more particularly to a microcontroller that realizes high-speed operation and low power consumption by controlling a substrate noise of a processor circuit including MOS transistors in accordance with an operation mode of the processor. Regarding the processor.
- CMOS complementary metal-oxide-semiconductor
- the power consumption of the CMOS circuit includes dynamic power consumption due to charging and discharging during switching and static power consumption due to leakage current.
- the dynamic power consumption is proportional to the square of the power supply voltage V dd and occupies a large amount of power, so it is effective to lower the power supply voltage to reduce power consumption.
- the power supply voltage is decreasing.
- Some current low-power microprocessors have a power management mechanism, have multiple operation modes in the processor, and stop the clock supply to the execution unit during standby in accordance with the operation mode. By stopping the clock supply, dynamic power consumption due to switching in unnecessary execution units can be reduced as much as possible. However, static power consumption due to leakage current cannot be reduced and remains.
- FIG. 2 is a cross-sectional view of a circuit having a CMOS structure, in which a part of a surface layer of a p-type (p-type substrate) 201 has an n-type layer 205 and a p-type layer 201.
- An nMOS transistor consisting of an n + source source / drain region 202, a gate oxide film 203, and a gate electrode 204 is formed on the surface of n + type, and a p + type
- a pMOS transistor composed of a source / drain region 206, a gate oxide film 207, and a date electrode 208 is formed.
- the sources of the pMOS transistor and nMOS transistor are connected to the power supply voltage (hereinafter referred to as Vdd) and the ground potential (hereinafter referred to as Vss), respectively, and the drains of the nMOS transistor and pMOS transistor are connected to the output signal.
- Vdd power supply voltage
- Vss ground potential
- Vb p 209 is provided at the n-layer 205 of the pMOS transistor
- Vb n 210 is provided at the p-well 201 of the nMOS transistor.
- Vb p209 is connected to Vdd and Vbn210 is connected to Vss using a device as shown in Fig. 2.
- these substrate biases are switched to Vbp2
- the threshold voltage of the MOS transistor can be increased and the leakage current can be reduced.
- the above-mentioned variable control of the substrate bias is performed on the processor circuit, and the threshold voltage of the MOS transistor is lowered during the operation of the processor. Therefore, it is necessary to maintain high speed and increase the threshold voltage during standby to reduce leakage current.
- the base noise of the processor it is necessary to accurately shift the operation mode of the processor when switching the board noise, especially the timing of restarting the processor when shifting from the standby state to the operation state. Control to prevent processor malfunction Must.
- An object of the present invention is to provide a high-speed and low-power-consumption processor by solving the above problems and realizing the above-described substrate bias control on a processor 'chip and applying it to various operation modes of the processor. .
- the processor of the present invention is characterized by a processor main circuit for executing a program instruction sequence on a processor, a board bias switching device for switching a board bias voltage applied to the board.
- the board ⁇ bias switching device In response to the execution of the instruction to shift to the standby mode in the processor main circuit, the board ⁇ bias switching device is controlled so as to switch the bias to the voltage for the standby mode.
- the board mode switching device is controlled to switch to the voltage for the normal mode, and after the switched bias voltage is stabilized, the operation mode control unit that releases the standby of the processor main circuit and resumes the operation is provided. is there.
- the semiconductor device of the processor chip has a triple hole structure, and the processor main circuit is formed on a cell area different from the substrate bias switching device and the operation mode control section. Is to be done.
- the operation mode control unit includes means for waiting for the switched bias voltage to stabilize before restarting the operation of the main processor circuit when the bias is switched, and for stabilizing the bias.
- An on-chip timer for measuring the elapse of the required time or a sensor for detecting that the bias has stabilized at a predetermined voltage is provided.
- the semiconductor device of the processor chip has a triple-cell structure, is divided into a plurality of functional modules, and these are formed on different cell areas respectively.
- a processor main circuit a substrate bias switching device for switching a substrate bias applied to a substrate of each functional module, and an instruction for setting one or more of the functional modules in the processor main circuit to standby.
- the board bias switching device is controlled so that the substrate bias of the functional module is switched to the voltage for the standby mode in response to the signal. Control the device to switch the interface to the normal mode voltage, and notifies the processor main circuit that the standby of the functional module has been released after the switched bias voltage has stabilized. That is, an operation mode control unit is provided.
- the processor of the present invention includes a means for dynamically switching the operating speed of the processor main circuit, and a board bias switching device which receives an instruction to change the operating frequency in the processor main circuit, and executes the processor main circuit or the functional module. Control to switch the board substrate of the controller to a voltage suitable for the operating frequency, and after the stabilized bus voltage is stabilized, notifying the processor main circuit of the completion of the switching of the operating speed.
- a mode controller is provided.
- a feature of the processor of the present invention is that the substrate bias switching device is constituted by a substrate bias generation circuit for internally generating a substrate bias voltage.
- the present invention also proposes a control method that contributes to lower power consumption of the device. In other words, although a transistor with a low threshold voltage is fast, the leakage current between the source and drain is large and power consumption increases, so it is important to prevent this.
- a configuration for this is a control method for controlling power consumption of a semiconductor integrated circuit device having a plurality of element circuit blocks operating on the basis of a clock signal and having a transistor formed on a semiconductor substrate.
- a first mode in which all the circuit blocks operate based on the clock, a second mode in which the supply of the clock signal to at least one of the element circuit blocks is stopped, and a clock signal in which all of the element circuit blocks are supplied.
- the main circuit is, for example, a processor including a CPU and the like.
- the first mode is a mode in which the main circuit performs normal operations (calculation, storage, etc.).
- the second mode is a state in which the clock to a part of the processor is stopped, and is called, for example, a sleep mode or a deep sleep mode. By selecting the range in which the clock is stopped, low power consumption can be achieved while maintaining only the necessary functions.
- the third mode is a mode in which the body bias is controlled for the processor circuit, the threshold value of the transistors constituting the circuit is increased, and the power consumption due to the sub-threshold leakage current is reduced.
- the standby mode is referred to as a hardware standby mode.
- the standby mode is powerful enough to return to the normal state by interrupt control. In the hardware standby mode, it cannot return without resetting.
- the third mode the function of the main circuit is stopped.
- the element circuit block is included in the first circuit block
- the clock signal is formed by the oscillation circuit included in the second circuit block
- the second circuit blocker is connected to the first circuit block.
- a clock signal and an information signal to be processed in the first circuit block are input.
- the second circuit block further includes an input / output circuit and a control circuit for controlling the substrate bias. Normally, the second circuit block does not need to operate as fast as the first circuit block including the main circuit. Therefore, it is desirable that the transistors forming the second circuit block have a larger threshold value and a higher operating voltage than the transistors forming the first circuit block. Further, the transistor constituting the main circuit of the first circuit block is formed on a well separate from the other circuits, so that the influence of the other circuits can be reduced.
- a level conversion circuit is required between the two.
- a first circuit block is provided with a level-down circuit
- a second circuit block is provided with a level-up circuit to convert a signal level.
- the operation sequence is important for ensuring reliability.
- the clock signal input from the second circuit block to the first circuit block or the signal processed by the first circuit block First, the information signal input to the first circuit block is stopped, and then, the substrate bias of at least a part of the transistor formed on the semiconductor substrate is controlled to increase the threshold value of the transistor.
- input to the first circuit block can be prevented when the operation of the first circuit block is unstable, and malfunction of the first circuit block can be prevented.
- a configuration such as controlling the substrate bias can be adopted.
- the timer for waiting is arranged outside the first circuit block, and is arranged, for example, in the second circuit block or outside the device.
- the threshold of the transistor is reduced by controlling the substrate bias of at least a part of the transistor formed on the semiconductor substrate. Then, the input of the above-described cook signal input from the second circuit block to the first circuit block or the information signal to be processed by the first circuit block is started. That is, in order to prevent malfunction of the first circuit block, signal input is started after the substrate voltage of the first circuit block is stabilized.
- the threshold value of the transistor is reduced by controlling the substrate bias of the first circuit block, and the timer waits for a predetermined time, and then operates. After is stabilized, input of the clock signal and other signals input to the first circuit block is started.
- the signal input to the first circuit block is started.
- the input of the clock signal and other signals input to the first circuit block is started in accordance with the signal output from the substrate bias generation circuit that indicates the release of standby. I do.
- FIG. 1 is a block diagram of a processor chip according to a first embodiment of the present invention.
- FIG. 2 is a sectional view showing a general device structure used for substrate bias control.
- FIG. 3 is a sectional view showing a device structure according to the first example of the present invention.
- FIG. 4 is a flowchart used to explain the operation in the first embodiment of the present invention.
- FIG. 5 is a block diagram of a processor 'chip according to the second embodiment of the present invention.
- FIG. 6 is a block diagram of a processor chip according to the third embodiment of the present invention.
- FIG. 7 is a block diagram of a processor 'chip according to the fourth embodiment of the present invention.
- FIG. 8 is a block diagram of a processor 'chip according to a fifth embodiment of the present invention.
- FIG. 9 is a diagram for explaining the relationship between the operation mode and the substrate bias control according to the present invention.
- FIG. 10 is a diagram illustrating a configuration of a processor main circuit of the present invention.
- FIG. 11 is a diagram for explaining a low power consumption mode of the present invention.
- FIG. 12 is a diagram illustrating sleep and deep sleep according to the present invention.
- FIG. 13 is a transition diagram of the operation mode of the present invention.
- FIG. 14 is a first configuration diagram of a configuration of a processor chip and a power supply control circuit of the present invention.
- FIG. 15 is a diagram for explaining a power supply replacement sequence according to the present invention.
- FIG. 16 is a configuration diagram of a processor chip and a second configuration diagram of a power supply control circuit according to the present invention.
- FIG. 17 is a diagram for explaining the sequence of the RTC power supply backup of the present invention.
- FIG. 18 is a view for explaining the sequence from the low power consumption mode of the present invention to the return from an interrupt.
- FIG. 19 is a diagram for explaining the sequence from the low power consumption mode of the present invention to the return from reset.
- FIG. 1 is a block diagram showing a configuration example of a processor chip for realizing the first embodiment of the present invention.
- a processor chip 101 is an LSI chip having a circuit of a CMOS structure, and includes a processor main circuit 102, an operation mode control unit 103, and a substrate bias switching device 104.
- the substrate bias switching device 104 receives the substrate 107 of the pMOS transistor constituting the processor main circuit 102 in accordance with the signal 107 output from the operation mode control unit.
- Vdd or Vddb is selected as the bias and output to signal Vbpill, and either Vss or Vssb is selected as the substrate bias of the nMOS transistor and output to signal Vbn112.
- the level 302 formed by the processor main circuit 102 is formed separately and independently from the level formed by the substrate bias switching device 104 and the operation mode control unit.
- FIG. 3 is a sectional view showing the device structure of the processor chip 101.
- Fig. 3 The difference from Fig. 2 is that the n-type substrate 301 has a p-type layer 302 and a part of its surface phase has an n-type layer 205, that is, a triple-layer device. Is a point.
- An nMOS transistor is formed on the surface of the p-type transistor 302, and a pM ⁇ S transistor is formed on the surface of the n-type well 205, thereby forming a CMOS circuit.
- Vbp 209 is provided to the n-well 205 of the pMOS transistor and Vbn 210 is provided to the p-well 302 of the nMOS transistor, as in FIG.
- the processor main circuit 102 is formed in a p-layer 302 different from the operation mode control section 103 and the substrate bias switching device 104.
- the influence of the substrate bias control extends only to the processor main circuit 102, and the operation mode control section 103 and the substrate bias switching device 104 can avoid the influence.
- the operation of the processor 'chip 101 in this embodiment will be described with reference to FIG.
- the operation modes of the processor main circuit 102 include a normal mode for executing normal instructions and a standby mode for not executing instructions.
- FIG. 4 shows a case where the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode, and from the standby mode to the normal mode. This is a flowchart showing the processing.
- the processor main circuit 102 operates in the normal mode.
- the substrate bias switching device 104 selects 0 (3 and 3 s) for the substrate biases Vb p 111 and Vb n 112, respectively.
- the pressure value is Vbp2 1.5 V, which is obtained by 1311310 ⁇ (Step 401).
- the processor main circuit 102 When executing the sleep instruction, the processor main circuit 102 outputs a “standby request” to the signal 105 and transmits the signal to the operation mode control unit 103, and then stops the instruction execution operation and shifts to the standby mode ( Step 4 0 2).
- the operation mode control unit 103 When receiving the signal 105 from the processor main circuit, the operation mode control unit 103 outputs a signal 107 to switch the substrate bias of the processor main circuit 102 to the voltage for the standby mode.
- the substrate bias switching device 104 receives this signal 107 and selects and outputs Vd db and V ssb from the input voltage 1 10 to the substrate biases Vb p 111 and Vbn 112 (step 4). 0 3, 4 4).
- step 405 When the operation mode control unit 103 detects that the “standby release interrupt” is externally asserted to the signal 108 while the processor main circuit 102 is in the standby state (step 405), A signal 107 is output to switch the substrate bias of the processor main circuit 102 to the voltage for the normal mode, and the substrate bias switching device 104 receives the signal 107 and receives the substrate bias V bp 1 11. Switch 1 1 and Vbn 112 to Vdd (1.5 V) and Vss (0.0 V), respectively (step 406).
- the operation mode control unit 103 sets the sufficient time necessary for stabilizing the switched substrate bias voltage to the on-chip timer 109 before switching the operation mode of the processor main circuit 102. Start (step 407) and wait until the time starts (step 408). Then, after a time-out, the operation mode control unit 103 outputs “standby release” to the signal 106 and transmits it to the processor main circuit 102. Upon receiving this signal 106, the processor main circuit 102 shifts to the normal mode and resumes the instruction execution operation (step 409).
- the MOS transistors constituting the processor main circuit are controlled during operation by controlling the substrate biases Vbp 11 and Vbn 112 of the processor main circuit 102.
- the substrate biases Vbp 11 and Vbn 112 of the processor main circuit 102 By lowering the threshold voltage of the transistor, it is possible to support high-speed operation, and by increasing the threshold voltage during standby, leakage current can be reduced.
- FIG. 5 is a block diagram showing a configuration of a processor chip according to the second embodiment of the present invention.
- the operation mode control unit 103 includes a sensor 501 that detects a bias voltage applied to the substrate of the processor main circuit 102.
- the operation mode control unit 103 controls the substrate bias switching device 104 as in the first embodiment.
- the operation mode control unit 103 outputs "standby release" to the signal 106 and restarts the operation of the processor main circuit 102. Let it.
- FIG. 6 is a block diagram showing a configuration of a processor chip according to the third embodiment of the present invention.
- the triple device structure shown in Fig. 3 is considered as the basic device structure of the processor chip 601.
- the processor main circuit is composed of a plurality of functional modules such as CPU 604, module A 606, and module B 608. Each functional module is separated on a different area, and is not affected by the board bias control of other functional modules.
- Functional modules include smaller units, such as CPUs, FPUs, caches, or arithmetic units.
- Substrate bias switching devices 605, 607, 609 are provided corresponding to the respective functional modules 604, 606, 608, and the substrate module of the corresponding functional module is provided.
- Instruction execution is performed mainly by the CPU 604, which is one of the functional modules.
- the standby of the functional module is transmitted to the operation mode control unit 602.
- the operation of the processor 'chip 601 in this embodiment will be described below. Most First, it is assumed that all functional modules are operating in the normal mode. When the CPU 604 executes the instruction to set the module A to standby, it outputs this standby request to the signal 610 and disables this module until the standby of module A 606 is released. Become.
- the operation mode control section 602 receives this signal 610 and outputs a signal 612 to the substrate bias switching device 607 to switch the substrate bias of the module A 606 to the voltage for the standby mode. . When the module A 606 is in the standby state, the operation mode control unit 602 receives the module A from the output signal 610 of the CPU 604 or the external signal 613 of the processor chip 601.
- the standby release signal of 606 When the standby release signal of 606 is received, the signal 612 is output to the substrate bias switching device 607, and the substrate bias of the module A is switched to the voltage for the normal mode. Then, the operation mode control unit 602 waits for the stability of the substrate bias switched by using the on-chip timer 603 in the same manner as the first embodiment of the present invention. Notifies that module A has been released from standby. When the CPU 604 receives this signal 611, it becomes possible to execute an instruction using the module A.
- the CPU 604 itself is also a target of the standby control. In this case, when the CPU 604 shifts to the standby mode, execution of all instructions is stopped, and when the external signal 613 is asserted with the signal for releasing the standby of the CPU 604, the operation mode control unit is activated. 602 asserts the release of the standby of the CPU 604 to the signal 611 after the switching of the substrate bias of the CPU 604 is completed, except that the instruction execution of the CPU 604 is resumed. The control is performed in the same manner as in the case of the module A606.
- FIG. 7 is a block diagram showing a configuration of a processor chip according to the fourth embodiment of the present invention.
- the difference from the first embodiment is that the number of types of the voltage 701 supplied from the outside to the substrate bias switching device 104 is increasing, and the substrate bias switching device 104 That it can be selected as a bias and applied to the processor main circuit 102.
- the processor main circuit 1 There is provided a means for dynamically changing the operation speed of the processor main circuit 102, that is, the operation frequency of the processor main circuit 102, according to an instruction.
- Vdd (for pMOS) and Vss (for nMOS) are used as substrate biases corresponding to the high-speed mode
- Vddb2 (for pMOS) and Vssb2 (nMOS) are used as substrate biases corresponding to the low-speed mode
- Vd db 1 (for pMOS) and V ssbl (for nMOS) are selected as the substrate bias corresponding to the standby mode.
- the operation of the processor 'chip 101 in this embodiment will be described.
- the substrate bias switching device 104 selects Vdd for Vb p 111 and V ss for Vb n 112 as the substrate bias of the processor main circuit. are doing.
- the processor main circuit 102 executes the instruction for shifting to the low-speed mode, it outputs the request as a signal 105 and interrupts the instruction execution operation.
- the clock supplied to the processor main circuit 102 is switched to a low frequency by execution of the instruction for shifting to the low-speed mode.
- the operation mode control unit 103 receives the signal 105 and outputs the signal 107 to switch the substrate bias of the processor main circuit 102 to the voltage for the low-speed mode.
- the substrate bias switching device 104 receives the signal 107 and switches the substrate biases Vb p 111 and Vb n 112 to Vddb2 and Vssb2, respectively.
- the operation mode control unit 103 uses the on-chip timer 109 as in the above embodiment, waits for the stabilized substrate bias to stabilize, and the processor main circuit 102 completes the transition to the low-speed mode. Is notified via signal 106. Upon receiving this signal 106, the processor main circuit 102 resumes the interrupted instruction execution operation in the low-speed mode.
- the operation at the time of switching from the low-speed mode to the high-speed mode, switching from the high-speed mode or the low-speed mode to the standby mode, or switching from the standby mode to the high-speed mode or the low-speed mode in this embodiment is also the same as described above. Details are omitted because they are the same.
- the operation speed can be further subdivided, and the substrate bias control corresponding thereto can be performed.
- the processor main circuit 102 uses the triple-layer structure of the device for each functional module. It is also possible to control the substrate bias in conjunction with the switching of the operating frequency for each functional module.
- the substrate bias control suitable for the operating frequency of the processor as in the present embodiment, it is possible to reduce the leak current in the low-speed operation mode. Furthermore, in this low-speed mode, the input voltage range in which both the pMOS and nMOS transistors of the CMOS circuit conduct simultaneously is narrower than in the high-speed operation mode, so that the shoot-through current during switching is small. Is also obtained.
- FIG. 8 is a block diagram showing a configuration of a processor chip according to a fifth embodiment of the present invention.
- the substrate bias switching device is constituted by a substrate bias generation circuit 801.
- the substrate bias generation circuit 801 is controlled by the output signal 802 of the operation mode controller 103, generates the substrate bias voltage internally, and outputs it to V bp 111 and V bn 112. I do.
- the substrate biases V bp 111 and V bn 112 generated in accordance with the operation mode of the processor main circuit 102 are the first voltage values. This is the same value as in the example.
- the operations of the processor main circuit 102 and the operation mode control unit 103 are the same as those of the first embodiment, and thus the details are omitted.
- the substrate bias switching device in the second, third, and fourth embodiments with this substrate bias generation circuit 811, similarly to the present embodiment, a substrate bias is generated inside the processor 'chip. It can be switched according to the operation mode.
- the timing for restarting the processor at the time of transition from the standby state to the operating state is accurately controlled using the timer or the sensor.
- Optimum substrate bias control becomes possible.
- the leakage current can be reduced in the standby mode while the operation mode of the processor maintains the high speed in the normal mode.
- by performing substrate bias control according to the operation mode of each function module it is possible to reduce the leakage current of function modules that are not necessary for execution even while the processor is operating.
- substrate bias control suitable for the operating frequency of the processor it is possible to obtain not only a reduction in leakage current in the low-speed mode, but also an effect of reducing a through current during switching. As a result, power consumption can be effectively reduced, and a microprocessor having both high speed and low power can be provided.
- the microcomputer has two power supplies, 1.8 V and 3.3 V, and controls the substrate bias only at 1.8 V. It is desirable that the circuit that supplies 1.8 V be composed of MOS transistors with a relatively low threshold (for example, Vth is about 0.4 V).
- Figure 9 shows an example of the operation mode of the microcomputer.
- the operation modes include a normal operation mode 982 in which normal operation is performed, and a reset mode 981.
- Modes that operate with low power consumption include sleep 983, deep sleep 984, standby 985, hardware standby 986, and RTC (real-time clock) battery backup mode.
- As a test mode there is I DDQ measurement.
- the RTC battery backup mode is a mode in which only the power of the RTC circuit operating at 3.3 V is supplied. Since transition to this mode is made from the low power consumption mode, substrate bias control is performed.
- IDDQ measurement is a mode in which the standby current is measured and the through current due to short-circuit or failure of the transistor is measured, in this case, the substrate bias must be controlled and the leakage power of the chip must be controlled. Need to be smaller to make it easier to find defects.
- the arithmetic circuits include a CPU (Central Processing Unit) 971 and an FPU (Floating-Point Arithmetic Unit) 972. Also built in chip A memory 973, a BSC (bus control unit) 974 that performs interface with external memory, a DMAC (DMA control unit) 975 that performs DMA (direct memory access), and a serial port. There are SCI (serial control unit) 976 to control, INTC (interrupt control unit) 977 to control interrupt input, and CPG (clock control unit) 978 to control clock.
- SCI serial control unit
- INTC interrupt control unit
- CPG clock control unit
- the power consumption is large because only the clocks of the arithmetic devices such as CPU 971, FPU 972, and cache 973 are stopped and the substrate bias control is not performed. Although it is not possible to reduce the number of times, DMA transfer by DMAC 975 and normal refresh of DRAM (Dynamic RAM) and SDRAM (Sink Mouth Dynamic RAM) by BSC 974 (102 4 times / 16 ms Refresh) is possible. Since the CPG 978 is operating and the substrate bias is not controlled, the return time from the sleep 983 to the normal operation mode 982 is fast.
- the standby 985 mode power consumption is extremely low because all operations are stopped and board bias control is performed. Since the clock is stopped, DMA transfer is not possible. Before refreshing the DRAM or SDRAM, the control signal (R AS Signal, CAS signal) must be set beforehand. However, the recovery time from standby 985 to normal operation 982 becomes longer because the clock power is stopped, because the clock oscillation is waiting for stabilization and the recovery time from the substrate bias state.
- Deep sleep 984 mode is a low power consumption mode between sleep 983 and standby 985.
- Figure 12 shows the differences between the operation modules of sleep 983 and deep sleep 984.
- sleep 983 the operating BSC 975, DMAC 974, and SCI 975 are stopped in deep sleep 984, so power consumption can be reduced accordingly.
- deep sleep 984 mode DMA transfer cannot be performed, and the memory refresh becomes self-refresh.
- the return time from the deep sleep 984 to the normal operation mode 982 is as fast as in the sleep mode.
- FIG. 13 shows a state transition diagram of the operation mode. All the power supply is off from 980.
- the RESET # 952 (or power-on reset) pin input causes the processor chip to transition to the reset state 981. When RESET # 952 is negated, the operation transits to normal operation 982. Transition from this state to the low power consumption operation mode.
- transitions by an instruction This transition is made when the CPU 971 executes the sleep instruction.
- the mode register can be set to select sleep 983, deep sleep 984, or standby 985, and transition to each mode can be made.
- the return from each mode to the normal operation mode 982 is an interrupt 988.
- Another transition method is a transition by the HARDSTB # 951 pin. When this pin is asserted, a transition is made to the hardware standby state 986. In this state, as in the case of the standby 985, all clocks are stopped and the substrate bias control is being performed.
- the 3.3 V circuit will have no transistors through which through current flows, and I DDQ can be measured. Also, if the input buffer of the RTC circuit placed in the 3.3 V system is fixed, the input signal of the RTC circuit will not be floating (intermediate level) even if the power supply other than the RTC circuit is turned off. Malfunction can be prevented, and only the RTC circuit can operate.
- FIG 14 shows the configuration of the processor chip 901 and the configuration of the power supply control circuit, which make it possible to replace the power supply 904 (battery) of the processor chip 901 by applying Hardener Standby.
- the processor chip 901 is composed of a 1.8 V domain circuit 930 operating at 1.8 V and a 3.3 V domain circuit 933 operating at 3.3 V.
- the 1.8 V area circuit 930 is composed of a processor main circuit 902 and a level down circuit 905 that converts the level from 3.3 to 1.8 V.
- 3.3 V circuit 931 is substrate bias generation circuit 903, clock oscillation circuit 9108, 10 circuit 909, operation mode control section 913, RTC circuit 914 and 1.8 Level-up circuit for level conversion from V to 3.3 V 904, 910, output fixing circuit for fixing the signal from 3.3 to 1.8 V 9 0 7.9.1 1 Have been.
- control circuit of the power supply system there are a power supply 904, a power supply monitoring circuit 921, a display 922, and a voltage generation circuit 920 for generating a 1.8 V system voltage.
- the substrate bias generation circuit 9 0 3 is connected to the normal substrate level without subtracting the substrate bias (for example, VDD potential for PMOS, VSS potential for NMOS) ) Is held.
- the clock oscillating circuit 908 is composed of a PLL (Phase Locked Loop) or the like, generates a clock for internal operation, and outputs the clock to the processor via the output fixing circuit 907 and the level down circuit 905.
- the 10 circuit 909 takes in an external signal and sends it to the main processor circuit 902 via the output fixing circuit 907 and the level down circuit 905.
- a signal from the processor main circuit 902 is output to the outside via the level-up circuit 904.
- the RTC circuit 914 operates at 3.3 V, receives a control signal from the processor main circuit 902 via the level-up circuit 910, and receives a control signal from the processor main circuit 902, the level-down circuit 906, and the output fixing circuit 911.
- a control signal is transmitted to the processor main circuit 902 via The operation mode control section 913 controls the substrate bias generation circuit 903 in particular.
- the power supply monitoring circuit 921 monitors the voltage level of the power supply 904. When the voltage level falls below the specified level (detects a dead battery), set HARDSTB # 951 to low level. At the same time, a low battery alarm is displayed on the display 9 22 to notify the user. Even when the voltage level is lowered, the voltage holding circuit 923 can hold the voltage level for a predetermined period (from several minutes to several hours). During this period, the user can replace the power supply 904. The power supply replacement sequence will be described below with reference to FIG.
- the operation mode enters the hardware standby state 986 when HARDSTB # 9 5 1 becomes a bite level.
- the operation mode control section 913 outputs a 1.8 V signal fixed 953, fixes the signal from 3.3 to 1.8 V, and stops the 1.8 V system clock. This ensures that 1.
- the substrate bias is pulled because the 8 V signal does not operate (the threshold voltage of the MOS transistor is high, the operation speed is slow, and the substrate potential is unstable) To prevent malfunction of 1.8 V circuit.
- a substrate bias control start signal 955 is output to the substrate bias generation circuit 903.
- a substrate bias control start signal 955 is output to the substrate bias generation circuit 93.
- the time difference until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped is set. This time difference can be measured in the evening based on the RTC clock of the RTC circuit 914.
- the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8 V system substrate. While the substrate bias is being pulled, the 956 signal is returned to the operation mode control section 913 during the substrate bias control.
- the processor main circuit 902 does not operate while the substrate bias is being pulled. In addition, the current consumption is low due to low leakage current. As a result, the holding time of the voltage holding circuit 923 also becomes longer.
- substrate bias generation circuit 955 In response to the release of substrate bias control start signal 955, substrate bias generation circuit
- the operation mode control unit 913 starts to return the substrate bias of the 1.8 V diameter substrate to the operating state potential (for example, VDD potential for PMOS, VSS potential for NMOS). Substrate by A predetermined time is required for the recovery of the bias, and when the substrate bias is returned, the operation mode control unit 913 is notified by releasing the substrate bias controlling signal 956.
- the operating state potential for example, VDD potential for PMOS, VSS potential for NMOS.
- the operation mode control unit 913 In response to the release of the substrate bias control signal 956, the operation mode control unit 913 outputs the 1.8 V signal fixed 953, and the processor main circuit 902, etc. 1. A signal is input to the 8 V circuit.
- the power supply 904 can be replaced by using the low power consumption mode by the hardware standby.
- FIG 16 shows an example of a configuration that implements the RTC power supply backup mode.
- the RTC circuit 914 is called a real-time counter and implements a clock or calendar function. For this reason, the clock function cannot be realized unless it is constantly operating.
- the RTC circuit 914 must operate even when the power supply 904 is cut off.
- the 3.3 V region is divided into a normal 3.3 V region 991 and a region 992 operating at 3.3 V of the RTC. I have.
- an input fixed circuit 912 and an input fixed level-up circuit 960 are added to the input circuit, and other power supplies (1.8 V, normal Even if the input signal becomes floating while the 3.3 V power supply is turned off, the intermediate level signal should not be transmitted to the area 992 that operates at 3.3 V of the RTC even if the input signal becomes floating. To prevent malfunction.
- the power supply control circuit includes a power supply 904, a power supply monitoring circuit 921, a display 922, a voltage generation circuit 920 that generates 1.8 V system voltage, and a backup battery 9 There are 62, diodes 963 and 964.
- the substrate bias generating circuit 903 holds the normal substrate level without subtracting the substrate bias.
- the clock generation circuit 908 is composed of a PLL (Phase Locked Loop), etc., generates a clock for internal operation, and outputs the clock to the processor via the output fixing circuit 907 and the level down circuit 905.
- Send to circuit 902. I 0 circuit 909 takes in signals from outside and outputs The signal is sent to the processor main circuit 902 via the fixed circuit 907 and the level down circuit 905. Further, the signal from the processor main circuit 902 is output to the outside via the level up circuit 904.
- the RTC circuit 914 operates at 3.3 V, receives a control signal from the processor main circuit 902 via the input fixed level up circuit 960, and receives a control signal from the processor down circuit 906 and the output fixed circuit 9 A control signal is transmitted to the processor main circuit 902 via 11.
- the operation mode control section 913 receives a control signal via the input fixing circuit 912 and controls the substrate bias generation circuit 90.3 in particular.
- the power supply monitoring circuit monitors the voltage level of the power supply. When the voltage level falls below a predetermined level (detects the condition that the battery is dead), the HARDSTB # 951 is set to the lip level, the input of the RTC 3.3 V area 992 is fixed, and the RTC circuit 914 To prevent malfunction.
- the low battery alarm is displayed on the display 9 22. Thereafter, the voltage level continues to drop, and the 3.3 V and 1.8 V system voltages are not supplied to the processor chip 901. At this time, the voltage (VDD-RTC, VSS-RTC) is supplied only from the backup battery 962 to the 3.3 V region of the RTC via the diode 963, and even if there is no power supply 904 Only the RTC circuit 9 14 (calendar counter circuit) operates normally. The diode 964 prevents the current from flowing to other than the RTC circuit 914.
- the operation mode enters the hardware standby state 986 when HARDSTB # 951 becomes a bite level.
- the operation mode control section 913 outputs a 1.8 V signal fixed 953, fixes the signal from 3.3 to 1.8 V, and stops the 1.8 V system clock.
- the 1.8 V system signal does not operate, so that the malfunction of the 1.8 V system circuit while the substrate bias is pulled is prevented.
- an input fixed signal 954 to the RTC circuit 914 is output and the input signal is fixed. This prevents an unstable intermediate level signal from entering the RTC circuit 914 when the other power supply is cut off.
- a substrate bias control start signal 955 is output to the substrate bias generation circuit 93.
- Signal fix 9 5 3 Between the start of the substrate bias control 955, the signal is actually fixed, and the time difference until the supply of the signal to the 1.8 V region is stopped is set. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
- the substrate bias generation circuit 903 Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8 V system substrate. While the substrate bias is being pulled, the 956 signal is returned to the operation mode control section 913 during the substrate bias control.
- the processor main circuit 902 does not operate while the substrate bias is being pulled. In addition, the current consumption is low due to low leakage current.
- the interruption period of the power supply 904 may be long. Also, the power supply 904 can be replaced. (6) After returning from the power supply 904 cutoff (or after replacing the power supply 904), the power supply voltage returns to the normal level, so that HARDSTB # 951 returns to the high level.
- the substrate bias generation circuit 903 sets the substrate bias of the 1.8 V-diameter substrate to the operating state potential (for example, the VDD potential for PMOS and the VDD potential for NMOS). Starts to return to VSS potential). A predetermined time is required until the board bias is recovered, and when the board bias is returned, the operation mode control unit 913 is notified by releasing the board noise control signal 956. .
- the operation mode control unit 913 In response to the release of the substrate bias control signal 956, the operation mode control unit 913 outputs the 1.8 V signal fixed 953, and the processor main circuit 902, etc. 1. A signal is input to the 8 V circuit.
- FIG. 18 illustrates a sequence in which the normal sleep instruction 959 is used to enter the standby state 985, and the interrupt signal 958 returns to the normal state 982.
- the operation mode enters the standby state 985 by the sleep instruction 959.
- the operation mode control section 9 13 outputs 1.8 V signal fixed 953, fixes the signal from 3.3 V to 1.8 V, and stops the 1.8 V system clock. . This prevents the 1.8 V circuit from malfunctioning when the substrate bias is pulled.
- a substrate bias control start signal 955 is output to the substrate bias generation circuit 93.
- the time difference until the signal is actually fixed and the supply of the signal to the 1.8 V region is stopped is set. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914.
- the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8 V system substrate. While the substrate bias is being pulled, the 956 signal is returned to the operation mode control section 913 during the substrate bias control.
- the processor main circuit 902 does not operate while the substrate bias is being pulled. In addition, the current consumption is low due to low leakage current.
- the substrate bias generation circuit 903 sets the substrate bias of the 1.8 V diameter substrate to the operating state potential (for example, VDD potential for PMOS, NMOS potential for NMOS). About Vss potential). A predetermined time is required until the substrate bias is recovered. When the substrate bias is returned, the operation mode control unit 913 is notified by releasing the substrate bias control signal 956.
- the operation mode controller 913 releases the 1.8 V signal fixed 953.
- the 8 V signal fixed 953 After the substrate bias control signal is released, malfunction of the 1.8 V system circuit is prevented.
- a signal is input to a 1.8 V system circuit such as the processor main circuit 902 and enters a normal state 998, and the processor main circuit 902 starts a normal operation.
- the processor chip 901 enters the low power consumption mode, More return.
- FIG. 19 shows a sequence in which the normal sleep instruction 959 is used to enter the standby state 985 and return to the normal state 982 by RESET # 952.
- the sleep mode 959 puts the operation mode into the standby state 985.
- the operation mode control section 9 13 outputs 1.8 V signal fixed 953, fixes the signal from 3.3 V to 1.8 V, and stops the 1.8 V system clock. . This prevents the 1.8 V circuit from malfunctioning when the substrate bias is pulled.
- the substrate bias control start signal 955 is output to the substrate bias generating circuit 903.
- the substrate bias generation circuit 903 Upon receiving the substrate bias control start signal 955, the substrate bias generation circuit 903 starts pulling the substrate bias of the 1.8 V system substrate. While the substrate bias is being pulled, the 956 signal is returned to the operation mode control section 913 during the substrate bias control.
- the processor main circuit 902 does not operate while the substrate bias is being pulled. In addition, the current consumption is low due to low leakage current.
- the operation mode control section 913 receives RSET # 952 and cancels the substrate bias control start signal 955.
- the substrate bias generation circuit 903 In response to the release of the substrate bias control start signal 955, the substrate bias generation circuit 903 starts returning the substrate bias of the 1.8 V system substrate to the operating state potential. When the substrate bias is returned, the operation mode control unit 913 is notified using the substrate bias control signal 956.
- the processor chip 901 enters the low power consumption mode and can be restored by resetting.
- the processor chip 901 has a portion where 1.8 V is supplied as a power supply voltage and a portion where 3.3 V is supplied as a power supply voltage.
- the portion to which 1.8 V is supplied is, for example, a processor main circuit 902 or the like.
- This part has a large circuit scale and needs to operate at high speed. Since the circuit scale is large and high-speed operation is required, the power consumption in this part increases.
- the power supply voltage is lowered to reduce the power consumption. Also, if the power supply voltage is lowered (for example, 1.8 V), the operation speed is reduced. Therefore, the threshold voltage of the MOS transistor is lowered (for example, V th (approximately 0.4 V). Further, in this embodiment, the substrate voltage control is performed to reduce the sub-threshold leakage current due to the lower threshold.
- a portion where 3.3 V is supplied as a power supply voltage is, for example, an RTC circuit 914. Since these circuits are small and operate at low speed, they consume little power. Therefore, such a circuit block does not need to lower the power supply voltage. For example, V th> 0.5 V can be set. Since there is no need to lower the threshold value of the MOS transistor, there is an advantage that it is not necessary to take measures against the current by controlling the substrate to reduce the subthreshold leakage current.
- the processor chip 901 of the present embodiment uses both of these power supply voltages. That is, the parts requiring large-scale high-speed operation use the low-voltage low-threshold MOS with substrate control, and use the high-voltage high-threshold MOS without substrate control.
- the method of fabricating MOS transistors with different thresholds can be realized by changing the amount of force channel impeller, which is not particularly limited. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the configuration of the MOS transistor may be increased by increasing the oxide film thickness so that the value is increased. This is because a high threshold value M 0 S operates at a high voltage, so that the oxide film thickness needs to be increased. If the threshold can be increased by making the oxide film thicker, the process can be simplified.
- the input / output circuit 909 needs to transmit and receive an external signal amplitude of 3.3 V, it is desirable to use the same M ⁇ S transistor as the high voltage threshold MOS so that the process can be shared.
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Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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US09/308,488 US6715090B1 (en) | 1996-11-21 | 1997-11-21 | Processor for controlling substrate biases in accordance to the operation modes of the processor |
JP52347998A JP3851663B2 (ja) | 1996-11-21 | 1997-11-21 | 低電力プロセッサ |
EP97913423A EP0943978A4 (en) | 1996-11-21 | 1997-11-21 | PROCESSOR WITH LOW POWER CONSUMPTION |
US10/768,136 US7475261B2 (en) | 1996-11-21 | 2004-02-02 | Substrate bias switching unit for a low power processor |
US11/396,543 US7321252B2 (en) | 1997-11-21 | 2006-04-04 | Semiconductor integrated circuit |
US12/346,268 US7958379B2 (en) | 1996-11-21 | 2008-12-30 | Substrate bias switching unit for a low power processor |
US13/101,678 US8364988B2 (en) | 1996-11-21 | 2011-05-05 | Substrate bias switching unit for a low power processor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP8/310380 | 1996-11-21 | ||
JP31038096 | 1996-11-21 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US09/308,488 A-371-Of-International US6715090B1 (en) | 1996-11-21 | 1997-11-21 | Processor for controlling substrate biases in accordance to the operation modes of the processor |
US09308488 A-371-Of-International | 1997-11-21 | ||
US10/768,136 Continuation US7475261B2 (en) | 1996-11-21 | 2004-02-02 | Substrate bias switching unit for a low power processor |
Publications (1)
Publication Number | Publication Date |
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WO1998022863A1 true WO1998022863A1 (fr) | 1998-05-28 |
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ID=18004560
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PCT/JP1997/004253 WO1998022863A1 (fr) | 1996-11-21 | 1997-11-21 | Processeur a faible consommation d'energie |
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US (4) | US6715090B1 (ja) |
EP (1) | EP0943978A4 (ja) |
JP (1) | JP3851663B2 (ja) |
KR (1) | KR100484699B1 (ja) |
CN (3) | CN1122906C (ja) |
TW (1) | TW382670B (ja) |
WO (1) | WO1998022863A1 (ja) |
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- 1997-11-21 KR KR10-1999-7004444A patent/KR100484699B1/ko not_active IP Right Cessation
- 1997-11-21 CN CN97199916A patent/CN1122906C/zh not_active Expired - Fee Related
- 1997-11-21 CN CNB031075541A patent/CN1270223C/zh not_active Expired - Fee Related
- 1997-11-21 WO PCT/JP1997/004253 patent/WO1998022863A1/ja active IP Right Grant
- 1997-11-21 EP EP97913423A patent/EP0943978A4/en not_active Withdrawn
- 1997-11-21 JP JP52347998A patent/JP3851663B2/ja not_active Expired - Lifetime
- 1997-11-21 US US09/308,488 patent/US6715090B1/en not_active Expired - Lifetime
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2003
- 2003-03-27 CN CN03107553A patent/CN1442768A/zh active Pending
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2004
- 2004-02-02 US US10/768,136 patent/US7475261B2/en not_active Expired - Fee Related
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2008
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US7741869B2 (en) | 2002-10-25 | 2010-06-22 | Renesas Technology Corp. | Low power consumption MIS semiconductor device |
US7928759B2 (en) | 2002-10-25 | 2011-04-19 | Renesas Electronics Corporation | Low power consumption MIS semiconductor device |
CN100419636C (zh) * | 2004-02-18 | 2008-09-17 | 联想(新加坡)私人有限公司 | 控制cpu执行模式的信息处理设备 |
JP2010146474A (ja) * | 2008-12-22 | 2010-07-01 | Hitachi Ltd | 半導体装置 |
JP2010157711A (ja) * | 2008-12-26 | 2010-07-15 | Hynix Semiconductor Inc | 電源分配装置、それを備える集積回路、およびメモリ装置 |
JP2012065070A (ja) * | 2010-09-15 | 2012-03-29 | Fujitsu Ltd | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
TW382670B (en) | 2000-02-21 |
US20110208983A1 (en) | 2011-08-25 |
CN1442769A (zh) | 2003-09-17 |
US8364988B2 (en) | 2013-01-29 |
US7958379B2 (en) | 2011-06-07 |
KR100484699B1 (ko) | 2005-04-22 |
KR20000057158A (ko) | 2000-09-15 |
US20040158756A1 (en) | 2004-08-12 |
EP0943978A1 (en) | 1999-09-22 |
US20100005324A1 (en) | 2010-01-07 |
US7475261B2 (en) | 2009-01-06 |
JP3851663B2 (ja) | 2006-11-29 |
CN1270223C (zh) | 2006-08-16 |
CN1238047A (zh) | 1999-12-08 |
US6715090B1 (en) | 2004-03-30 |
EP0943978A4 (en) | 2006-08-23 |
CN1442768A (zh) | 2003-09-17 |
CN1122906C (zh) | 2003-10-01 |
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