WO1997024622A1 - Circuit electronique a broche d'entree/sortie - Google Patents

Circuit electronique a broche d'entree/sortie Download PDF

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Publication number
WO1997024622A1
WO1997024622A1 PCT/JP1995/002744 JP9502744W WO9724622A1 WO 1997024622 A1 WO1997024622 A1 WO 1997024622A1 JP 9502744 W JP9502744 W JP 9502744W WO 9724622 A1 WO9724622 A1 WO 9724622A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
test
output
voltage generation
common
Prior art date
Application number
PCT/JP1995/002744
Other languages
English (en)
Japanese (ja)
Inventor
Kazumichi Yoshiba
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP18679294A priority Critical patent/JP3605146B2/ja
Priority claimed from JP18679294A external-priority patent/JP3605146B2/ja
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to US08/817,755 priority patent/US6064242A/en
Priority to PCT/JP1995/002744 priority patent/WO1997024622A1/fr
Priority to KR1019960706233A priority patent/KR100230492B1/ko
Publication of WO1997024622A1 publication Critical patent/WO1997024622A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver

Definitions

  • the present invention relates to an I / O pin electronics circuit that enables both an I / 0 common test and an I / 0 separate test.
  • the usual I / O pin electronics circuit is an IZ common pin that has the functions of a dryno (DR) and a comparator (CP) as shown in Fig. 5 (a). .
  • the DR and CP and the device under test (DUT) are connected by a cable with a propagation delay time T.
  • Figure 5 (b) shows a timing diagram when writing and reading operations are repeated.
  • the output data DR 1 from the DR arrives at the DUT end after the time T and becomes the write data W 1.
  • the read data R from the DUT arrives at the CP end after the time T.
  • the data DR 2 must be output from the DR earlier by the time T than the write data W 2 to the DUT.
  • the data DR2 output from the DR arrives at the CP end without time delay. Then, at the CP end, there is a time to input the read data R from the DUT and the data DR 2 output from the own DR.
  • the time for this combination is twice as long as T, during which the CP cannot make a correct comparison.
  • This range is called the IZ0 deadband and is determined by the propagation delay time T between the DR and the CP and the DUT.
  • the output data DR 2 and the read data R from the DUT are synthesized in waveform, but the collision of traveling waves only passes each other and has no effect, and the waveform from the DUT is not affected by the DR end. Since it is terminated, it does not affect the CP end.
  • FIG. 7 shows the case where the I / O common pin is used for the I-separate test in which the path between DR and DUT and the path between DUT and CP are connected by different routes.
  • 1 / ⁇ Common pin CH1 is used as DR and 1/0 common pin CH2 is used as CP.
  • the I / O separate pin shown in Fig. 8 is suitable for the I / O separate test.
  • the I / O separate Can test By connecting the DR and DUT, and the DUT and CP, respectively, the I / O separate Can test.
  • the I / O separation test using the I / 0 common pin requires twice as many I I common pins as when using it as a normal 10 common pin. Therefore, the number of simultaneously measured DUTs is reduced by half. Also, CH1 is used as a DR, so the comparison circuit and comparison voltage generation circuit are wasted, and CH2 is used as a CP, so the waveform shaping circuit and applied voltage generation circuit are wasted, as shown in Figure 8. In addition, the I / ⁇ separation test using the IZ0 separate bin does not waste the comparison circuit, comparison voltage generation circuit, waveform shaping circuit, and applied voltage generation circuit, but tests as the I / ⁇ common pin.
  • the read cycle is terminated at both ends of the DR side and the CP side, so the DUT drive capability is required accordingly.
  • the I0 separate test cannot be performed, and the I0 common test must be performed.
  • the number of wires between the DUT and the semiconductor test equipment is larger in the I / O separate test than in the I / O common test.
  • an IZ0 common test may be required to avoid wiring complications.
  • the present invention performs a comparison circuit, a comparison voltage generation circuit, a waveform shaping circuit, and an application when performing a high-speed device IZ0 separation test in which I0 deadband is a problem
  • the purpose is to realize an I / 0 pin electronics circuit that enables device testing without wasting voltage generator circuits and reducing the number of simultaneously measured DUTs by half. Disclosure of the invention
  • a plurality of drivers for example, two drivers D R1 and D R2 that share the applied Z termination voltage generation circuit and the waveform shaping circuit are provided. Further, at least one of the plurality of drivers, for example, one of DR1 and DR2 is provided with a comparator configured with a comparison circuit and a comparison voltage generation circuit.
  • the applied terminal voltage generating circuit generates three types of voltages. Each voltage is supplied to two drivers, DR 1 and DR 2, through a switch circuit. Each switch circuit includes a PAT (pattern signal) and a DRE (drive enable signal) output from the waveform shaping circuit, and a driver It is controlled by the signals CONT la, CONT lb, CONT 2a and CONT 2b in the control circuit.
  • the comparator is connected to the output of either DR 1 or DR 2.
  • the IZ ⁇ pin electronics circuit configured as described above can perform the I / O common test by setting the DR2 side to DRE control and terminating the DR1 side. Also, by setting the DR1 side to DRE control and setting the DR2 side to the end of CP, an I / O separate test can be executed.
  • FIG. 1 is a block diagram of a 10-pin electronics circuit of the present invention.
  • FIG. 2 is a circuit block diagram when performing an I / O common test with the IZO pin electronics circuit of the present invention.
  • FIG. 3 is a circuit block diagram when a 10-separate test is performed by the 1-pin and 0-pin electronics circuit of the present invention.
  • FIG. 4 is a detailed block diagram and operation explanatory diagram of the I / O pin electronics circuit of the present invention.
  • Figure 5 shows the connection diagram and timing diagram for the IZO common test.
  • Fig. 6 is a connection diagram and timing diagram in the case of an IZO separate test.
  • Fig. 7 is a block diagram of a 10 separate test using a conventional I / O common pin.
  • FIG. 8 is a block diagram of an I / O separate test using a conventional I / O separate pin.
  • BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 shows a schematic block diagram of an IZO pin electronics circuit obtained by branching the DR according to the present invention into two branches, and FIG. 4 shows a detailed block diagram of the circuit.
  • a waveform shaping circuit and an application / termination voltage generation circuit for one channel are assigned to the two branched drivers DR 1 and DR 2, and one of them is provided with a comparison circuit and a comparison voltage generation circuit.
  • CP is connected.
  • the function of the CP is the same as before.
  • the waveform shaping circuit is a circuit that generates a driver pattern (PAT) for switching between high and low levels of DR and a DRE (Driver Enable) pattern for switching between on and off of DR.
  • PAT driver pattern
  • DRE Driver Enable
  • the two-branch DR has a common PAT signal, DRE signal, applied voltages VIH and VIL, and a termination voltage VTT, and only the DR control port is independent for DR1 and DR2.
  • a dry circuit and a control circuit are provided so that it can be carried out.
  • DRE control is performed on the DR 2 side by setting CONT la, CONT 1b, and CONT 2b to logic 0 and CONT 2a to logic 1 in Fig. 4. And generates an output according to the PAT signal.
  • the DR 1 side is in a terminal state to prevent interference. As a result, the operation becomes the same as that of the conventional I Z ⁇ common pin.
  • the DR 1 side is controlled by DRE. And generates an output according to the PAT signal.
  • the DR2 side functions as the terminal of CP.
  • the comparison circuit, the comparison voltage generation circuit, the waveform shaping circuit, and the applied voltage generation circuit are not wasted, and the number of simultaneous measurements is reduced. There is no. Industrial applicability
  • the present invention is configured as described above, and has the following effects.
  • I / 0 separate test can be performed by using DR1 and CP.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Lors de la réalisation d'un essai séparé d'entrée/sortie pour des dispositifs à haute vitesse dans lesquels une bande neutre d'entrée/sortie crée un problème qui s'ajoute à ceux connus avec un essai commun d'entrée/sortie classique, on fait intervenir un circuit de comparaison, un circuit de production de tension de comparaison, un circuit de mise en forme d'onde et un circuit de production de tension appliquée/de terminaison pour former un circuit électronique à broche d'entrée/sortie qui permet de réaliser un essai de dispositifs sans qu'il soit nécessaire de réduire le nombre de dispositifs à essayer simultanément. A cet effet, on utilise deux circuits d'attaque (DR1 et DR2) qui partagent le circuit de production de tension appliquée/de terminaison et le circuit de mise en forme d'onde. Un comparateur pourvu du circuit de comparaison et le circuit de production de tension de comparaison sont reliés à la sortie du circuit DR2. L'essai commun d'entrée/de sortie peut être réalisé par soumission du circuit DR2 à la commande DRE et terminaison du circuit DR1. L'essai séparé d'entrée/de sortie peut être effectué par soumission du circuit DR1 à la commande DRE et terminaison du circuit DRE au niveau du comparateur. Le comparateur peut être placé à la sortie du circuit DR1 au lieu d'être placé à la sortie du circuit DR2.
PCT/JP1995/002744 1994-07-15 1995-12-28 Circuit electronique a broche d'entree/sortie WO1997024622A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18679294A JP3605146B2 (ja) 1994-07-15 1994-07-15 Ｉ／ｏピンエレクトロニクス回路
US08/817,755 US6064242A (en) 1995-12-28 1995-12-28 I/O pin electronics circuit having a pair of drivers
PCT/JP1995/002744 WO1997024622A1 (fr) 1994-07-15 1995-12-28 Circuit electronique a broche d'entree/sortie
KR1019960706233A KR100230492B1 (ko) 1995-12-28 1995-12-28 입/출력 핀 전자 회로

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP18679294A JP3605146B2 (ja) 1994-07-15 1994-07-15 Ｉ／ｏピンエレクトロニクス回路
PCT/JP1995/002744 WO1997024622A1 (fr) 1994-07-15 1995-12-28 Circuit electronique a broche d'entree/sortie

Publications (1)

Publication Number Publication Date
WO1997024622A1 true WO1997024622A1 (fr) 1997-07-10

Family

ID=26436327

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1995/002744 WO1997024622A1 (fr) 1994-07-15 1995-12-28 Circuit electronique a broche d'entree/sortie

Country Status (1)

Country Link
WO (1) WO1997024622A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049330A1 (fr) * 1998-03-26 1999-09-30 Teradyne, Inc. Compensation des effets du temps de propagation aller-retour dans les appareils de controle automatique
WO2001015174A1 (fr) * 1999-08-23 2001-03-01 Sun Microsystems, Inc. Systeme de test de modules de memoire comprenant une faible impedance de sortie de circuit d'attaque
WO2003019213A1 (fr) * 2001-08-31 2003-03-06 Advantest Corporation Instrument d'essai de semi-conducteurs

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6060572A (ja) * 1983-09-13 1985-04-08 Ando Electric Co Ltd Ｉｃテスタ
JPH03255377A (ja) * 1990-03-05 1991-11-14 Nec Corp 集積回路の試験装置
JPH04259868A (ja) * 1991-02-14 1992-09-16 Advantest Corp Ｉｃ試験装置
JPH04305178A (ja) * 1991-04-01 1992-10-28 Advantest Corp 半導体デバイスドライバ回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6060572A (ja) * 1983-09-13 1985-04-08 Ando Electric Co Ltd Ｉｃテスタ
JPH03255377A (ja) * 1990-03-05 1991-11-14 Nec Corp 集積回路の試験装置
JPH04259868A (ja) * 1991-02-14 1992-09-16 Advantest Corp Ｉｃ試験装置
JPH04305178A (ja) * 1991-04-01 1992-10-28 Advantest Corp 半導体デバイスドライバ回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999049330A1 (fr) * 1998-03-26 1999-09-30 Teradyne, Inc. Compensation des effets du temps de propagation aller-retour dans les appareils de controle automatique
WO2001015174A1 (fr) * 1999-08-23 2001-03-01 Sun Microsystems, Inc. Systeme de test de modules de memoire comprenant une faible impedance de sortie de circuit d'attaque
US6442718B1 (en) 1999-08-23 2002-08-27 Sun Microsystems, Inc. Memory module test system with reduced driver output impedance
WO2003019213A1 (fr) * 2001-08-31 2003-03-06 Advantest Corporation Instrument d'essai de semi-conducteurs

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