WO1997011420A1 - Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede - Google Patents

Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede Download PDF

Info

Publication number
WO1997011420A1
WO1997011420A1 PCT/JP1995/001845 JP9501845W WO9711420A1 WO 1997011420 A1 WO1997011420 A1 WO 1997011420A1 JP 9501845 W JP9501845 W JP 9501845W WO 9711420 A1 WO9711420 A1 WO 9711420A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
data
signal
output signal
input signals
Prior art date
Application number
PCT/JP1995/001845
Other languages
English (en)
Japanese (ja)
Inventor
Yasuhisa Shimazaki
Hideo Maejima
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001845 priority Critical patent/WO1997011420A1/fr
Publication of WO1997011420A1 publication Critical patent/WO1997011420A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices

Definitions

  • the present invention relates to a bus control method, a bus control circuit using the same, and a data processing device.
  • the present invention relates to a method for controlling a line for transmitting a group of simultaneously changing signals such as a data bus and an address bus, and more particularly, to an individual collecting circuit such as a microprocessor and a gate array or an integrated circuit thereof via a bus.
  • the present invention relates to a method for reducing the power consumption of the entire g processing unit. Background art
  • the method of reducing the voltage amplitude of the address bus and the data bus requires high-speed data transfer and low power consumption, but has a problem with high reliability because it is very weak against noise. There is.
  • an object of the present invention is to provide an input / output signal control method that more reliably realizes low power consumption when transferring a plurality of signals having the same change point to an address bus, a data bus, and the like, and a bus control using the same. Circuit and data processing equipment.
  • a means for solving the above problem is to input a plurality of input signals (13 1) having the same change point and to output a plurality of output signals (1 1 1) having the same change point.
  • the bus control circuit (100) for outputting 1a) to the bus :-comparing the plurality of input signals with the data on the bus; and, depending on the comparison result, the plurality of input signals or the plurality of signals.
  • the method comprises a step of outputting a signal obtained by processing an input signal to the bus (see FIG. 1).
  • a signal processed in advance is prepared, so that the signal is output to the bus at a high speed based on the comparison result.
  • a bus control circuit (10) that receives multiple input signals (13 1) having the same transition point and outputs multiple output signals (11 11a) having the same transition point to the bus 0)
  • bus control circuit (100) which inputs a plurality of input signals (1 3 1) having the same transition point and outputs a plurality of output signals (1 1 1a) having the same transition point to a bus,
  • Determining means for comparing the output signal of the processing means and the plurality of input signals with the data on the bus, and outputting the selection signal to the selection means in accordance with the comparison result; (See Fig. 1).
  • the determination means performs an exclusive logical operation of the plurality of input signals (131) or the output signal of the processing means and data (110a) on a bus. Take the sum (2 0 2) and output "1" at the exclusive OR output. It is characterized by performing a majority decision (201) between the number of "0” and the number of "0” (see FIGS. 1 and 2).
  • the first bus (71Ob) and the central processing unit (70) connected to the first bus (71Ob) are connected. 1) and the memory module (704)
  • a bus control circuit (100f) provided between the first bus and the second bus,
  • the first bus and the second bus each include a data bus and a status bus for transmitting a status signal indicating a status of data on the data bus,
  • a first processing means for processing data on a data bus of the first bus
  • First selecting means for selecting and outputting one of the data of
  • the output signal of the first processing means or the data on the data bus of the first bus is compared with the data on the data bus of the second bus, and the selection signal is changed according to the comparison result.
  • Determining means for outputting to the selecting means of 1;
  • Second processing means for processing the status signal on the status bus of the first bus
  • a second selection means for selectively outputting one of an output signal of the second processing means and a status signal on a status bus of the first bus according to the selection signal. It is characterized by having (see FIGS. 7 and 8).
  • FIG. 1 is a block diagram of an LSI circuit configuration showing one embodiment of the present invention.
  • FIG. 2 is a block diagram of an LSI circuit configuration showing a specific example of the determination circuit 102 in FIG.
  • FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG.
  • FIG. 4 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG.
  • FIG. 5 is a diagram showing the operation timing of FIG.
  • FIG. 6 is a diagram showing the operation timing of FIG.
  • FIG. 7 is a block diagram showing an embodiment of a microprocessor system to which the present invention is applied.
  • Figure 8 is a c Fig. 9 is a diagram showing an internal circuit of FIG. 7 of the bus control mechanism 1 0 0 f is a block diagram showing an embodiment of a microprocessor system according to the present invention is there.
  • FIG. 10 is a block diagram of an LSI circuit configuration showing an embodiment in which the present invention is applied to a system having a dynamic bus.
  • FIG. 11 is a block diagram of an LSI circuit configuration showing another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram showing an embodiment of the present invention.
  • Reference numeral 130 denotes a logic module constituted by an LSI circuit, which outputs an output signal 131 constituted by 32 bits and an input signal 132 constituted by 32 bits.
  • 100 is a bus control mechanism using the present invention.
  • 104 a is an inverter that receives the output signal 13 1 as an input and outputs a polarity inversion signal for each bit.
  • 101 a is a select signal 107, and an output signal when '"0" A selector that outputs 1 3 1 and outputs the output signal 13 la of the inverter 10 4 a when "1-" is output.
  • 102 is the output signal of the output signal 13 1 and the latch 10 3.
  • 105 a and 105 b respectively output the output signal of the selector 10 la and the select signal 107 in the timing controlled by the output buffer control signal 121, the data output signal 11 la, Output buffer to output as status output signal 1 1 2a.
  • 103 is a latch that holds the data input signal 11 lb by the latch control signal 120
  • 104b is an inversion that receives the data input signal 111b and outputs the polarity inversion signal of each bit.
  • 1 1 b outputs the data input signal 1 1 1 b when the status input signal 1 1 2 is “0” and outputs the output signal 1 1 1 c of the inverter 1 0 4 b when the status input signal 1 2 is “1” Selector.
  • Reference numeral 110 denotes a bus, which comprises a 32-bit data bus 110a and a 1-bit status bus 11Ob.
  • decision circuit 102 is shown in FIG. In the figure, 200 is 3 A match decision circuit composed of two exclusive ORs 202 and taking an exclusive OR between corresponding bits of the output signal 131 and the latch signal 106.
  • Reference numeral 201 denotes a circuit which outputs “1” when the number of bits that become “1” among the output bits of the match determination circuit 200 is 17 bits or more, and outputs “0” when the number of bits is 16 bits or less.
  • the voting circuit is a voting circuit, and the output from the majority circuit 201 is a select signal 10
  • data "FFFFFFFFh” is about to be sent from the CPU 300 to the cache memory 301 via the bus 110a.
  • a latch control signal 1 2 immediately before the data output operation from the CPU 300 is started, and which is determined to rise during a period in which the data on the data bus 110 a is valid.
  • the decision circuit 102 receives the output signal “FFFFFFFFh” from the CPU 300 and the signal “0 0 0 0 0 0 0 0 0h” in the latch 103.
  • the selector 101a selects and outputs the non-inverted signal, that is, the output signal "FFFFOOOOh" of the CPU 300 itself. Then, when the output buffer control signal rises at the timing shown in Fig. 6, the output signal of selector 101a and the select signal 107 become output buffer 105a as in the case of Fig. 3. To the data bus 110a via 105b Is forced. In the cache memory 310 that receives data on the data bus 110a, the selector 101b is supplied with the signal '0' on the status bus 110b so that the signal on the data bus is supplied to the selector 101b. "FFFFOOOOh" is selected by the selector 101b and transmitted to the cache memory 301.
  • the above-described operation can be performed without any problem not only between the CPU and the cache memory, but also between other modules sharing the same bus and exchanging data via the bus.
  • the number of logical transitions on the data bus can be reduced to less than half of the total number of bits of the data bus, that is, 16 or less for 32 bits, and charging and discharging of the data bus occurs. Since the number of bits is 16 bits or less, the power consumed by the data bus can be reduced to less than half of the conventional level, and the influence of noise on the power supply line and GND line can be reduced to half of the conventional level. Can be done.
  • the latch 103 since the latch 103 constantly monitors the data bus and holds the signal currently on the bus, the other module can be used one cycle earlier.
  • the number of logical transitions on the data bus can be reduced to 16 bits or less even when data is output to the data bus c .
  • the bus width is 32 bits.
  • the inverter 104 a for processing (inverting) the signal inverts the signal before the select signal 107 from the decision circuit 102 is generated.
  • the inversion can also be started by inputting a select signal to the inverter. In this case, the power consumption required for the processing is reduced because it is first known whether the processing labor is required.
  • a signal processed in advance is prepared, so that the signal is output to the bus at high speed based on the comparison result (select signal).
  • a selector is connected in parallel with an inverting buffer and a non-inverting buffer, and one of the buffers is activated by a select signal.
  • the inversion buffer functions as an inverter, the inverter 104a becomes unnecessary.
  • both the inverted signal and the non-inverted signal can be output at high speed by the select signal, and low power consumption is realized because one of the buffers is in an inactive state.
  • FIG. 1 a processing means for exchanging the positions of specific bits of a plurality of input signals may be used.
  • both the output signal of the processing means and the plurality of input signals are compared with the data on the bus to determine which signal can reduce the number of polarity inversion bits.
  • reference numeral 200 denotes a microprocessor system that constitutes a data processing device, which includes a microprocessor 700 and a memory chip 72. 0, logic chip 7 21, no, 's 7 110 c. Each chip shares the bus 710c via the bus control mechanism 100i, 100g, and 100h according to the present invention.
  • the microprocessor 700 comprises a CPU 701, a memory module 704, a logic module 705, and a node 710b, and each module is a bus control mechanism 100 according to the present invention.
  • the bus 71Ob is shared via c, 100d, and 100e.
  • the CPU 701 comprises an ALU 702, a register 703, and a bus 710a, and a bus control mechanism 100a-, 100b via the bus control mechanism according to the present invention. Sharing.
  • the problem here is the data transfer between the bus 710b and the bus 710c.
  • the bus control mechanism 100f here does not have the same configuration as that shown in FIG.
  • FIG. 8 is a diagram showing an internal circuit of the bus control mechanism 100f.
  • a circuit for performing data transfer from the bus 7110b to the bus 7110c is shown.
  • a circuit for transferring data from the bus 71 0 c to the bus 71 Ob is also configured by exactly the same circuit.
  • the feature here is that there is a selector that inputs the status signal from the status bus through the inverter and the signal as it is, and determines whether to invert based on the output signal (select signal) of the judgment circuit. That is.
  • select signal select signal
  • the status signal is "1", but when the data is inverted and transferred to the bus 710c, the status signal of the bus 710c becomes "0". In this way, by using the bus control mechanism of FIG. 8, it is possible to realize low power consumption in data transfer between buses while retaining the inversion / non-inversion information of the transfer data.
  • the present invention can be applied to all buses in the microprocessor system 2000, and the number of logical transitions on the bus is reduced to less than half of the conventional bus. Can be reduced to less than half of the conventional one.
  • FIG. 10 shows an embodiment in which the present invention is applied to a dynamic bus system having a bus precharge device.
  • reference numeral 901 denotes a bus precharge device for precharging the data bus 110a to a power supply voltage at a predetermined timing
  • reference numeral 900 denotes a bus precharge device, which is connected to a power supply. FFFFFFFFh ". With this configuration, the same effect as in the case of FIG. 1 can be expected.
  • the decision circuit 102 a firstly outputs the output signal 13 1 and each bit corresponding to the latch signal 106, which is the output signal of the latch 103, every byte. , That is, bit 31 to bit 24, bit 23 to bit 16, bit 15 to bit 8, and bit 7 to bit 0 for comparison.
  • bit 31 to bit 24 bit 23 to bit 16, bit 15 to bit 8, and bit 7 to bit 0 for comparison.
  • "1" is output as a select signal from a set having 5 or more bits having different logical values
  • "0" is output as a select signal otherwise. I do.
  • the selector 1 0 1 c 1 Pas It is configured so that it is possible to control whether to select the output signal 1311 or the polarity inversion signal 1331a for each unit.
  • 110d is a 4-bit status bus. It serves to transmit the status output signal 1 1 2 c to other modules. According to the status input signal 112d, the selector 101d selects either the data input signal 111b or its polarity-inverted signal 111c for each byte and outputs it.
  • the logic transition of the plurality of signals is reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un procédé de commande des signaux d'entrée et de sortie destiné à un traitement à faible puissance, un circuit de commande de bus et un processeur utilisant ledit procédé de commande quand une pluralité de signaux ayant le même point de changement sont transférés à un bus d'adressage, un bus de données, etc. Pour réaliser cet objectif, dans un circuit de commande de bus (100) destiné à introduire une pluralité de signaux (131) ayant le même point de changement et à émettre une pluralité de signaux (111a) ayant le même point de changement au niveau d'un bus, le procédé comprend une étape d'inclusion d'une pluralité de signaux d'entrée dans des données au niveau du bus, et une étape d'émission, à destination du bus, d'une pluralité de signaux ou des signaux obtenus par le traitement de ces signaux d'entrée. Le procédé permet de connaître le nombre de bits inversés entre les données et les signaux de sortie qui existent pratiquement au niveau du bus de destination, et de réduire de manière fiable la consommation d'énergie.
PCT/JP1995/001845 1995-09-18 1995-09-18 Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede WO1997011420A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/001845 WO1997011420A1 (fr) 1995-09-18 1995-09-18 Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/001845 WO1997011420A1 (fr) 1995-09-18 1995-09-18 Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede

Publications (1)

Publication Number Publication Date
WO1997011420A1 true WO1997011420A1 (fr) 1997-03-27

Family

ID=14126265

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1995/001845 WO1997011420A1 (fr) 1995-09-18 1995-09-18 Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede

Country Status (1)

Country Link
WO (1) WO1997011420A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005025765A (ja) * 2003-07-03 2005-01-27 Samsung Electronics Co Ltd データ反転を有するメモリシステム及びメモリシステムにおけるデータ反転方法
US6946867B2 (en) 2002-08-21 2005-09-20 Nec Corporation Data output circuit and data output method
JP2007511828A (ja) * 2003-11-13 2007-05-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ パックワードをバスを介して送信する電子データ処理回路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05333979A (ja) * 1992-05-28 1993-12-17 Mitsubishi Electric Corp 信号伝搬装置
JPH0720973A (ja) * 1993-07-01 1995-01-24 Sony Corp バス駆動回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05333979A (ja) * 1992-05-28 1993-12-17 Mitsubishi Electric Corp 信号伝搬装置
JPH0720973A (ja) * 1993-07-01 1995-01-24 Sony Corp バス駆動回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946867B2 (en) 2002-08-21 2005-09-20 Nec Corporation Data output circuit and data output method
JP2005025765A (ja) * 2003-07-03 2005-01-27 Samsung Electronics Co Ltd データ反転を有するメモリシステム及びメモリシステムにおけるデータ反転方法
JP4667773B2 (ja) * 2003-07-03 2011-04-13 三星電子株式会社 データ反転を有するメモリシステム及びメモリシステムにおけるデータ反転方法
JP2007511828A (ja) * 2003-11-13 2007-05-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ パックワードをバスを介して送信する電子データ処理回路

Similar Documents

Publication Publication Date Title
US5448703A (en) Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
US8713298B2 (en) Fast and compact circuit for bus inversion
US20160364348A1 (en) Systems and Methods Involving Data Bus Inversion Memory Circuitry, Configuration(s) and/or Operation
JPH0463573B2 (fr)
US6883053B2 (en) Data transfer control circuit with interrupt status register
JP3316001B2 (ja) 半導体メモリに対するデータ伝達方法およびこの方法を実施するための半導体メモリ
KR19990067846A (ko) 버스 시스템 동작 방법 및 장치
JPS6035696B2 (ja) デ−タ処理装置における母線制御装置
KR20020069008A (ko) 두 개의 프로세서를 포함하는 시스템 및 컴퓨팅 장치
JPH11509950A (ja) Ｎ本未満のｉ／ｏピンを伴うｎビットのデータバス幅をもつマイクロコントローラ及びそのための方法
US6253298B1 (en) Synchronous SRAM having pipelined enable
WO1997011420A1 (fr) Procede de commande de bus, circuit de commande de bus et processeur utilisant ledit procede
JP3425443B2 (ja) パイプライン化されたデータの順序決めシステム
KR100449721B1 (ko) 서로 다른 데이터 버스 폭을 갖는 장치들을 위한인터페이스 및 이를 이용한 데이터 전송방법
US20010046176A1 (en) Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines
US20040006664A1 (en) System and method for efficient chip select expansion
JP2580325B2 (ja) デ―タ伝送方式、デ―タ出力回路およびデ―タ入力回路
US6034545A (en) Macrocell for data processing circuit
JPH09274796A (ja) 半導体装置および半導体システム
JPH06161620A (ja) 出力同時変化制御方式
JP3119618B2 (ja) データ処理装置
WO1997032333A1 (fr) Procede et dispositif de reduction du temps de latence sur une interface, par chevauchement des paquets transmis
US7519755B2 (en) Combined command and response on-chip data interface for a computer system chipset
JP2536912B2 (ja) バス制御方式
US6060908A (en) Databus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase