WO1997011420A1

WO1997011420A1 - Bus control method, and bus control circuit and data processor using the bus control method

Info

Publication number: WO1997011420A1
Application number: PCT/JP1995/001845
Authority: WO
Inventors: Yasuhisa Shimazaki; Hideo Maejima
Original assignee: Hitachi, Ltd.
Priority date: 1995-09-18
Filing date: 1995-09-18
Publication date: 1997-03-27

Abstract

An input/output signal control method for low power operation, and a bus control circuit and a data processor using this control method when a plurality of signals having the same change point are transferred to an address bus, a data bus, etc. As the construction for accomplishing this object, in a bus control circuit (100) for inputting a plurality of signals (131) having the same change point and outputting a plurality of signals (111a) having the same change point to a bus, the method includes a step of comprising a plurality of input signals with data on the bus and a step of outputting a plurality of signals or those signals which are obtained by processing these input signals, to the bus. According to this method, the number of inverted bits between the data and the output signals existing practically on the bus of the destination can be known, and power consumption can be reliably reduced.

Description

Specification

TECHNICAL FIELD The present invention relates to a bus control method, a bus control circuit using the same, and a data processing device.

The present invention relates to a method for controlling a line for transmitting a group of simultaneously changing signals such as a data bus and an address bus, and more particularly, to an individual collecting circuit such as a microprocessor and a gate array or an integrated circuit thereof via a bus. The present invention relates to a method for reducing the power consumption of the entire g processing unit. Background art

In recent years, LSIs represented by microphone-mouth processors have become more sophisticated and faster. Under such circumstances, there is a problem that the power consumption in the LSI increases remarkably due to an increase in the scale of logic accompanying higher functionality and an increase in operating frequency accompanying higher speed. In particular, the load capacity of address buses and data buses has increased significantly due to the increase in logic, so if a situation occurs in which data on the bus changes frequently, power consumption will only increase. In addition, the influence on the power supply line and the GND line also increases.

Speaking of the power consumption due to charge and discharge due to data changes on the bus, methods to reduce the power consumption by reducing the number of bits in the address bus and data bus, and to reduce the voltage swing of the address bus and data bus Methods to reduce power consumption have been adopted.

Although not paying attention to low power consumption, a method of reducing the number of bits for which the polarity of the output signal to the data bus is inverted to reduce the influence of noise on the power supply line and the GND line is disclosed in It is disclosed in Japanese Patent Publication No. 161620. Disclosure of the invention

In the case of high-speed and high-reliability data transfer of a processor, the above-described method of reducing the number of bits of the address bus and the data bus significantly limits the amount of data that can be transferred at one time. There is a problem with the transfer.

In addition, the method of reducing the voltage amplitude of the address bus and the data bus requires high-speed data transfer and low power consumption, but has a problem with high reliability because it is very weak against noise. There is.

On the other hand, the invention described in Japanese Patent Application Laid-Open No. 6-161620 not only reduces noise, but also without reducing the number of bus bits and without reducing the bus voltage amplitude. The present inventors have clarified that low power consumption in bus charging and discharging can be realized.

Then, in order to solve the above-mentioned problems, the inventors studied to apply the invention disclosed in Japanese Patent Application Laid-Open No. H6-161620 to a processor. In this case, the inventors have confirmed that the invention described in the above publication can be applied to the transfer of the address signal.

However, in the above publication, since the number of polarity inversion bits between the previous output signal and the next output signal of the IC is determined, a system in which a plurality of logic modules share one bus is used. On the other hand, it has been clarified by the inventors that the power consumption is not sufficiently reduced. For example, if another module is outputting an address or data to the bus one cycle before, the actual address or data on the bus is used as the previous output signal of the IC. Therefore, the number of polarity inversion bits on the bus cannot be reduced. Accordingly, an object of the present invention is to provide an input / output signal control method that more reliably realizes low power consumption when transferring a plurality of signals having the same change point to an address bus, a data bus, and the like, and a bus control using the same. Circuit and data processing equipment.

According to an embodiment of the present invention, a means for solving the above problem is to input a plurality of input signals (13 1) having the same change point and to output a plurality of output signals (1 1 1) having the same change point. In the bus control circuit (100) for outputting 1a) to the bus:-comparing the plurality of input signals with the data on the bus; and, depending on the comparison result, the plurality of input signals or the plurality of signals. The method comprises a step of outputting a signal obtained by processing an input signal to the bus (see FIG. 1).

According to this method, since actually it is found polarity reversal number of bits between the data and the output signal present at the output destination of the bus, _c attained reliably power consumption In this way, processing the signal The steps to be performed may be performed earlier than the step of comparison, may be performed later, or may be performed almost simultaneously.

If the processing is performed first, a signal processed in advance is prepared, so that the signal is output to the bus at a high speed based on the comparison result.

If it is performed later, the power consumption required for processing is reduced because it is first known whether the labor for processing is required.

If performed simultaneously, high speed and low power consumption are realized.

Also, according to another embodiment of the present invention,

A bus control circuit (10) that receives multiple input signals (13 1) having the same transition point and outputs multiple output signals (11 11a) having the same transition point to the bus 0)

Processing means (104a) for processing the plurality of input signals;

Selecting means (101a) for inputting the output signal of the processing means and the plurality of input signals, and selectively outputting one of the output signal of the processing means and the plurality of input signals according to a selection signal;

Determining means for comparing the output signal or the plurality of input signals of the processing means with the data on the bus and outputting the selection signal to the selection means in accordance with the comparison result; (See Fig. 1).

Further, according to another embodiment of the present invention,

In a bus control circuit (100) which inputs a plurality of input signals (1 3 1) having the same transition point and outputs a plurality of output signals (1 1 1a) having the same transition point to a bus,

Processing means (104a) for exchanging the position of a specific bit of the plurality of input signals;

Determining means for comparing the output signal of the processing means and the plurality of input signals with the data on the bus, and outputting the selection signal to the selection means in accordance with the comparison result; (See Fig. 1).

Further, according to a preferred embodiment of the present invention, the determination means performs an exclusive logical operation of the plurality of input signals (131) or the output signal of the processing means and data (110a) on a bus. Take the sum (2 0 2) and output "1" at the exclusive OR output. It is characterized by performing a majority decision (201) between the number of "0" and the number of "0" (see FIGS. 1 and 2).

Furthermore, according to the embodiment in which the present invention is applied to the data processing device, the first bus (71Ob) and the central processing unit (70) connected to the first bus (71Ob) are connected. 1) and the memory module (704)

A second bus (710c), a memory chip (720) connected to the second bus (710c),

A bus control circuit (100f) provided between the first bus and the second bus,

The first bus and the second bus each include a data bus and a status bus for transmitting a status signal indicating a status of data on the data bus,

A first processing means (inverter) for processing data on a data bus of the first bus;

The output signal of the first processing means and the data on the data bus of the first bus are input, and the output signal of the first processing means and the data bus of the first bus are input by a selection signal. First selecting means (selector) for selecting and outputting one of the data of

The output signal of the first processing means or the data on the data bus of the first bus is compared with the data on the data bus of the second bus, and the selection signal is changed according to the comparison result. Determining means (determining circuit) for outputting to the selecting means of 1;

Second processing means (inverter) for processing the status signal on the status bus of the first bus;

The output signal of the second processing means and the status bus of the first bus A second selection means (selector) for selectively outputting one of an output signal of the second processing means and a status signal on a status bus of the first bus according to the selection signal. It is characterized by having (see FIGS. 7 and 8).

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of an LSI circuit configuration showing one embodiment of the present invention.

FIG. 2 is a block diagram of an LSI circuit configuration showing a specific example of the determination circuit 102 in FIG.

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 4 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG.

FIG. 5 is a diagram showing the operation timing of FIG.

FIG. 6 is a diagram showing the operation timing of FIG.

FIG. 7 is a block diagram showing an embodiment of a microprocessor system to which the present invention is applied.

Figure 8 is a _c Fig. 9 is a diagram showing an internal circuit of FIG. 7 of the bus control mechanism 1 0 0 f is a block diagram showing an embodiment of a microprocessor system according to the present invention is there.

FIG. 10 is a block diagram of an LSI circuit configuration showing an embodiment in which the present invention is applied to a system having a dynamic bus.

FIG. 11 is a block diagram of an LSI circuit configuration showing another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in more detail with reference to examples.

One embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 130 denotes a logic module constituted by an LSI circuit, which outputs an output signal 131 constituted by 32 bits and an input signal 132 constituted by 32 bits. 100 is a bus control mechanism using the present invention.

104 a is an inverter that receives the output signal 13 1 as an input and outputs a polarity inversion signal for each bit. 101 a is a select signal 107, and an output signal when '"0" A selector that outputs 1 3 1 and outputs the output signal 13 la of the inverter 10 4 a when "1-" is output. 102 is the output signal of the output signal 13 1 and the latch 10 3. As a result of comparing the corresponding bits of the switch signal 106, when the number of bits having different logical values is 17 bits or more, "1-" is output as a select signal, otherwise, This is a decision circuit that outputs "0" as a select signal. 105 a and 105 b respectively output the output signal of the selector 10 la and the select signal 107 in the timing controlled by the output buffer control signal 121, the data output signal 11 la, Output buffer to output as status output signal 1 1 2a. 103 is a latch that holds the data input signal 11 lb by the latch control signal 120, and 104b is an inversion that receives the data input signal 111b and outputs the polarity inversion signal of each bit. 1 1 b outputs the data input signal 1 1 1 b when the status input signal 1 1 2 is “0” and outputs the output signal 1 1 1 c of the inverter 1 0 4 b when the status input signal 1 2 is “1” Selector. Reference numeral 110 denotes a bus, which comprises a 32-bit data bus 110a and a 1-bit status bus 11Ob.

One specific example of the decision circuit 102 is shown in FIG. In the figure, 200 is 3 A match decision circuit composed of two exclusive ORs 202 and taking an exclusive OR between corresponding bits of the output signal 131 and the latch signal 106.

Reference numeral 201 denotes a circuit which outputs “1” when the number of bits that become “1” among the output bits of the match determination circuit 200 is 17 bits or more, and outputs “0” when the number of bits is 16 bits or less. The voting circuit is a voting circuit, and the output from the majority circuit 201 is a select signal 10

Equivalent to 7.

Next, the overall operation of this embodiment will be described with reference to FIGS.

In the initial state, it is assumed that data “000000” is output from the main memory 302 to the data bus 110a.

In the case of FIG. 3, data "FFFFFFFFh" is about to be sent from the CPU 300 to the cache memory 301 via the bus 110a. First, a latch control signal 1 2 immediately before the data output operation from the CPU 300 is started, and which is determined to rise during a period in which the data on the data bus 110 a is valid. When the power starts up at the timing shown in Fig. 5, the data '0 0 0 0 0 0 0 Oh' on the bus 110a at that time is latched. Then, the decision circuit 102 receives the output signal “FFFFFFFFh” from the CPU 300 and the signal “0 0 0 0 0 0 0 0h” in the latch 103. Since it is input, "1" is output as the select signal 107. On the other hand, the output signal "FFFFFFFFh" from the? Although "0 0 0 0 0 0 0 0 h" is input, the polarity inversion signal "0 0 0 0 0 0 0 0 h" side is selected because the select signal 107 is "1". The output buffer control signal is then output as shown in Fig. 5. It rises in to Thailand Mi ring, out Kanoku Ffa 1 0 5 a, 1 0 5 b, respectively selector 1 0 1 a output of. Outputs select signal 107 to data bus 110a and status bus 110b. At this time, “0 0 0 0 0 0 0 0 h” and its polarity inverted signal “FFFFFFFF h” are stored in the selector 101 b of the cache memory 310 that receives the data on the data bus 110a. Is input, but since the signal on the status bus 110b is "1", the polarity inversion signal "FFFFFFFFh" side is selected and transmitted to the cache memory 301, and therefore output from the CPU. The data has been successfully sent to the cache memory. At this time, when observing the data bus 110a, the data output from the main memory one cycle ago and the data output from the output buffer 105a just before are the same. 0h ", it can be seen that there is no transition on the data bus 110a.

Next, as shown in FIG. 4, consider a case where data "FFFFOOOOh" is sent from the CPU 300 to the cache memory 301 via the bus 110a. As in the case of FIG. 3, when the latch control signal 120 rises at the timing shown in FIG. 6, the data “0 0 0 0 0” on the data bus 110 a at that time 0 00 h ”is captured in latch 103. The output signal “FFFFOOOOh” from the CPU 300 and the signal “0 0 0 0 0 0 0 0h” in the latch 103 are input to the judgment circuit 102, but this time both data As a result of comparing these bits, since the number of bits having different logical values is 16 bits, "0" is output as the select signal 107. Therefore, the selector 101a selects and outputs the non-inverted signal, that is, the output signal "FFFFOOOOh" of the CPU 300 itself. Then, when the output buffer control signal rises at the timing shown in Fig. 6, the output signal of selector 101a and the select signal 107 become output buffer 105a as in the case of Fig. 3. To the data bus 110a via 105b Is forced. In the cache memory 310 that receives data on the data bus 110a, the selector 101b is supplied with the signal '0' on the status bus 110b so that the signal on the data bus is supplied to the selector 101b. "FFFFOOOOh" is selected by the selector 101b and transmitted to the cache memory 301. In this case, when observing the data bus 110a, the data output from the main memory one cycle ago is obtained. Since "OOOOOOOOh" and the data output just from the output buffer 105a, "" FFFF0000Oh ", the data bus 110a transitions only 16 bits. You know what happens.

It goes without saying that the above-described operation can be performed without any problem not only between the CPU and the cache memory, but also between other modules sharing the same bus and exchanging data via the bus. According to the present embodiment, the number of logical transitions on the data bus can be reduced to less than half of the total number of bits of the data bus, that is, 16 or less for 32 bits, and charging and discharging of the data bus occurs. Since the number of bits is 16 bits or less, the power consumed by the data bus can be reduced to less than half of the conventional level, and the influence of noise on the power supply line and GND line can be reduced to half of the conventional level. Can be done.

Also, as shown in the present embodiment, since the latch 103 constantly monitors the data bus and holds the signal currently on the bus, the other module can be used one cycle earlier. In this embodiment, the number of logical transitions on the data bus can be reduced to 16 bits or less even when data is output to the data bus _c . In this embodiment, the bus width is 32 bits. Although the case has been described, the same effect can be expected with other bit numbers by increasing or decreasing the bit number of each block in FIG. As shown in this embodiment, the present invention can be applied to high-speed data transfer because the present invention does not reduce the data transfer efficiency.

In FIG. 1, the inverter 104 a for processing (inverting) the signal inverts the signal before the select signal 107 from the decision circuit 102 is generated. The inversion can also be started by inputting a select signal to the inverter. In this case, the power consumption required for the processing is reduced because it is first known whether the processing labor is required.

Of course, in the circuit of Fig. 1, a signal processed in advance is prepared, so that the signal is output to the bus at high speed based on the comparison result (select signal). As another method, it is conceivable that a selector is connected in parallel with an inverting buffer and a non-inverting buffer, and one of the buffers is activated by a select signal. In this case, since the inversion buffer functions as an inverter, the inverter 104a becomes unnecessary. In this case, both the inverted signal and the non-inverted signal can be output at high speed by the select signal, and low power consumption is realized because one of the buffers is in an inactive state.

In addition, although an inverter is used in FIG. 1, a processing means for exchanging the positions of specific bits of a plurality of input signals may be used.

In this case, both the output signal of the processing means and the plurality of input signals are compared with the data on the bus to determine which signal can reduce the number of polarity inversion bits.

Next, an embodiment in which the present invention is applied to the entire microprocessor system will be described with reference to FIG.

In FIG. 7, reference numeral 200 denotes a microprocessor system that constitutes a data processing device, which includes a microprocessor 700 and a memory chip 72. 0, logic chip 7 21, no, 's 7 110 c. Each chip shares the bus 710c via the bus control mechanism 100i, 100g, and 100h according to the present invention. Next, the microprocessor 700 comprises a CPU 701, a memory module 704, a logic module 705, and a node 710b, and each module is a bus control mechanism 100 according to the present invention. The bus 71Ob is shared via c, 100d, and 100e. Further, the CPU 701 comprises an ALU 702, a register 703, and a bus 710a, and a bus control mechanism 100a-, 100b via the bus control mechanism according to the present invention. Sharing.

The problem here is the data transfer between the bus 710b and the bus 710c. The bus control mechanism 100f here does not have the same configuration as that shown in FIG.

FIG. 8 is a diagram showing an internal circuit of the bus control mechanism 100f. Here, for simplicity, only a circuit for performing data transfer from the bus 7110b to the bus 7110c is shown. Actually, a circuit for transferring data from the bus 71 0 c to the bus 71 Ob is also configured by exactly the same circuit. The feature here is that there is a selector that inputs the status signal from the status bus through the inverter and the signal as it is, and determines whether to invert based on the output signal (select signal) of the judgment circuit. That is. As a result, when data is transferred from the bus 710b to the bus 710c, if the data on the bus 710b is an inverted signal, the status of the bus 710b is changed. The status signal is "1", but when the data is inverted and transferred to the bus 710c, the status signal of the bus 710c becomes "0". In this way, by using the bus control mechanism of FIG. 8, it is possible to realize low power consumption in data transfer between buses while retaining the inversion / non-inversion information of the transfer data. With the above configuration, the present invention can be applied to all buses in the microprocessor system 2000, and the number of logical transitions on the bus is reduced to less than half of the conventional bus. Can be reduced to less than half of the conventional one.

Further, as shown in FIG. 9, an embodiment in which the status bus 800 is shared by the entire microprocessor system 2000 is also possible.

FIG. 10 shows an embodiment in which the present invention is applied to a dynamic bus system having a bus precharge device. In FIG. 10, reference numeral 901 denotes a bus precharge device for precharging the data bus 110a to a power supply voltage at a predetermined timing, and reference numeral 900 denotes a bus precharge device, which is connected to a power supply. FFFFFFFFh ". With this configuration, the same effect as in the case of FIG. 1 can be expected.

Next, an embodiment in which the present invention is applied by dividing 32 bits of data for each byte will be described with reference to FIG. In FIG. 11, the decision circuit 102 a firstly outputs the output signal 13 1 and each bit corresponding to the latch signal 106, which is the output signal of the latch 103, every byte. , That is, bit 31 to bit 24, bit 23 to bit 16, bit 15 to bit 8, and bit 7 to bit 0 for comparison. As a result, "1" is output as a select signal from a set having 5 or more bits having different logical values, and "0" is output as a select signal otherwise. I do. Since each-select signals from the set four sets of each byte are output,-select signal 1 0 7 a is in response to _c it becomes total 4 bits Bok signal, the selector 1 0 1 c 1 Pas It is configured so that it is possible to control whether to select the output signal 1311 or the polarity inversion signal 1331a for each unit. 110d is a 4-bit status bus. It serves to transmit the status output signal 1 1 2 c to other modules. According to the status input signal 112d, the selector 101d selects either the data input signal 111b or its polarity-inverted signal 111c for each byte and outputs it. By configuring the bus control mechanism 100b as described above, the same effects as in the embodiment shown in FIG. 1 can be expected.

As described in detail above, according to the present invention, when driving a plurality of signals having the same change point, such as an address bus and a data bus, the logic transition of the plurality of signals is reduced. In addition to reducing the influence of noise on the power supply line and the GND line, it is possible to realize an input / output signal control method applicable to high-speed data transfer.

Claims

The scope of the claims

1. In a bus control circuit that inputs multiple input signals having the same transition point and outputs multiple output signals having the same transition point to the bus,

Comparing the plurality of input signals with data on the bus, and outputting the plurality of input signals or a signal obtained by processing the plurality of input signals to the bus in accordance with a result of the comparison. I / O signal control method.

2. In the input / output signal control method according to claim 1,

The input / output signal control method according to claim 1, wherein the step of processing the signal is performed before the step of comparing.

3. In the input / output signal control method according to claim 1,

An input / output signal control method, wherein the step of processing the signal is performed after the step of comparing.

4. In the input / output signal control method according to claim 1,

The input / output signal control method, wherein the step of processing the signal is performed substantially simultaneously with the step of comparing.

5. In a bus control circuit that inputs multiple input signals having the same transition point and outputs multiple output signals having the same transition point to the bus,

Processing means for processing the plurality of input signals;

Selecting means for inputting the output signal of the processing means and the plurality of input signals, and selectively outputting one of the output signal of the processing means and the plurality of input signals according to a selection signal;

A bus for comparing the output signal of the processing means or the plurality of input signals with the data on the bus, and outputting the selection signal to the selection means in accordance with the comparison result; Control circuit.

6. The bus control circuit according to claim 5,

The determination means calculates an exclusive OR of the plurality of input signals or the output signal of the processing means and data on the bus, and determines a majority of the number of "1" and the number of "0" in the exclusive OR output. A bus control circuit for making a determination.

7. In a bus control circuit that inputs multiple input signals with the same transition point and outputs multiple output signals with the same transition point to the bus,

Processing means for exchanging the positions of specific bits of the plurality of input signals; inputting the output signal of the processing means and the plurality of input signals; and selecting the output signal of the processing means and the plurality of input signals by a selection signal Selecting means for selecting and outputting one of

A bus for comparing the output signal of the processing means and the plurality of input signals with the data on the bus, and outputting the selection signal to the selection means in accordance with the comparison result; Control circuit.

8. The bus control circuit according to claim 7,

The determining means performs an exclusive OR of the plurality of input signals and the output signal of the processing means with the data on the bus, and determines the majority of the number of "1" and the number of "0" in the exclusive OR output. A bus control circuit that specializes in making judgments.

9. A first bus, a central processing unit and a memory module connected to the first bus,

A second bus, a memory chip connected to the second bus, and a bus control circuit provided between the first bus and the second bus;

The first bus and the second bus each include a data bus and a status bus for transmitting a status signal indicating a status of data on the data bus. The bus control circuit comprises: first processing means for processing data on a data bus of the first bus;

The output signal of the first processing means and the data on the data bus of the first bus are inputted, and the output signal of the first processing means and the data bus of the first bus are inputted by a selection signal. First selecting means for selecting and outputting one of the data of

The output signal of the first processing means or the data on the data bus of the first bus is compared with the data on the data bus of the second bus, and the selection signal is changed according to the comparison result. Determining means for outputting to the first selecting means; second processing means for processing a status signal on the status bus of the first bus;

The output signal of the second processing means and the status signal on the status bus of the first bus are input, and the output signal of the second processing means and the status bus of the first bus are input by the selection signal. A second selection means for selecting and outputting one of the status signals.