JP2000295088A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of an EMI(electromagnetic interference) while corresponding to an acceleration request of an output operation by reducing the occurrence of noise involved in output simultaneous change by setting output driving capability small when the number of output terminals whose output level changes surpasses a preliminarily set prescribed number. SOLUTION: A data latch circuit 5 latches output data 2a to 2n of a logic circuit part 2. An output buffer circuit 4 drives respective output terminals 3a to 3n on the basis of latch outputs 5a to 5n. The circuit 4 is configured by parallelly connecting a tri-state buffer 41 whose driving capability is large and a buffer 42 whose driving capability is small. A logical level change number monitoring circuit 6 compares the current output state with the next output state, and when the number of terminals whose output states are inverted surpasses a preliminarily set allowable value, outputs a signal 6a which indicates the number of changed terminals is too large. An output buffer capability control circuit 7 makes the buffer 41 a non-operational state only for a prescribed period and lowers output driving capability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an address bus,
The present invention relates to an output circuit that outputs a multi-bit signal to a multi-bit parallel signal line such as a data bus and a control bus.
The current output state is compared with the state to be output next, and when the number of terminals at which the logic level changes exceeds a predetermined value, the output buffer is set to have a small driving capability, which is generated when the output state is switched. Reduce instantaneous current changes,
The present invention relates to an output circuit configured to reduce high-frequency noise generated by an instantaneous current change.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication (Kokai) No. 3-121617 discloses that a drive capability of an output buffer can be changed by a signal from an external terminal, thereby preventing a malfunction during simultaneous operation of an output buffer circuit. A CMOS integrated circuit is described. This CMOS integrated circuit includes a plurality of output buffer circuits having different driving capabilities, a plurality of transfer gates provided between the plurality of output terminals and the output terminals, and a plurality of transfer gates provided by a selection signal input from an external terminal. And a means for controlling the transfer gate. This makes it possible to prevent power supply fluctuations due to simultaneous operation of the output buffer circuits that could not be found at the time of circuit design by lowering the drive capability of the output buffer based on an external signal at the time of evaluation.

Japanese Patent Application Laid-Open No. 4-278716 discloses an output buffer circuit which reduces noise generated when a large number of output buffer circuits having large driving capabilities operate simultaneously. In this output buffer circuit, a main buffer circuit and a parallel buffer circuit are connected in parallel. The parallel buffer circuit is configured to be in an inactive state based on the off-pulse signal. Further, the output buffer circuit includes an off-pulse generation circuit that generates an off-pulse signal for a predetermined period from the time when the logic level of the input signal changes. Therefore, when the output of the buffer circuit makes a transition, the output terminal and the load connected to the output terminal are first driven only by the main buffer circuit, and then both the main buffer circuit and the parallel buffer circuit are driven. The buffer circuit drives the output terminal and the load connected to the output terminal. As a result, the time for charging and discharging the load applied to the output terminal is delayed, and the generation of noise is reduced.

Japanese Patent Application Laid-Open No. Hei 5-75427 discloses that a current for charging and discharging a stray capacitance of a power supply wiring and a ground wiring is reduced,
A semiconductor integrated circuit device capable of stably operating a logic circuit by reducing noise due to a transient current is described. In this semiconductor integrated circuit device, an output buffer circuit having a small driving capability and a tristate output buffer circuit having a large driving capability are provided in parallel. When the simultaneous change of the output of the logic circuit is large (when there are a plurality of output terminals and the number of output terminals whose output level changes from H level to L level or from L level to H level at a predetermined timing is large, ), The tri-state output buffer circuit having a large driving capability is controlled to a non-operating state, and the output driving is performed using only the output buffer circuit having a small driving capability.
Thereby, when the simultaneous change of the output of the logic circuit is large, the transient current is suppressed to be small, and the noise due to the transient current is reduced.

Japanese Patent Application Laid-Open No. 5-175746 discloses an output buffer in which the effect of noise generated on a ground line when a plurality of output buffers operate simultaneously on the output terminal level of another output buffer is reduced. Has been described. In this output buffer, a switching buffer (tristate buffer) having a large driving capability and a level holding buffer having a small driving capability are connected in parallel.
Then, the data to be output and the actual output value are compared by a comparison circuit, and the switching buffer (tri-state buffer) is controlled to be off (non-driving state) during the period when both match. Thus, when the output terminal level of the output buffer does not change, the noise generated on the ground line due to the change of the output terminal level of the other output buffer can be reduced only through the level holding buffer having a small driving ability. And the effect of noise can be reduced.

Japanese Unexamined Patent Publication No. Hei 6-161620 discloses a simultaneous output change control method in a logic circuit having a simultaneous change signal group such as a data bus in which the influence on a power supply and a ground during simultaneous output drive is reduced. Have been. In this simultaneous output change control method, in a circuit that inputs a plurality of input signals having the same change point and outputs from a plurality of output terminals, means for inverting a plurality of input signal polarities identically, Means for selectively outputting a non-inverted input signal; and selecting an input signal on the side where the number of polarity inversions at the time of a signal change at the output terminal is smaller, from the inverted / non-inverted input signal. The polarity inversion / non-inversion information is output. The receiving side receives a correct signal by inverting / non-inverting the signal based on the polarity inversion / non-inversion information.

Further, a circuit configuration for reducing an instantaneous current change generated at the time of switching the output state and reducing high-frequency noise generated due to the instantaneous current change,
9 to 11 are conceivable.

FIG. 9 is a circuit configuration diagram of an address drive circuit in which address data is represented by a gray code to reduce high frequency noise accompanying driving of an address bus or the like. The address drive circuit 600 shown in FIG. 9 includes a binary up / down counter 601 and a gray code generation circuit 602.

A binary up / down counter 601
Is up / supplied to the operation mode designation terminal MODE.
Up-counter operation and down-counter operation can be switched based on the down mode designation signal. In the up counter operation mode, the counter value is incremented (+1) in synchronization with, for example, the rising edge of the clock signal supplied to the clock input terminal CLK. In the down counter operation mode, the counter value is decremented (−1) in synchronization with, for example, the rising edge of the clock signal supplied to the clock input terminal CLK. DO0 to DO7 are output terminals for the counter value. The binary type up / down counter 601 clocks the preset data (preset value) supplied to the preset data (preset value) input terminals DI0 to DI7 by supplying, for example, an H level load signal to the load signal input terminal LOAD. For example, the preset data (preset value) taken in in synchronization with, for example, the rising edge of the signal CLK can be set as a counter initial value. Then, by stopping the supply of the load signal, it is possible to perform the increment from the preset counter value.

The Gray code generation circuit 602 has seven 2
Input exclusive OR circuits 602a to 602g are provided. To each input terminal of each of the two-input exclusive OR circuits 602a to 602g, signals of adjacent two bits of the counter outputs DO0 to DO7 are supplied, respectively. The gray code generation circuit 102 includes seven 2-input exclusive OR circuits 602a.
An 8-bit gray code consisting of 7 bits output of .about.602g and the most significant bit DO7 of the counter output is output. The gray code output signal generated by the gray code generation circuit 602 is supplied to an address bus or the like as address designation signals A0 to A7.

The Gray code is a code in which two adjacent Hamming distances are one. Therefore, by using the Gray code as the addressing signal, two
Only one bit can change between two addresses. Therefore, when specifying addresses sequentially in ascending or descending order, the addressing signal is only one.
Since only one bit changes, it is possible to reduce the occurrence of high-frequency noise due to driving of the address bus and the like.

FIG. 10 is a circuit diagram of a continuously variable output-capacity output circuit in which the H-level drive ability and the L-level drive ability can be continuously varied. 10 includes a pre-buffer circuit (inverting buffer circuit) including an enhancement-type P-channel transistor 701 and an enhancement-type N-channel transistor 702, an enhancement-type P-channel transistor 703, and an enhancement-type And a main buffer circuit (inverting buffer circuit) including an N-channel transistor 704. Reference numeral 705 indicates an input terminal, reference numeral 706 indicates an output terminal, and reference numeral 70
Reference numeral 7 denotes a voltage input terminal for setting an L level driving capability, and reference numeral 708
Is an H level drive capability setting voltage input terminal.

The logic level signal supplied to input terminal 705 is supplied to the gate of P-channel transistor 701 and the gate of N-channel transistor 702.
The L-level drive capability setting voltage supplied to the L-level drive capability setting voltage input terminal 707 is applied to the source of the P-channel transistor 701. The H-level driving capability setting voltage supplied to the H-level driving capability setting voltage input terminal 708 is applied to the source of the N-channel transistor 702. The drain of P-channel transistor 701 and the drain of N-channel transistor 702 are connected to each other, and the connection point is connected to the gate of P-channel transistor 703 and the gate of N-channel transistor 704. The source of the P-channel transistor 703 is connected to the circuit power supply V +. N
The source of the channel transistor 704 is connected to the ground. The drain of the P-channel transistor 703 and the drain of the N-channel transistor 704 are connected to each other, and the connection point is connected to the output terminal 706. The H level of the output signal output from the output terminal 706 is set based on the circuit power supply V +, and the L level of the output signal is set.
The level is set by the ground potential.

When the signal input to input terminal 705 is at L level, N-channel transistor 702 is turned off and P-channel transistor 701 is turned on. When the P-channel transistor 701 is turned on, an L-level driving capability setting voltage is supplied to the gates of the transistors 703 and 704 constituting the main buffer circuit. Here, the L level driving capability setting voltage is
A voltage at which the P-channel transistor 703 is turned off and higher than the threshold voltage of the N-channel transistor 704 (a voltage higher than the gate-source threshold voltage of the N-channel transistor 704 with respect to the ground potential) ). Therefore, when an L-level drivability setting voltage is supplied to the gates of the transistors 703 and 704, the P-channel transistor 703 is turned off, the N-channel transistor 704 is turned on, and the output terminal 706 is set to the L level ( (Ground potential). Here, the source-gate voltage of the N-channel transistor 704 driven to the on state is
Voltage input terminal 707 for setting ground and L level driving capability
By changing the L-level drive capability setting voltage, the source-gate voltage of the N-channel transistor 704 can be adjusted, and the drive capability of the N-channel transistor 704 can be controlled.

When the signal input to input terminal 705 is at H level, P-channel transistor 701 is turned off and N-channel transistor 702 is turned on. When the N-channel transistor 702 is turned on, the H-level drive capability setting voltage is supplied to the gates of the transistors 703 and 704 constituting the main buffer circuit. Here, the voltage for setting the H level driving capability is
A voltage at which the N-channel transistor 704 is turned off and which is higher than the threshold voltage of the P-channel transistor 703 (the source-gate threshold voltage of the P-channel transistor 704 with respect to the potential of the positive power supply V +) Is also set to a low voltage). Therefore, when an H-level drive capability setting voltage is supplied to the gates of transistors 703 and 704, N-channel transistor 70
4 is turned off, the P-channel transistor 703 is driven to the on state, and the output terminal 706 is driven to the H level (the potential of the positive power supply V +). Here, since the voltage between the source and the gate of the P-channel transistor 703 driven in the ON state is a difference between the potential of the positive power supply V + and the voltage for setting the H level driving capability, the voltage for setting the HL level driving capability is changed. By doing so, the source-gate voltage of the P-channel transistor 703 can be adjusted, and the driving capability of the P-channel transistor 703 can be controlled.

FIG. 11 is a circuit diagram of a drive capability switching type output circuit in which the H-level drive capability and the L-level drive capability can be varied stepwise. The variable drive capability switching type output circuit 300 shown in FIG.
01 and an output circuit 802. The output control circuit 801 sequentially generates data (output data signal) QS to be output at a predetermined cycle or the like based on a clock signal (not shown) or the like, and outputs the generated data to the data output terminal Q. The output control circuit 801 supplies an H-level output enable signal OES to the output enable signal output terminal OE at a timing at which data is to be output.

The output control circuit 801 has output drive capability setting input terminals DS0 and DS1 for setting the output drive capability in four stages. The output drive capability can be set in the following four stages based on a 2-bit output drive capability setting signal supplied to each output drive capability setting input terminal DS0, DS1. (First stage) L level driving capability,
H level driving capability is small, (second stage) L level driving capability is small, H level driving capability is large, (3rd stage) L level driving capability is large, H level driving capability is small, (L level) Both driving capability and H level driving capability are large.

When the first-stage driving capability is set, the output control circuit 801 outputs an H-level driving capability control output terminal H
An L-level signal is output to D, and an L-level signal is output to the L-level drive capability control output terminal LD. When the second-stage driving capability is set, the output control circuit 801 outputs an H-level signal to the H-level driving capability control output terminal HD and outputs an L-level signal to the L-level driving capability control output terminal LD. I do. When the third-stage driving capability is set, the output control circuit 801 outputs an L-level signal to the H-level driving capability control output terminal HD and outputs an H-level signal to the L-level driving capability control output terminal LD. I do. The output control circuit 801 outputs H
An H level signal is output to the level drive capability control output terminal HD, and an H level signal is output to the L level drive capability control output terminal LD.

The output circuit 802 includes a first drive circuit including a P-channel transistor 803 and an N-channel transistor 804, a second drive circuit including a P-channel transistor 805 and an N-channel transistor 806, and a two-input OR gate 807. , A two-input NAND gate 808, an inverter 809, a two-input NOR gate 810, and a two-input AND gate 811. Reference numeral 812 is an output terminal. Each P-channel transistor 8
Sources 03 and 805 are connected to the positive power supply V +. Each source of each of the N-channel transistors 804 and 806 is connected to the ground. The drains of the transistors 803 to 806 are connected to the output terminal 812.

The output enable signal OES is supplied to one input terminal of a two-input NAND gate 808. Also,
Output enable signal OES is inverted by inverter 809 and supplied to one input terminal of a two-input NOR gate. When output enable signal OES supplied from output control circuit 801 is at L level, the output of 2-input NAND gate 808 is at H level, and this H-level signal is supplied to the gate of P-channel transistor 803 and the 2-input The signal is supplied to the gate of the P-channel transistor 803 via the OR gate 807. Thus, when the output enable signal OES is at the L level, the gates of the P-channel transistors 803 and 805 are both supplied with the H-level, so that the P-channel transistors 803 and 805 are both turned off. On the other hand, when output enable signal OES is at L level, an H level signal is supplied to 2-input NOR gate 810 via inverter 809, so that the output of 2-input NOR gate 810 is at L level, and this L level is at N channel. Since the power is supplied to the gate of the transistor 804, the N-channel transistor 804 is turned off. Further, the N-channel transistor 8 is connected via a two-input AND gate 811.
Since the L level is supplied to the gate of the transistor 06, the N-channel transistor 806 is turned off. Therefore, when output enable signal OES is at L level,
All the transistors 803 to 806 are turned off,
The output terminal 812 is in a high impedance state.

When the H level driving capability control signal HDS is at H level, the H level is supplied to the gate of the P channel transistor 805 via the 2-input OR gate 807, so that the P channel transistor 805 is turned off.
When the L level driving capability control signal LDS is at L level, 2
Since the L level is supplied to the gate of the N-channel transistor 806 via the input AND gate 811, the N-channel transistor 806 is turned off.

When the output driving capability is set to the first stage (both L level driving capability and H level driving capability are small), the H level driving capability control signal HDS is set to H level, and the L level driving capability control is performed. Signal LDS is set to L level. When H-level drive capability control signal HDS is at H level, L-level drive capability control signal LDS is at L level, and output enable signal OES is at H level, P-channel transistor 803 and N-channel transistor 804 Thus, the output terminal 812 can be driven using the first drive circuit composed of When output data signal QS is at H level, 2-input NAND gate 8
08 is at the L level, and this L level is supplied to the gate of the P-channel transistor 803, so that the P-channel transistor 803 is driven to the ON state. On the other hand, when output data signal QS is at H level, the output of 2-input NOR gate 810 is at L level, and this L level is supplied to the gate of N-channel transistor 804, so that N-channel transistor 804 is turned off.
Therefore, when output data signal QS is at H level, P-channel transistor 803 is turned on, N-channel transistor 804 is turned off, and output terminal 8 is turned off.
12 is driven to H level. Output data signal QS is L
In the case of the level, the P-channel transistor 803 is turned off and the N-channel transistor 804 is turned on, so that the output terminal 812 is driven to L level. In the above state, since the output drive is performed using only the first drive circuit, both the H-level output drive ability and the L-level output drive ability are small.

When the output driving capability is set to the above-described second stage (the L level driving capability is small and the H level driving capability is large), the H level driving capability control signal HDS is set to the L level, and the L level is set to the L level. Driving ability control signal LDS is set to L level. When the H level drive capability control signal HDS becomes L level, the output of the two-input NAND gate 803 is output via the two-input OR gate 807 to the P-channel transistor 80.
5 gates. Therefore, when output data signal QS is at H level, both P-channel transistors 803 and 805 are turned on, and output terminal 812 is set to H level via each P-channel transistor 803 and 805.
Drive to the level. Therefore, the driving capability at the time of driving at the H level is large.

When the output driving capability is set to the above-described third stage (the L level driving capability is large and the H level driving capability is small), the H level driving capability control signal HDS is set to the H level, and the L level is set to the L level. Driving capability control signal LDS is set to H level. When the L level drive capability control signal HDS becomes H level, the output of the two-input NOR gate 810 is output to the N-channel transistor 80 via the two-input AND gate 811.
6 is supplied to the gate. Therefore, when output data signal QS is at L level, both N-channel transistors 804 and 806 are turned on, and output terminal 812 is set to L-level via each N-channel transistor 804 and 806.
Drive to the level. For this reason, the driving capability at the time of L-level driving is large.

When the output driving capability is set to the above-described fourth stage (both L level driving capability and H level driving capability are large), the H level driving capability control signal HDS is set to L level, and the L level driving capability control is performed. Signal LDS is set to H level. In this state, each P-channel transistor 8
The output terminal 812 is driven to H level by 03,805, and the output terminal 812 is driven to L level by each N-channel transistor 804,806. Therefore, both the H level driving and the L level driving have a large driving capability.

Therefore, the drive capability switching type output circuit 800 shown in FIG. 11 can set a suitable drive capability in accordance with the load connected to the output terminal 812.

[0027]

Problems to be Solved by the Invention
In the CMOS integrated circuit described in Japanese Patent Application Laid-Open No. 7-107, the driving capability of the output buffer can be changed by a signal from an external terminal. Thus, even when the output states of a plurality of output buffers change simultaneously, the potential shift of the power supply line and the ground line can be reduced, and malfunction can be prevented. However, if the driving capability of the output buffer is reduced, the delay of the output signal is increased, so that high-speed operation may not be supported.

The output buffer circuit described in Japanese Patent Application Laid-Open No. 4-278716 discloses that when the output of the buffer circuit transitions, first the output is driven only by the main buffer circuit and then both the main buffer circuit and the parallel buffer circuit are driven. Since the output driving is performed by the buffer circuit, the time for charging and discharging the load applied to the output terminal can be delayed, and the generation of noise can be reduced. However, when the output of the buffer circuit makes a transition, the charge / discharge time for the load is always delayed, so that the signal delay time until the logic level on the load side is determined increases.

In the semiconductor integrated circuit device described in Japanese Patent Application Laid-Open No. 5-75427, when the simultaneous change of the output of the logic circuit is large, the output is driven only by using the output buffer circuit having a small driving capability, thereby making the transient. The current can be kept small. However, since output driving is performed by an output buffer circuit having a small driving capability, wiring from an output terminal to a bus or the like connected to the output terminal and an input terminal to a next-stage circuit or the like receiving a signal output from the output terminal. The time required for the voltage of the signal transmission path to reach the predetermined logic level potential is later than when the output driving is performed using a tri-state output buffer circuit having a large driving capability. For this reason, if a next-stage circuit or the like that receives a signal output from the output terminal captures an output signal at a timing when the logic level potential is determined when a tri-state output buffer circuit having a large driving capability is used in combination, There is a risk that abnormal logic levels will be captured. Therefore, in a circuit device or an electronic system that operates in synchronization with the clock, the clock cycle is limited by the signal delay time when the output is driven using only the output buffer circuit having a small driving capability. Therefore, high-speed operations of the circuit device, the electronic system, and the like are restricted.

In the output buffer described in Japanese Patent Application Laid-Open No. 5-175746, the noise generated in the ground line propagates to the output terminal of another buffer via the ground line of another buffer outputting L level. Can be reduced. However, when the previous output logic level is different from the next output logic level, a switching buffer (tristate buffer) having a large driving ability is used until the next output logic level matches the actual output logic level. Buffer) is driven, so if there is a large simultaneous change in the output of a logic circuit or the like (there are multiple output terminals,
When the number of output terminals whose output level changes from the H level to the L level or from the L level to the H level at a predetermined timing is large), the charging / discharging current flowing at the time of switching increases, and noise due to a transient current may occur. There is.

In the simultaneous output change control method described in Japanese Patent Application Laid-Open No. 6-161620, when a plurality of signals to be output are output as they are (non-inverted signal output), a plurality of signals to be output are inverted respectively. When the signal is output (inverted signal output), the number of polarity inversions at the time of signal change at the output terminal is compared, and the one with the smaller number of polarity inversions at the time of signal change at the output terminal is selected and output. The number of polarity inversions at the time of a signal change at the output terminal can be reduced, and the influence of noise on power supply and ground due to simultaneous output driving can be reduced. However, on the receiving side of the output signal, it is necessary to perform signal inversion / non-inversion processing based on the polarity inversion / non-inversion information. Therefore, both the output side device and the input side device that receives the signal output from the output side device need to support the simultaneous output change control method. Further, a wiring for transmitting polarity inversion / non-inversion information is newly required.

The gray code-based address drive circuit shown in FIG. 9 is effective in reducing noise when addresses change in ascending or descending order, but reduces noise generation when non-consecutive addresses are specified. I can't.

In the output circuit with continuously variable driving capability shown in FIG. 10, a power supply and the like for supplying a driving capability setting voltage are separately required, and the circuit configuration including peripheral circuits becomes complicated. Since there is a trade-off relationship between the driving capability and the output delay time, it is difficult to respond to a demand for high-speed data output.

The drive capability switching type output circuit shown in FIG. 11 can set a suitable output drive capability in accordance with the load condition, but it is difficult to respond to a demand for high-speed data output.

[0035]

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem. In an output circuit for outputting a plurality of bits of data at a predetermined timing such as a timing synchronized with a clock signal, a plurality of bits output earlier are output. When the number of output terminals at which the output level changes exceeds a predetermined number, the output drive capability is set to a small value to generate noise due to simultaneous output changes. The output circuit that ensures reliable data transmission by changing the output signal reception timing for the circuit that receives the output signal when the output drive capability is set to a small value while reducing the output drive capability The purpose is to do.

[0036]

According to an aspect of the present invention, there is provided an output circuit for comparing a current logic level state with a logic level state to be output next and changing an output logic level. A logic level change terminal count monitoring circuit that outputs a logic level change terminal count excess signal when the calculated number of terminals exceeds a predetermined logic level change allowable number of terminals, and a logic level change terminal count excess signal And an output buffer capacity control circuit for reducing the driving capacity of the output buffer circuit based on the

In the output circuit according to the first aspect, when the number of terminals at which the output level is inverted is large, the driving capability of the output buffer circuit is reduced. If the number of terminals at which the output level is inverted is large, higher-frequency noise may be generated.
In such a case, by reducing the driving capability of the output buffer circuit, the transient current can be reduced even when many outputs are inverted at the same time, and the occurrence of high-frequency noise can be reduced.
When the number of terminals at which the output level is inverted is small, the output cycle can be shortened because the driving capability of the output buffer circuit is not reduced.

The output buffer circuit can be configured by connecting a buffer circuit having a small driving capability and a tristate buffer circuit having a large driving capability in parallel.

In this case, the driving capability can be increased by using both the buffer circuit and the tri-state buffer circuit, and the tri-state buffer circuit can be switched to a small driving capability by controlling the tri-state buffer circuit to a non-operating state.

Further, the output buffer circuit may be configured by connecting a tri-state buffer circuit having a small driving capability and a tri-state buffer circuit having a large driving capability in parallel.

In this case, by using only a tri-state buffer circuit having a small driving ability, a state having a small driving ability can be realized. Further, by using only a tri-state buffer circuit having a large driving capability, or by using both tri-state buffer circuits together, a state having a large driving capability can be realized. Further, by controlling both the tri-state buffer circuits to the non-operating state, the output terminal can be used also as the input terminal.

According to a fourth aspect of the present invention, a drive level of the output buffer circuit is reduced based on the logic level change terminal number monitoring circuit and the logic level change terminal excess signal, and the drive capacity of the output buffer circuit is lowered. And an output buffer capacity control circuit for generating an output indeterminate state signal for inhibiting the capture of the output signal in synchronization with the state of the output buffer.

In the output circuit according to the present invention, when a large number of outputs are simultaneously inverted, the driving capability of the output buffer circuit is reduced, whereby the transient current can be suppressed and the occurrence of high frequency noise can be reduced. In a state where the driving capability of the output buffer circuit is reduced, the delay time until the logic level of the output signal is determined increases. Therefore, the output circuit according to claim 4 is configured to output an output indeterminate state signal, so that a circuit that receives a signal supplied from the output circuit, a device side, or the like outputs an output indeterminate state signal based on the output indeterminate state signal. By delaying the reception timing of the supplied signal, reception of an abnormal signal can be prevented.

According to a fifth aspect of the present invention, there is provided an output circuit for driving a plurality of terminal groups based on a plurality of bits of a parallel signal sequentially generated in synchronization with a clock from a logic circuit portion, wherein an output driving capability is varied. An output buffer circuit, a logic level change terminal number monitoring circuit, and a drive capability of the output buffer circuit for a predetermined clock period based on the logic level change terminal excess signal. A pause request signal for temporary suspension is generated in synchronization with the period during which the driving capability of the output buffer circuit is reduced, and further, the output request signal is synchronized with the period during which the driving capability of the output buffer circuit is decreasing. And an output buffer capacity control circuit for generating an output indeterminate state signal for inhibiting capture.

In the output circuit according to the fifth aspect, when a large number of outputs are simultaneously inverted, the driving capability of the output buffer circuit is reduced, whereby the transient current can be suppressed and the occurrence of high frequency noise can be reduced. The output circuit according to claim 5 can suspend the operation of the logic circuit unit by supplying the suspension request signal to the logic circuit unit.
As a result, the operation of generating new output data can be temporarily stopped, and the occurrence of missing data to be output can be prevented. In a state where the driving capability of the output buffer circuit is reduced, the delay time until the logic level of the output signal is determined increases. Therefore, the output circuit according to claim 5 is configured to output an output indeterminate state signal, so that a circuit receiving a signal supplied from the output circuit, a device side, etc., output the output circuit based on the output indeterminate state signal. By delaying the reception timing of the signal supplied from the communication device, it is possible to prevent an abnormal signal from being received.

It should be noted that a configuration may be employed in which a clock enable signal indicating whether the clock is valid or invalid is used as the output indeterminate state signal.

In this case, the circuit or device that receives the signal supplied from the output circuit delays the reception timing of the signal supplied from the output circuit based on the clock enable signal to receive an abnormal signal. Can be prevented.

According to a seventh aspect of the present invention, in the output circuit for driving a plurality of terminal groups based on a plurality of bits of a parallel signal sequentially generated from a logic circuit portion in synchronization with a clock, the output drive capability is varied. An output buffer circuit, a logic level change terminal number monitor circuit, and a drive capability of the output buffer circuit for a predetermined clock period based on the logic level change terminal excess signal, and supply of a clock to the logic circuit unit. The operation of the logic circuit unit is stopped for a predetermined clock period by stopping only for a predetermined clock period, and the supply of a clock to another circuit unit that captures signals output to a plurality of terminals in synchronization with the clock is performed for a predetermined clock period. During the period in which the driving capability of the output buffer circuit is reduced by stopping only Composed of an output buffer capacity control circuit for stopping the capture of the signal applied to.

In the output circuit according to the present invention, when a large number of outputs are simultaneously inverted, the driving capability of the output buffer circuit is reduced, whereby the transient current can be suppressed and the occurrence of high frequency noise can be reduced. The output circuit according to claim 7 can temporarily stop the operation of the logic circuit unit by stopping the supply of the clock to the logic circuit unit. As a result, the operation of generating new output data can be temporarily stopped, and the occurrence of missing data to be output can be prevented. In a state where the driving capability of the output buffer circuit is reduced, the delay time until the logic level of the output signal is determined increases. Therefore, the output circuit according to claim 7 temporarily suspends the supply of the clock to the circuit that receives the signal supplied from the output circuit, the other circuit unit such as the device side, so that the other circuit unit is illegal. I try not to take in data.

An output circuit according to claim 8 is a data latch circuit for latching a plurality of bits of parallel signals sequentially generated from a logic circuit section in synchronization with a clock, and a plurality of bits of parallel signals latched by the data latch circuit. An output buffer circuit that can drive a plurality of terminals based on the output and can vary the output drive capability, a parallel signal of a plurality of bits latched by the data latch circuit, and a next output supplied to the input side of the data latch circuit. The number of terminals whose logic level state changes by comparing the parallel signal of a plurality of bits to be obtained is obtained, and the obtained number of terminals is compared with a predetermined number of allowable logic level change terminals, and the obtained number of terminals is obtained. Outputs an excessive number of logic level change terminals signal indicating that the number of logic level change terminals is too large when exceeds the number of allowable logic level change terminals. That it consists of a logic level change terminal number monitoring circuit, an output buffer capacity control circuit to reduce the drive capacity of the output buffer circuit based on the logic level change number of terminals excessive signal.

According to an eighth aspect of the present invention, a data latch circuit latches a parallel signal of a plurality of bits output from a logic circuit section in synchronization with a clock, and supplies the latched output to an output buffer circuit to output a plurality of signals. Drive the output terminal. The logic level change terminal number monitoring circuit is configured to output a logic level change terminal based on the multi-bit parallel signal latched by the data latch circuit and the next multi-bit parallel signal to be output to the input side of the data latch circuit. It is determined whether the number is excessive. When the number of logic level change terminals is excessive, by reducing the driving capability of the output buffer circuit,
Suppresses transient current and reduces high frequency noise generation.

As described above, the output circuit according to the present invention comprises:
Since the drive capability of the output circuit is switched according to the number of terminals whose output level is inverted, the output drive capability is set to a high state when the number of output level inverting terminals is small (when high-frequency noise is less generated). By holding the data, it is possible to output data and the like at high speed. Then, only when the number of output level inverting terminals is large (when there is a possibility that large high-frequency noise is generated), the output drive capability is reduced, and the generation of high-frequency noise is prevented by suppressing the transient current. Therefore, by applying the output circuit according to the present invention, it is possible to meet the demand for high-speed circuit operation and to reduce the EMI.
(Electromagnetic interference) can be solved.

[0053]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a first embodiment of the output circuit according to the present invention. The output circuit 1 shown in FIG. 1 is connected to a plurality of output terminals 3a to 3n and a plurality of output terminals 3a to 3n based on n-bit output signals (output control signals) 2a to 2n supplied from a logic circuit unit 2. Drive the load (not shown). The output circuit 1 includes an output buffer circuit 4, a data latch circuit 5, a logic level change terminal number monitoring circuit 6, and an output buffer capacity control circuit 7.

The logic circuit 2 sequentially generates and outputs n-bit output signals 2a to 2n based on a clock signal CLK supplied from a clock signal generation circuit (not shown) and control input information (not shown). Logic circuit part 2
When the temporary stop request signal 7a is not supplied from the output buffer capacity control circuit 7, the n-bit output signals 2a to 2n are sequentially generated and output in synchronization with the clock signal CLK. The logic circuit unit 2 includes an output buffer capacity control circuit 7
, The output signals 2a to 2n that are currently being output are held, and while the pause request signal 7a is being supplied, new output signals 2a to 2n are generated and output. Stop operation. Code C
I is an input terminal of the clock signal CLK, Q0 to Qn are output terminals of n-bit output signals 2a to 2n, and WI is an input terminal of the pause request signal 7a.

The output buffer circuit 4 has output terminals 3a to 3a.
3n is provided with n output drivers 4a to 4n.
Each of the output driving units 4a to 4n is configured by connecting a buffer circuit 41 (41a to 41n) having a small driving capability and a tristate buffer circuit 42 (42a to 42n) having a large driving capability in parallel. The tri-state buffer circuit 42
When the buffer operation control signal 7b of, for example, H level for requesting buffer activation is supplied from the output buffer capacity control circuit 7, the operation state is set, and the output is performed according to the logic level supplied to the input terminal of the tristate buffer circuit 42. Drive. The tri-state buffer circuit 42 enters a non-operating state when a buffer operation control signal 7b at L level, for example, requesting buffer deactivation is supplied. In this non-operating state, the output terminal of the tri-state buffer circuit 42 is in a high impedance state. Therefore, by controlling the tri-state buffer circuit 42 to the operating state, the buffer circuit 41 and the tri-state buffer circuit 4 are controlled.
2 can be used in combination to drive the output terminal 3 (in a state where the driving capability is large), and the tri-state buffer circuit 42
Is controlled to a non-operating state, the output terminal 3 can be driven only by the buffer circuit 41 (a state in which the driving capability is small).

The tri-state buffer circuit 42 having a large driving capability is connected to an output terminal and a load (not shown) connected to the output terminal in a sufficiently short time of about 1/10 of a period of a clock signal described later. ) To a predetermined logic level potential (load drive capability)
Having. The buffer circuit 41 having a small driving ability has the ability to change the output load to a predetermined logic level potential over a period of about one cycle of the clock signal.

Data latch circuit 5 latches output signals Q0-Qn from logic circuit section 2 supplied to data input terminals DI0-DIn based on a latch control signal 7c supplied from output buffer capacity control circuit 7, The latched signal is output to data output terminals DO0 to DOn. Sign L
TI is a latch control signal input terminal. Latch output signals 5a to 5n output to data output terminals DO0 to DOn
Is supplied to the output buffer circuit 4 and also to the logic level change terminal number monitoring circuit 6.

The logic level change terminal number monitoring circuit 6 includes latch output signals 5a to 5n which are outputs of the data latch circuit 5.
(The current output logic level state) is compared with the output signals Q0 to Qn (the logic level state to be output next) of the logic circuit unit 2, and the number of bits at which the logic level changes (the output logic level changes) Number of output terminals), and compares the obtained number of bits (the number of output terminals at which the output logical level changes) with a predetermined number of allowable logic level change bits (the number of allowable logic level change terminals). If (the number of output terminals at which the output logical level changes) exceeds the number of logical level change allowable bits (the number of logical level change allowable terminals), an excessive logic level change terminal number signal 6a is output. The logic level change terminal excess signal 6a is supplied to the output buffer capacity control circuit 7. The symbol NOW is the latch output signal 5
a to 5n (current output logic level state) input terminal group,
Reference symbol NEXT denotes an input terminal group of output signals Q0 to Qn (the logic level state to be output next) of the logic circuit unit 2 and reference symbol OV.
O is an output terminal of the logic level change terminal excess signal 6a.

When the excessive logic level change terminal number signal 6a is not supplied, the output buffer capacity control circuit 7 generates and outputs a latch control signal 7c synchronized with the clock signal CLK, and requests the buffer activation. For example, it outputs an H-level buffer operation control signal 7b. The output buffer capability control circuit 7 outputs the temporary stop request signal 7a and outputs the temporary stop request signal 7a during the period of one cycle of the next clock when the excessive logic level change terminal number signal 6a is supplied. During this period, the buffer operation control signal 7b of, for example, L level requesting the buffer deactivation is output. Further, when the output buffer capability control circuit 7 outputs the temporary stop request signal 7a, it temporarily stops the output of the latch control signal 7c. This allows
It inhibits the data latch circuit 5 from latching a new output signal and keeps the current latch state. Reference numeral CKI denotes an input terminal of the clock signal CLK, reference numeral OVI denotes an input terminal of the logic level change terminal excessive number signal 6a, reference numeral WO denotes an output terminal of the temporary stop request signal 7a, reference numeral DRO denotes an output terminal of the buffer operation control signal 7b, and reference numeral LTO is an output terminal of the latch control signal 7c.

FIG. 2 is a block diagram showing a specific example of the circuit for monitoring the number of logic level change terminals. The logic level change terminal number monitoring circuit 6 includes an output state change detection circuit 61, a counting circuit 62, a threshold value setting circuit 63, and a comparison circuit 64.

The output state change detecting circuit 61 includes n exclusive OR circuits (exclusive OR circuits) 61 a to 61.
n. One of the input terminals of each of the exclusive OR circuits 61a to 61n is supplied with a logical level signal relating to the current output state, and the other input terminal is supplied with a logical level signal relating to the next output state. For example, one input terminal of the first exclusive OR circuit 61a is supplied with the logical level of the first bit of the current output, and the other input terminal is supplied with the logical level of the first bit of the next output. You. The exclusive OR circuits 61a to 61n generate an L-level output when the logic levels of the two inputs match, and generate an H-level output when the logic levels of the two inputs do not match. I do. Therefore, by performing an exclusive OR operation of the current output signal and the next output signal for each bit, when the output level changes, an H-level output is obtained.

The counting circuit 62 includes an output state change detecting circuit 6
A signal in which the outputs of the exclusive OR circuits 61a to 61n are at the H level based on the n-bit output state change detection result signal (the output signal of each of the exclusive OR circuits 61a to 61n) supplied from 1. , The number of terminals at which the output changes is determined, and the determined number of output change terminals (counting result) 6
2a is output.

The threshold setting circuit 63 stores a predetermined number of allowable logic level change terminals. The comparison circuit 64 compares the number 63a of allowable logic level change terminals supplied from the threshold value setting circuit 63 with the number of output change terminals (counting result) 62a output from the counting circuit 62 to determine the magnitude of the output change. If the number of terminals (counting result) 62a exceeds the logical level change allowable terminal number 63a, for example, H
The logic level change number excessive signal 6a is output.

The threshold value setting circuit 63 may be provided with a digital switch for setting the number of logical level change allowable terminals, and may be configured to change the number of logical level change allowable terminals. Alternatively, the threshold setting circuit 63 may not be provided, and the number of logic level change allowable terminals may be supplied from the outside. The comparison circuit 64 may be configured using a magnitude comparator circuit or the like.

FIG. 3 is a timing chart showing the operation of the output circuit shown in FIG. 3A shows a clock signal CLK, and FIG. 3B shows output signals 2a to 2a of the logic circuit unit 2.
2n, FIG. 3 (c) shows the latch control signal 7c, and FIG.
3D shows the latch output signals 5a to 5n, FIG. 3E shows the logic level change number excessive signal 6a, FIG. 3F shows the temporary stop request signal 7a, and FIG. 3G shows the buffer operation control signal. 7
FIG. 3H shows output signals of the output terminals 3a to 3n.

When the temporary stop request signal 7a is not supplied, the logic circuit unit 2 outputs the output signals 2a to 2n in synchronization with, for example, the rising edge of the clock signal CLK. The output buffer capability control circuit 7 generates a latch control signal 7c having a rising edge synchronized with, for example, a rising edge of the clock signal CLK except during a period in which the driving capability of the output buffer circuit 4 is reduced.

Output signal 2a output from logic circuit unit 2
2n are latched by the data latch circuit 5 in synchronization with, for example, the rising edge of the latch control signal 7c output from the output buffer capacity control circuit 7. The logic level change terminal number monitoring circuit 6 compares the latch output signals 5a to 5n with the output signals 2a to 2n of the logic circuit unit 2, and determines the number of terminals whose logic level changes between the current output state and the next output state. (The number of bits) is counted, and if the counting result exceeds a preset allowable number, the logic level change number excessive signal 6a
Is output.

Here, when changing from the logic level state A to the logic level state B, the number of terminals (bit number) at which the logic level changes is equal to or less than the allowable number, and the logic level state B changes to the logic level state C. In this case, the number of terminals (number of bits) at which the logic level changes exceeds the allowable number, and when changing from the logic level state C to the logic level state D, the number of terminals (bit number) at which the logic level changes is equal to or less than the allowable number. Shows the case. Therefore, during the period from time t2 to time t3, it is detected that the number of logic level change terminals becomes excessive when changing from the logic level state B to the logic level state C, and the number of logic level changes shown in FIG. An excessive signal 6a is output.

The output signals 2a to 2n of the logic circuit section 2 indicating the logic level state C are latched by the data latch circuit 5 based on the rise of the latch control signal 7c at time t3. Further, the logic circuit unit 2 outputs an output signal indicating the logic level state D to be output next, based on the rise of the clock signal CLK at time t3.

The output buffer capacity control circuit 7 operates at time t2
Based on the logic level change number excessive signal 6a generated during the period from time t3 to time t3, one cycle period of the next clock (time t3).
During a period from 3 to time t4), the CPU outputs the temporary stop request signal 7a, and outputs an L level buffer operation control signal 7b requesting buffer deactivation while the temporary stop request signal 7a is being output. As a result, the driving capability of the output buffer circuit 4 becomes small over the period from the time t3 to the time t4. Time t3 to time t4
During the period, since the driving capability is limited to a small value, the potential changes of the output terminals 3a to 3n change gradually.

As described above, when the number of terminals (the number of signal lines) at which the logic level changes is large, the drive capability of the output buffer circuit 4 is reduced, so that the output signal can be gradually changed. Electrical and magnetic high-frequency noise generated from a system, output terminals, wiring to a load, and the like can be reduced.

The logic circuit section 2 outputs the current output state (logical level state D) based on the temporary stop request signal 7a supplied from the output buffer capacity control circuit 7 between time t3 and time t4. Is held until time t5, and the next output state (logic level state E) is synchronized with the rising edge of the clock signal CLK at time t5.
Are output.

On the other hand, output buffer capacity control circuit 7 does not generate latch control signal 7c at time t4. Thereby, the data latch circuit 5 holds the logic level state C latched at the time t3. Then, at time t4, the output buffer capability control circuit 7 sets the buffer operation control signal 7b to the H level, and returns the drive capability of the output buffer circuit 4 to the large state. As a result, the time t
During the period from time 4 to time t5, the output signals of the output terminals 3a to 3n correspond to the logic level state C and have a potential whose logic level is sufficiently determined.

At time t5, output signals 2a to 2n to be output next are latched in data latch circuit 5, and output terminals 3a to 3n are output based on latch output signals 5a to 5n.
n is driven to logic level state D.

FIG. 4 is a block diagram showing a second embodiment of the output circuit according to the present invention. The output circuit 101 shown in FIG.
The input / output terminals 103a to 103n are output-driven based on the input / output terminals 103a to 103n, and data supplied to the input / output terminals 103a to 103n from other circuit units and devices (not shown) can be input to the logic circuit unit 102. It is.

The output circuit 101 includes a logic circuit section 102
Data latch circuit 105 for latching the parallel n-bit data outputs 102a to 102n output from the data output terminals of
5n, an output buffer circuit 104 for driving a plurality of input / output terminals 103a to 103n, a logic level change terminal number monitoring circuit 106, and an output buffer capacity control circuit 10.
7, the input buffer circuit 108, and the two-input AND circuit 1
09, an output undetermined state signal output buffer circuit 111 for driving the output undefined state signal output terminal 110, and a clock signal output buffer circuit 113 for driving the clock signal output terminal 112. Data latch circuit 10
5 and the logic level change terminal number monitoring circuit 106 are the same as the data latch circuit 5 and the logic level change terminal number monitoring circuit 6 shown in FIG.

The output buffer circuit 104 includes a plurality of sets (n sets) of drive circuits connected in parallel to a tri-state buffer circuit 104a having a small driving capability and a tri-state buffer circuit 104b having a large driving capability.

The logic circuit section 102 is a logic circuit section 10
2 to output a data output mode to the mode control terminal, an H level input / output mode control signal R / W is output. An L level input / output mode control signal R indicating a data input mode at a control terminal
/ W is output.

The input / output mode control signal R / W is supplied to the operation state control input terminal of the tri-state buffer circuit 104a having a small driving ability. Therefore, when the input / output mode control signal R / W is at the L level, the tri-state buffer circuit 104a having a small driving capability is in an inactive state. Further, the input / output mode control signal R / W is supplied to one input terminal of the two-input AND circuit 109. The buffer control operation signal 7b is supplied to the other input terminal of the two-input AND circuit 109. I / O mode control signal R / W
Is L level, the output of the 2-input AND circuit 109 is L
Level, and this L level is supplied to the operation state control input terminal of the tri-state buffer circuit 104b having a large driving capability, so that the tri-state buffer circuit 104b having a large driving capability enters a non-operating state. Since both the tri-state buffer circuits 104a and 104b are in a non-operating state, the output side of the output buffer circuit 104 is in a high impedance state.

The logic circuit section 102 includes the output buffer circuit 1
By controlling the input / output terminal 103 to the non-operation state,
Input data and the like supplied from other circuits and devices can be taken into the input buffers a to 103n via the input buffer circuit 108. The input buffer circuit 108 includes a plurality of sets (n sets) of input buffer circuits having a high input impedance.
Have.

In the data output mode, the input / output mode control signal R / W at the H level is output, so that the tri-state buffer circuit 104a having a small driving capability is activated. When the buffer operation control signal 7b is at the H level, the output of the two-input AND gate circuit 109 is at the H level, and this H level is supplied to the operation state control input terminal of the tri-state buffer circuit 104b having a large driving capability. High-performance tristate buffer circuit 10
4b is in operation. With both tri-state buffer circuits 104a and 104b operating,
The driving capability becomes large. Buffer operation control signal 7
By setting b to the L level, the tri-state buffer circuit 104b having a large driving capability can be set in a non-operating state, thereby switching to a state having a small driving capability.

The output buffer capacity control circuit 107 has the configuration shown in FIG.
, The output non-determined state signal 107d is generated in synchronization with the period in which the buffer control signal 7b is controlled to the L level, and the output non-determined state signal output terminal INH Output to The output indeterminate state signal 107d is supplied to an input terminal of the output indeterminate state signal output buffer circuit 111, and is output to the output indeterminate state signal output terminal 1 via the buffer circuit 111.
10 is driven. Other circuit units, devices, and the like (not shown) that receive output data supplied from the output circuit 101
By preventing output data from being received while the output non-determination state signal is supplied, it is possible to prevent reception of data whose logic level is not completely determined.

The output circuit 101 transmits the clock signal CLK to another circuit via a clock signal output buffer circuit 113 and a clock signal output terminal 112.
It can be supplied to a device or the like (not shown). Therefore, other circuit units, devices, and the like (not shown) can achieve synchronization in circuit operation such as adjusting the reception timing of output data based on the clock signal supplied through the clock signal output terminal 112. .

Output undefined state signal output buffer circuit 1
11 and clock signal output buffer circuit 113
Is the ability to change the output terminal and a load (not shown) connected to the output terminal (output load) connected to the output terminal to a predetermined logic level potential (load drive) in a sufficiently short time about 1/10 of the cycle of the clock signal. Ability).

The output capability of the output buffer circuit 104 is lowered by setting the buffer control signal 7b to L level instead of supplying the output indeterminate state signal 107d to another circuit section, device, or the like (not shown). The period is for other circuit parts,
By temporarily stopping the supply of the clock signal CLK to the devices and the like (not shown), the operation of other circuit units and devices and the like (not shown) is restricted during the period when the output capability of the output buffer circuit 104 is reduced. You may do so. In this case, the clock output line is used to transmit information during a period in which the output capability of the output buffer circuit 104 is reduced in the form of a missing clock. Therefore,
A signal line for transmitting the output indeterminate state signal 107d becomes unnecessary.

FIG. 5 is a block diagram showing a third embodiment of the output circuit according to the present invention. The output circuit 201 shown in FIG. 5 is different from the output circuit 10 shown in FIG.
Different from 1. The first difference is that the data latch circuit 205
, A data selector circuit 215 is provided at the preceding stage, and the output of the data latch circuit 205 is fed back to the input side of the data latch circuit 205 via the data selector circuit 215 to hold the output data of the data latch circuit 205. Is a point. The first difference is that the logic level information relating to the current output state is fetched via the input buffer circuit 108, so that the number of terminals at which the logic level changes even when switching from the input mode to the output mode is monitored. It is a point that can be done.

The clock signal CLK is supplied to the latch control signal input terminal LTI of the data latch circuit 205. Therefore, data latch circuit 205 latches the output of data selector circuit 215 based on clock signal CLK.

When the selection control signal 207e at the L level is supplied to the selection control signal input terminal SEL, the data selector circuit 215 selects and outputs the data outputs 102a to 102n supplied from the logic circuit unit 102. When the selection control signal 207e at the H level is supplied to the selection control signal input terminal SEL, the data selector circuit 215 selects and outputs the outputs 5a to 5n of the data latch circuit 205.

Therefore, when data selector circuit 215 selects and outputs outputs 5a-5n of data latch circuit 205, data latch circuit 205 outputs outputs 5a-5n of data latch circuit 205 based on clock signal CLK. Since the data is latched, the outputs 5a to 5n of the data latch circuit 205 retain the previously latched data without being changed.

FIG. 6 is a timing chart showing the operation of the output circuit shown in FIG. FIG. 6A shows the clock signal CLK, and FIG.
2n, FIG. 6 (c) shows the selection control signal 207e, and FIG.
6D shows the latch output signals 5a to 5n, FIG. 6E shows the logic level change number excessive signal 6a, FIG. 6F shows the temporary stop request signal 7a, and FIG. 6G shows the buffer operation control signal. 7
FIG. 6H shows the output signals of the output terminals 3a to 3n.

While the output buffer capacity control circuit 207 reduces the drive capacity of the output buffer circuit 104 based on the logic level change number excessive signal 6a (during the period from time t3 to time t4 shown in FIG. 6), As shown in FIG. 6 (c),
An H level selection control signal 207e is output. Based on the H level selection control signal 207e, the data selector circuit 215 outputs the outputs 5a to 5a of the data latch circuit 205.
n is selected and supplied to the data input terminal DI of the data latch circuit 205. Therefore, the data latch circuit 205
Are latched based on the rising edge of the clock signal CLK at time t4, which are the outputs 5a to 5n of the data latch circuit 205. Therefore, the data latch circuit 205 holds the data (logic level state C) latched earlier as it is.

In the output circuit 201 shown in FIG. 5, the output of the input buffer circuit 108 (parallel n-bit signal) is supplied to the current output logic level state input terminal group NOW of the logic level change terminal number monitoring circuit 206. I have. When the output circuit 201 is operating in the output mode, the output state driving the output terminals 103 a to 103 n via the output buffer circuit 104 changes to the current output logic level state input terminal group via the input buffer circuit 108. Since the signal is supplied to the NOW, the logic level change terminal number monitoring circuit 206 can compare the current output state with the next output state to monitor the number of terminals whose output state changes.

When the output circuit 201 is operating in the input mode (when the output buffer circuit 104 is in a non-operating state and its output side has a high impedance), it is supplied from another circuit or device (not shown). The current logic level state is supplied to the current output logic level state input terminal group NOW via the input buffer circuit 108. Accordingly, the logic level change terminal number monitoring circuit 206 can monitor the number of terminals whose output state changes by comparing the current state of the input / output terminal with the state to be output next.

Therefore, the output circuit 201 shown in FIG.
Even when switching from the input mode to the output mode, when the number of terminals at which the logic level changes is large, the driving capability of the output buffer circuit 104 is set to be small, and the transient current when switching from the input mode to the output mode is suppressed. In addition, the generation of high frequency noise can be prevented.

FIG. 7 is a block diagram of an SDRAM (synchronous dynamic random access memory) control device to which the output circuit according to the present invention is applied. SDRA
The M control device 400 includes an SDRAM control circuit 500 and 1
Alternatively, the output circuit 401 includes a plurality of SDRAM integrated circuits (SDRAM memory chips) 501 to 504 and an output circuit 401.
The output circuit 401 includes the SDRAM control circuit 500 and the SDR
SDR is provided between the AM integrated circuits 501 to 504 and
AM control circuit 500 and SDRAM integrated circuits 501 to 50
4 is passed.

The SDRAM control circuit 500 includes a clock signal generator, a sequencer, a data buffer, and the like. When a memory access request is supplied from a higher-level system (not shown) via a system bus 500a, the SDRAM control circuit 500 interprets the contents of the memory access request, and the SDRAM integrated circuit Various signal groups (control signals, address signals,
Data signal, etc.).

SDRAM control circuit 500 operates in synchronization with a clock having a predetermined period generated by a clock signal generation unit, and outputs clock signal CLK to output circuit unit 40.
1 and to each of the SDRAM integrated circuits 501 to 504 to synchronize the operation between the circuit units. SDRA
The M control circuit 500 sequentially generates and outputs various control signals, address signals, and the like in synchronization with the clock, unless the temporary stop request signal WAIT is supplied from the output circuit 401, and outputs the signals via the output circuit 401. Access is made to each of the SDRAM integrated circuits 501-504. SDRAM
When the suspension request signal WAIT is supplied, the control circuit 500 suspends generation of a new address signal and the like. In the present embodiment, the SDRAM control circuit 500
Is the clock 1 based on the pause request signal WAIT.
The control operation for memory access is suspended only for the period.

The SDRAM control circuit 500 supplies the output circuit 401 with threshold data TH for setting a monitoring condition for the number of logic level change terminals. The threshold data TH is data for designating the number of terminals (the number of logical level change allowable terminals) that can be tolerated when the output circuit 401 is performing a high-speed output operation with a large driving capability. The threshold data TH is stored in the system bus 500.
It can be set from the host system side via a.
Therefore, a suitable number of logic level change allowable terminals can be set in consideration of the number of SDRAM integrated circuits 501 to 504, the wiring length of various signal lines, and the like.

The SDRAM control circuit 500 is an SDRAM
In a write mode in which data is written to the integrated circuits 501 to 504 and an operation mode is set, for example, an H level write / read mode control signal R / W is output,
In a read mode in which data is read from the SDRAM integrated circuits 501 to 504, for example, an L level write / read mode control signal R / W is output. In the write mode, the SDRAM control circuit 500
The write data supplied from the host system or the like via the 00a and temporarily stored in the internal buffer unit or the like is sequentially output from the data output terminal group (data output). SDR
In the read mode, the AM control circuit 500 takes in data supplied to a data input terminal group (data input) and supplies the data to a host system or the like via the system bus 500a. The captured data may be temporarily stored in an internal buffer or the like, and then supplied to a host system or the like.

The SDRAM integrated circuits 501 to 504 include a control signal input terminal group CNT and an address signal input terminal group AD.
R, data input / output terminal group DQ, clock signal input terminal C
LKI and a clock enable signal input terminal CKEI. The control signal input terminal group CNT includes BA0, BA1,
It comprises various operation mode setting input terminals such as RAS, CAS, WE, and DQM, and various strobe signal input terminals for specifying a row address, a column address, and the like. The SDRAM integrated circuits 501 to 504 have a clock signal input terminal CKI.
Operates in synchronization with the clock signal CLK supplied to the clock signal CLK.
The SDRAM integrated circuits 501 to 504 validate various data during a clock period in which the clock enable signal CLE supplied to the clock enable signal input terminal CKEI is, for example, at L level. SDRAM integrated circuits 501-
Reference numeral 504 denotes a function of, when the clock enable signal CLE becomes H level, for example, in the next clock period after the clock period in which the H level becomes H level, even if various data are supplied, the data is ignored as invalid. Having.

In this embodiment, an SDRAM having an address bus width of, for example, 14 bits and a data bus width of 16 bits
S that includes four integrated circuits 501 to 504 and can be simultaneously accessed using two systems of chip enable (CS) signals
By dividing the DRAM integrated circuits 501 to 504 into groups of two, 32-bit data can be written or read by one access.

The output circuit 401 includes a control signal output terminal group 4
02, an output driver 412 that drives the output of the address signal output terminal group 403,
An output driver 413 for driving the data signal input / output terminal group 404, an output buffer circuit 414 for driving the clock enable signal output terminal 405, and an output buffer circuit 415 for driving the clock signal output terminal 406.
And an input buffer circuit 416 for inputting read data and the like supplied from the SDRAM integrated circuits 501 to 504 to the data signal input / output terminal group 404.

The output driving section 411 for driving the control signal output terminal group 402 includes a tristate buffer TB having a large output driving capability and a buffer SB having a small output driving capability.
And output drive units connected in parallel are provided for the number of control signal lines. The output drive unit 412 that drives the output of the address signal output terminal group 403 includes an output drive unit in which a tristate buffer TB having a large output drive capability and a buffer SB having a small output drive capability are connected in parallel. We only have minutes. The output driver 413 that drives the output of the data signal input / output terminal group 404 includes an output driver in which a tri-state buffer TB having a large output drive capability and a buffer SB having a small output drive capability are connected in parallel to a data signal line. Have only a few minutes.

The tri-state buffer TB having a large output driving capability is set to one cycle with respect to the cycle of the clock signal CLK.
A device having an ability to drive the output potential to a predetermined logic level potential in a sufficiently short time of about / 10 is used. A buffer SB having a small output drive capability and a tristate buffer STB having a small drive capability have a capability of changing the output potential to a predetermined logic level potential over a period of about one cycle of the clock signal CLK. ing. The output buffer circuit 414 that drives and outputs the clock enable signal output terminal 405 and the output buffer circuit 415 that drives and outputs the clock signal output terminal 406 have a sufficiently short time of about 1/10 of the cycle of the clock signal CLK. , Each having the ability to drive the output potential to a predetermined logic level potential.

The input buffer circuits 416 have the same number of input buffers IB as the number of data signal lines. The input buffer IB has a sufficiently high input impedance. The input terminal of each input buffer IB is connected to each terminal of the data signal input / output terminal group 404. The output terminal of each input buffer IB is connected to each data signal input terminal of the SDRAM control circuit 500. The read data and the like supplied to the data signal input / output terminal group 404 are supplied to each data signal input terminal of the SDRAM control circuit 500 via the input buffer IB.

The output circuit 401 includes a data latch circuit (DL) 421 for latching a control signal and a data selector circuit (DS) 422 for selecting an input signal of the data latch circuit (DL) 421. , Data latch circuit (DL) 42 for latching an address signal
3 and a data selector circuit (DS) 424 for selecting an input signal of the data latch circuit (DL) 421.
And a data latch circuit (DL) 425 for latching a data output signal, and the data latch circuit (DL) 4
And a data selector (DS) 424 for selecting 25 input signals.

Further, output circuit 401 latches logic level change terminal number monitoring circuit 431, output buffer capacity control circuit 432, and buffer capacity switching control signal (buffer operation control signal) BC in synchronization with clock signal CLK. D-type flip-flop circuit (FF) 433 for
Write / read mode control signal R / W is applied to clock signal CLK.
And a D-type flip-flop circuit (FF) 434 for latching in synchronism with.

The control signal CTS of a plurality of bits output from the SDRAM control circuit 500 is supplied to one input terminal group of the data selector circuit (DS) 422. Each output of the data selector circuit (DS) 422 is supplied to an input terminal group of the data latch circuit (DL) 421. Each output signal CTL of the data latch circuit (DL) 421 is supplied to each input terminal of the output driver 411. Each output signal CTL of the data latch circuit (DL) 421 is supplied to the other input terminal group of the data selector circuit (DS) 422.

When selection control signal SC supplied from output buffer capability control circuit 432 is at L level, data selector circuit (DS) 422 selects control signal CTS to input data to data latch circuit (DL) 421. When the selection control signal SC is at the H level, each output signal CTL of the data latch circuit (DL) 421 is selected and supplied to the input terminal group of the data latch circuit (DL) 421. The data latch circuit (DL) 421 latches each signal output from the data selector circuit (DS) 422 in synchronization with the clock signal CLK, and outputs the latched signal. Thus, when the selection control signal SC is at the L level, a new control signal CTS is latched, and when the selection control signal SC is at the H level, the previously latched control signal CTL is held.

The address signal AS of, for example, 14 bits output from the SDRAM control circuit 500 is supplied to one input terminal group of a data selector circuit (DS) 424. Each output of the data selector circuit (DS) 424 is supplied to an input terminal group of the data latch circuit (DL) 423. Each output signal AL of the data latch circuit (DL) 423
Is supplied to each input terminal of the output drive unit 412. Also, each output signal AL of the data latch circuit (DL) 423
Is supplied to the other input terminal group of the data selector circuit (DS) 424.

When the selection control signal SC supplied from output buffer capability control circuit 432 is at L level, data selector circuit (DS) 424 selects address signal AS and inputs data signal to data latch circuit (DL) 423. When the selection control signal SC is at H level, each output signal AL of the data latch circuit (DL) 423 is selected and supplied to the input terminal group of the data latch circuit (DL) 423. The data latch circuit (DL) 423 latches each signal output from the data selector circuit (DS) 422 in synchronization with the clock signal CLK, and outputs the latched signal. As a result, when the selection control signal SC is at the L level, a new address signal AS is latched. When the selection control signal SC is at the H level, the previously latched control signal AL is held.

The data output signal DO of, for example, 16 bits output from the SDRAM control circuit 500 is supplied to one input terminal group of a data selector circuit (DS) 426. Each output of the data selector circuit (DS) 426 is supplied to an input terminal group of a data latch circuit (DL) 425. Data latch circuit (DL) 425 Each output signal DB
Is supplied to each input terminal of the output drive unit 413. Also, each output signal DB of the data latch circuit (DL) 425
Is supplied to the other input terminal group of the data selector circuit (DS) 426.

When the selection control signal SC supplied from output buffer capability control circuit 432 is at L level, data selector circuit (DS) 426 selects data output signal DO and outputs data selection signal DO to data latch circuit (DL) 425. When the selection control signal SC is at the H level, each output signal DB of the data latch circuit (DL) 425 is selected and supplied to the input terminal group of the data latch circuit (DL) 425. The data latch circuit (DL) 425 latches each signal output from the data selector circuit (DS) 422 in synchronization with the clock signal CLK, and outputs the latched signal. Thereby, when the selection control signal SC is at the L level, a new data output signal DS is latched,
When the selection control signal SC is at the H level, the data output signal DB latched earlier is held.

The logic level change terminal number monitoring circuit 431 comprises:
The current output state is compared with the state to be output next. If the number of terminals at which the logic level changes exceeds the number of terminals specified by the threshold data TH, for example, a logic level change of H level An over-several signal OV is output. The logic level change terminal number monitoring circuit 431 is different from the logic level change terminal number monitoring circuit 6 shown in FIG.
3 is removed. As the current output state, the latched control signal CTL, the latched address signal AL, and the latched data output signal DB correspond to one input terminal group NOW of the logic level change terminal number monitoring circuit 431.
Supplied to The next state to be output is the control signal C
TS, the address signal AS, and the data output signal DO are supplied to the other input terminal group N of the logic level change terminal number monitoring circuit 431.
It is supplied to EXT.

The output buffer capacity control circuit 432, for example, when the H level logic level change number excessive signal OV is supplied, over one cycle period of the next clock at the time when the logic level change number excessive signal OV is supplied. For example, it outputs a H-level temporary stop request signal WAIT and outputs an L-level buffer capacity switching control signal (buffer operation control signal) BC over one cycle period of the next clock. Further, when the logic level change number excessive signal OV is supplied, the output buffer capability control circuit 432 sets the clock enable signal CKES to, for example, H level,
The level is held during the clock period when the logic level change number excessive signal OV is supplied.

The output buffer capacity control circuit 432
Indicates that the temporary stop request signal WAIT, the buffer capacity switching control signal (buffer operation control signal) BC, and the clock enable signal CKES start outputting from the point in time when the logic level change number excessive signal OV is supplied, and the output signals WAI
The output of each signal WAIT, BC, and CKES may be stopped after T, BC, and CKES are taken in by other circuit units in synchronization with the next clock signal CLK.

The suspension request signal WAIT is
It is supplied to a temporary stop request signal input terminal of the control circuit 500. The SDRAM control circuit 500 controls the suspension request signal W
When the AIT is supplied, the control operation for memory access is suspended for one period of the clock.

The buffer capacity switching control signal (buffer operation control signal) BC is a D-type flip-flop (FF) 43.
3 data input terminal. The D-type flip-flop (FF) 433 synchronizes with the clock signal CLK to switch the buffer capacity switching control signal (buffer operation control signal) BC
And outputs the latched signal. The buffer capacity switching control signal (buffer operation control signal) BCL latched by the D-type flip-flop (FF) 433 is the operating state of all the tri-state buffers TB in each of the output driving units 411, 412, and 413 having a large driving capacity. It is supplied to the control terminal.

Tri-state buffer TB operates when H level is supplied to the operation state control terminal (state in which output drive is performed in accordance with the logic level of the input signal).
When the L level is supplied to the operating state control terminal, a non-operating state (a state where the output side is set to high impedance) is used. Therefore, when the buffer capacity switching control signal (buffer operation control signal) BCL supplied via the D-type flip-flop (FF) 433 is at the H level, each of the output driving units 411, 412, and 413 has a large driving capacity. Tri-state buffer TB
And the buffer BF (or the tri-state buffer STB) having a small driving capability performs the output driving, so that the driving capability of each of the output driving units 411, 412, and 413 is in a large state.

Each output drive section 411, 412, 413
Buffer capacity switching control signal (buffer operation control signal) supplied via D-type flip-flop (FF) 433
When the BCL becomes L level, the output drive is performed only by the buffer BF (or the tristate buffer STB) having a small driving ability.
The drive capability of 2,413 is large. Therefore, each of the output driving units 411, 412, 4
13 can be switched.

The output buffer capacity control circuit 432
Recognizes that it is in the write state based on the write / read mode control signal R / W supplied from the SDRAM control circuit 500, and outputs the logical level change terminal excess signal O
When V is not supplied, a buffer capacity control signal BC of H level is output when
1, 412, 413 are controlled to be large. Then, when the logic level change terminal excess number signal OV is supplied, the output buffer capacity control circuit 432 sets the buffer capacity control signal BC to the L level for a predetermined period, so that each output drive unit 411, 412,41
3 is switched to a large driving capability. Accordingly, when the number of terminals at which the output logic levels of the output terminal groups 402 to 404 are inverted is a large number equal to or more than the allowable value, the driving capability is reduced and the logic level is changed over a relatively long time, for example, about one cycle. By changing, the transient current when the output logic level is inverted is suppressed, and the occurrence of high frequency noise accompanying the transient current is suppressed.

The clock enable signal CKES generated and output by the output buffer capability control circuit 432 is
It is supplied to an output buffer 414 having a large driving capability, and the clock enable signal C
Output as KE. Clock enable signal CKE
Is supplied to each clock enable signal input terminal CLKI of each of the SDRAM integrated circuits 501 to 504 via the clock enable signal output terminal 405.

Each of the SDRAM integrated circuits 501 to 504
The operation of taking in a control signal, a data signal and the like is stopped based on the clock enable signal CKE. Therefore, in a state where the driving potential of each of the output driving units 411, 412, and 413 is reduced and the output potential is changed over a relatively long time of about one cycle, a signal whose logic level is not sufficiently determined is generated. It is not taken into each of the SDRAM integrated circuits 501-504.

D-type flip-flop circuit (FF) 434
Latches write / read mode control signal R / W output from SDRAM control circuit 500 in synchronization with clock signal CLK, and latches write / read mode control signal RW
Is output. D-type flip-flop circuit (FF) 434
The write / read mode control signal RW, which is the latch output of
The signal is supplied to the operation state control terminal of the tri-state buffer STB having a small driving capability in the output driver 413. Since the write / read mode control signal R / W becomes H level at the time of writing, this H level is sent to the operation state control terminal of the tri-state buffer STB having a small driving capability via the D-type flip-flop circuit (FF) 434. By supplying the tri-state buffer STB having a small driving capability, the tri-state buffer STB can be brought into an operating state. At the time of reading,
Both tri-state buffers TB in the output driver 413,
Both STBs are controlled to be inactive. As a result, the output driver 413 has a high output impedance. Therefore, the SDRAM integrated circuit 5 is connected to the data input / output terminal group 404.
Input signals such as read data supplied from the 01 to 504 sides can be captured via the input buffer circuit 416.

The clock signal CLK supplied from the SDRAM control circuit 500 is supplied to each of the SDRAM integrated circuits 501 to 50 via the output buffer circuit 415 having a large driving capability.
4 clock signal input terminal CLKI.

FIG. 8 is a timing chart showing the operation of the SDRAM control device shown in FIG. 8A shows the clock signal CLK, and FIG. 8B shows the next output state (SD
Each output signal of RAM control circuit 500) CTS, AS, D
O, and FIG. 8C shows each data selector circuit 422, 42.
8 (d) shows the current output state (latch output of each latch circuit 421, 423, 425) CTL, A
L and DB are shown. FIG. 8E shows the logic level change number excessive signal OV, and FIG. 8F shows the temporary stop request signal WAI.
T, FIG. 8 (g) shows the buffer capacity switching control signal BC,
FIG. 8H shows a change state of output signals of the output terminal groups 402, 403, and 404, and FIG. 8I shows a clock enable signal CKE.

The SDRAM control circuit 500 operates as shown in FIG.
8 is not supplied (when the suspension request signal OV is at the L level) as shown in FIG.
Each signal CTS, AS, DO is output in synchronization with the rising edge of the clock signal CLK shown in FIG.

The output buffer capacity control circuit 432 keeps the L level unless the logic level change terminal excess signal OV is supplied.
It outputs a level selection control signal SC. Therefore, at time t1, each data selector circuit 422,
Reference numerals 424 and 426 select the output signals CTS, AS, and DO from the SDRAM control circuit 500, and these output signals CTS, AS, and DO are synchronized with the rising edge of the clock signal CLK, and the data latch circuits 421 are selected. ,
423 and 425 are latched. Each of the output driving units 411, 412, and 413 is connected to each of the data latch circuits 42.
Each output terminal group 402, 403, 404 is driven based on the latch outputs CTL, AL, DB of 1,423,425.

The output buffer capacity control circuit 432 outputs the H level unless the signal OV having an excessive number of logic level change terminals is supplied.
Since the buffer capacity switching control signal BC at the H level is output, the output driving units 411, 412, and 413 are set to have a large output driving capacity by the buffer capacity switching control signal BC at the H level. Therefore, at time t1
As shown in FIG. 8H, the output potentials of the output terminals 402 to 403 are driven to the logic level voltage corresponding to the output state A in a short time based on the output state A latched by.

In the clock cycle period from time t1 to time t2, the current output state A shown in FIG.
The output state B to be output next shown in (b) is compared by the logic level change terminal number monitoring circuit 431, and when the output state A transitions to the output state B, the number of terminals whose output logic level is inverted (signal The number of lines is counted. Here, since the number of terminals (number of signal lines) at which the output logic level is inverted when transitioning from the output state A to the output state B is equal to or smaller than the threshold value (allowable number), the logic level change terminal excess signal OV is No output.

Next clock cycle (time t2 to time t3)
Then, the output relating to the output state B is output, and the output state B is compared with the state C to be output next. Here, the number of terminals (the number of signal lines) at which the output logic level is inverted when transitioning from the output state B to the output state C exceeds the threshold (allowable number). Therefore, as shown in FIG. 8E, the logic level change terminal number monitoring circuit 431 outputs an H level logic level change terminal excess signal OV.

Output buffer capacity control circuit 432 receives the logic level change terminal excess signal OV, and in the next clock cycle period (time t3 to t4), the output buffer capacity control circuit 432 outputs the signal shown in FIG.
As shown in FIG. 8C, the selection control signal SC is set to the H level, and as shown in FIG.
Outputs AIT. The output buffer capacity control circuit 4
Reference numeral 32 denotes the next clock cycle period (time t3 to t4) to which the logic level change terminal excess signal OV is supplied.
As shown in FIG. 8 (g), the buffer capacity switching signal BC is set to L
By setting the level, the output drive units 411, 412, 4
13 is reduced. Further, the output buffer capability control circuit 432 sets the clock enable signal CKE to the H level as shown in FIG.

Since the driving capability of each output driver 411, 412, 413 is set to a small state, the output potential of each output terminal group gradually changes from output state B to output state C as shown in FIG. Change. If the number of terminals (number of signal lines) at which the output logic level is inverted is large, higher high-frequency noise will be generated due to transient current or the like, but the output drive capability should be reduced and the change in the output signal should be moderated. Thus, generation of high frequency noise can be reduced.

The SDRAM control circuit 500 operates as shown in FIG.
Since the control operation for memory access is interrupted for one period of the clock signal based on the temporary stop request signal WAIT shown in (1), the state in which the next output state D is output is held until time t5, and the time t5 Clock signal C at
The next output state E is output in synchronization with the rise of LK.

Each data selector circuit 422, 424, 4
26 is a latch output CT of each data latch circuit 421, 423, 425 based on the H level selection control signal SC.
L, AL, and DB are selected and each data latch circuit 421,
423 and 425 are fed back to the input terminals. Therefore,
Each of the data latch circuits 421, 423, and 425 operates at time t
4, the output of each data latch circuit 421, 423, 425 is latched at the rise of the clock signal CLK. As a result, the output state C latched at time t3 is held until time t5.

After time t4, each output driver 411,
In order to return to the state where the driving capability of 412, 413 is high,
During the period from time t4 to time t5, the potential state corresponding to the output state C is reliably driven.

On the other hand, each of SDRAM integrated circuits 501 to 50
4 is the clock signal C in the next clock period (time t3 to time t4) after the clock period (time t2 to time t3) in which the clock enable signal CKE is at the H level.
Without performing the data fetch operation in synchronization with LK, a signal whose logic level is not sufficiently determined is not taken into each of the SDRAM integrated circuits 501 to 504.

Therefore, SDRAM control apparatus 400 shown in FIG. 7 outputs data only when the number of output level inversion terminals is large (when large high-frequency noise is likely to be generated) when accessing SDRAM integrated circuits 501 to 504. The occurrence of high-frequency noise can be prevented by reducing the driving capability and suppressing the transient current. When the number of output level inversion terminals is small (when there is no possibility that large high-frequency noise is generated), high-speed output driving is performed with a large output driving capability. Therefore, it is possible to solve the problem of EMI (electromagnetic interference) while responding to a demand for faster access to the memory.

In this embodiment, an example has been described in which various signals are output in synchronization with the rising edge of the clock signal. However, a configuration may be employed in which various signals are output in synchronization with the rising edge of the clock signal. Further, various signals may be output in synchronization with one edge of the clock signal, and the signal receiving side may receive the output signal in synchronization with the other edge of the clock signal.

[0141]

As described above, the output circuit according to the present invention has a configuration in which the driving capability of the output circuit is switched in accordance with the number of terminals whose output level is inverted. In the case where the occurrence of high-frequency noise is small), it is possible to output data and the like at high speed while maintaining the output driving capability at a high level. And
Only when the number of output level inverting terminals is large (when there is a possibility that large high-frequency noise is generated), the output driving capability is reduced and the generation of high-frequency noise can be prevented by suppressing the transient current. Therefore, by applying the output circuit according to the present invention, it is possible to solve the problem of EMI (Electromagnetic Interference) while responding to the demand for high-speed circuit operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an output circuit according to the present invention.

FIG. 2 is a block diagram showing a specific example of a logic level change terminal number monitoring circuit.

FIG. 3 is a timing chart showing an operation of the output circuit shown in FIG.

FIG. 4 is a block diagram showing a second embodiment of the output circuit according to the present invention;

FIG. 5 is a block diagram showing a third embodiment of the output circuit according to the present invention;

FIG. 6 is a timing chart showing an operation of the output circuit shown in FIG.

FIG. 7 is an SDRAM to which the output circuit according to the present invention is applied.
It is a block diagram of a control device.

FIG. 8 is a timing chart showing an operation of the SDRAM control device shown in FIG. 7;

FIG. 9 is a circuit configuration diagram of a conventional address drive circuit.

FIG. 10 is a circuit configuration diagram of a conventional continuously variable output capability type driving circuit.

FIG. 11 is a circuit configuration diagram of a conventional drive capability switching type output circuit.

[Explanation of symbols]

1, 101, 201, 401 output circuit 2, 102 logic circuit section 3a to 3n output terminal 4, 104 output buffer circuit 5, 105, 205, 421, 423, 425 data latch circuit 6, 106, 206, 431 logic level change Terminal number monitoring circuit 7, 107, 207, 432 Output buffer capacity control circuit 41a to 41n Buffer circuit with small drive capacity 42a to 42n Tri-state buffer circuit with large drive capacity 61 Output state change detection circuit 62 Counting circuit 63 Threshold value setting Circuit 64 Comparison circuit 103 a to 103 n Input / output terminal 215, 422, 424, 426 Data selector circuit 400 SDRAM control device 411, 412, 413 Output drive unit 414, 415 Output buffer circuit with large drive capability 500 SDRAM control circuit 501-50 SDRAM integrated circuit SB tristate buffer TB drivability drivability is small buffer STB drivability is small is large tri-state buffer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J056 AA04 AA39 BB02 BB07 BB17 BB24 CC00 CC09 CC14 FF01 GG12 5J069 AA01 AA18 AA21 AA45 AA51 AA59 CA36 CA41 CA85 FA04 FA10 FA18 HA10 HA17 HA38 KA03 KA33 KA19

Claims (8)

[Claims] The present invention compares the current logic level state of a plurality of terminals with the next logic level state to be output to the plurality of terminals to determine the number of terminals whose logic level state changes, and obtains the number of terminals. A logic level change terminal that compares the number of terminals with a preset number of allowable logic level change terminals and indicates that the number of logic level change terminals is excessive when the obtained number of terminals exceeds the number of allowed logic level change terminals. An output, comprising: a logic level change terminal number monitoring circuit that outputs an excessive number signal; and an output buffer capacity control circuit that reduces the drive capability of the output buffer circuit based on the logic level change terminal number excess signal. circuit. 2. The output buffer circuit according to claim 1, wherein a buffer circuit having a small driving capability and a tri-state buffer circuit having a large driving capability are connected in parallel. 2. The output circuit according to claim 1, wherein the driving capability of the output buffer circuit is reduced by controlling the operation state. 3. The output buffer circuit comprises a parallel connection of a tri-state buffer circuit having a low driving capability and a tri-state buffer circuit having a high driving capability. By controlling the tri-state buffer circuit to a non-operating state, the driving capability of the output buffer circuit is reduced.
2. The output circuit according to claim 1, wherein the terminal is used as an input terminal by controlling each of the tri-state buffer circuits together with a non-operating state. 4. The number of terminals whose logic level state changes by comparing the current logic level state of the plurality of terminals with the next logic level state to be output to the plurality of terminals is determined, and the determined number is also determined. A logic level change terminal that compares the number of terminals with a preset number of allowable logic level change terminals and indicates that the number of logic level change terminals is excessive when the obtained number of terminals exceeds the number of allowed logic level change terminals. A logic level change terminal number monitoring circuit that outputs an excessive number signal, and a state in which the drive capability of the output buffer circuit is reduced based on the logical level change terminal excess signal and the drive capability of the output buffer circuit is reduced. An output buffer capacity control circuit for generating an output indeterminate state signal for inhibiting capture of an output signal in synchronization with the output signal. Road. 5. An output circuit for driving a plurality of terminal groups based on a plurality of bits of a parallel signal sequentially generated in synchronization with a clock from a logic circuit unit, wherein an output buffer circuit capable of varying output drive capability is provided. Comparing the current logic level state of the plurality of terminals with the logic level state to be output next to the plurality of terminals to determine the number of terminals whose logic level state changes, and the determined number of terminals A logic level change terminal excess signal indicating that the number of logic level change terminals is excessive when the calculated number of terminals exceeds the number of logic level change allowance terminals by comparing with a preset number of logic level change allowable terminals. A logic-level-change-terminal-number monitoring circuit that outputs a signal, and the drive capability of the output buffer circuit is reduced by a predetermined clock period based on the logic-level-change-terminal-excess signal. And generating a pause request signal for temporarily suspending the operation of the logic circuit unit in synchronization with the period in which the driving capability of the output buffer circuit is reduced, and further reducing the driving capability of the output buffer circuit. An output buffer capacity control circuit for generating an output indeterminate state signal for inhibiting capture of an output signal in synchronization with a period in which the output is performed. 6. The output buffer capacity control circuit generates and outputs a clock enable signal indicating whether the clock is valid or invalid as the output indeterminate state signal. Output circuit as described. 7. An output circuit for driving a plurality of terminal groups based on a plurality of bits of a parallel signal sequentially generated from a logic circuit section in synchronization with a clock, wherein an output buffer circuit capable of varying output drive capability is provided. Comparing the current logic level state of the plurality of terminals with the logic level state to be output next to the plurality of terminals to determine the number of terminals whose logic level state changes, and the determined number of terminals A logic level change terminal excess signal indicating that the number of logic level change terminals is excessive when the calculated number of terminals exceeds the number of logic level change allowance terminals by comparing with the preset number of logic level change allowable terminals. A logic-level-change-terminal-number monitoring circuit that outputs a signal, and the drive capability of the output buffer circuit is reduced by a predetermined clock period based on the logic-level-change-terminal-excess signal. Stopping the supply of the clock to the logic circuit unit for the predetermined clock period, thereby stopping the operation of the logic circuit unit for the predetermined clock period, and further, the signal output to the plurality of terminals is controlled by the clock. The other circuit unit outputs to the plurality of terminals during a period in which the driving capability of the output buffer circuit is reduced by stopping the supply of the clock to the other circuit unit in synchronization with the output for the predetermined clock period. An output buffer capacity control circuit for stopping the taking in of the output signal. 8. A data latch circuit for latching a plurality of bits of parallel signals sequentially generated from a logic circuit section in synchronization with a clock, and a plurality of terminals based on the plurality of bits of parallel signals latched by the data latch circuit. And an output buffer circuit capable of varying the output drive capability, and a plurality of parallel signals of a plurality of bits latched by the data latch circuit and a plurality of bits to be supplied next to the input side of the data latch circuit to be output next The number of terminals whose logic level status changes by comparing with the parallel signal of the number of terminals is determined, and the calculated number of terminals is compared with a predetermined number of allowable logic level change terminals. A logic level that outputs an excessive logic level change terminal number signal indicating that the number of logic level change terminals is excessive when the number of allowable terminals is exceeded. Change the terminal number monitoring circuit, output circuit, characterized in that an output buffer capacity control circuit to reduce the drive capacity of the output buffer circuit based on the logic level change number of terminals excessive signal.